LAB #1: Operational Amplifier

+ TABLE OF CONTENTS:
Part 1: Inverting and Non-Inverting Gain Configuration
Part 2: Gain-Bandwidth product relationship
Part 3: Frequency response limitation
Part 4: Transfer function measurement
Part 5: DC errors
+ ABSTRACT:
Lab 1 guides students through a methodical analysis of the operational
amplifier (specifically the LM741), and implementation of a variety of
applications of said technologies. Part 1 analyzes Inverting gain circuit with
regarded of the LM741 IC op amp, to determine bandwidth of amplifier as
well as the sign (phase shift) of the output relative to the input. Part 2
implements a change in circuit design so as to attain the gain of -500 for the
distinct purpose of investigating non-linear distortion know as clipping, and
the transfer function measurements. And then by disconnecting the input
source, we then figure out the DC offset error. Part 3 utilizes non-inverting
amplifier circuit which highlights similar properties like that of the inverting
amplifier. Part 4 is about using the operational amplifier for signal reading for
the circuit utilizing 2 external component which are the infrared LED LTE 302
and the photodiode LTR 516AD
+ EQUIPMENT:
-

IC operational amplifier : LM741

Resistors
LED LTE 302
LTR 516AD
Tektronix TDS 2004B Oscilloscope
Tektronix AFG 3021 Function Generator
Gwinstek GPS 3303 DC power supply
DMM

PART I: N-Channel and P-Channel Enhancement Mode

Parameters
INTRODUCTION
Part 1 utilizes 2 test circuits to discern process parameters for both a
NMOS and PMOS transistor in the MC14007 array. In each of the two circuit
configurations, a digital multimeter is used to measure the drain to source
resistance (rDS) at a variety of different gate voltages, as this resistance will
vary depending on the size of the conduction channel between the gate and
source, which is directly proportional to the gate voltage. These values are
then input into models intended to predict the value of r DS to calculate the
values for both process parameters, of kn(W/L) and the threshold voltage, Vt ,
for both the N-Channel and P-Channel MOSFETS, which serve as the building
blocks of the Complimentary-MOSFET (CMOS) logic inverter implemented in
parts 2 and 3.
Theoretical Basis
Differences in the MOSFET manufacturing processes, including physical
size, construction methods, and doping compounds used, result in different
process parameters, unique to each design, and possibly varying even
between identical models, due to manufacturing tolerances. The following
equation, derived from the saturation region estimation for the current
flowing through the drain of a MOSFET, provides a model for predicting the
drain-to source resistance of a MOSFET. The iteration seen here is specific to
NMOS transistors (indicated by n subscripts), as implemented in the circuit
in figure 1.1. The equation for r DSp (drain to source resistance of a PMOS
transistor) is identical to that for rDSn, except the n subscripts are replaced
with p subscripts, to specify the use of PMOS parameters and avoid
confusion.

rDSn = NMOS resistance between drain and source

kn(W/L) = Process parameter, based upon the size (W = width, L = length,
typically in m)
VGS = Gate to source voltage, or in this case, the voltage applied by the DC
power supply.
Vtn = Threshold voltage of NMOS, or the voltage at which the MOSFET turns
on, allowing current to flow between the drain and source.

Once the values of VGS and rDS are measured, the above equation can
be re-written into the form kn(W/L) = 1/[rDS(VGS Vt)], allowing for kn(W/L) to
be graphed as a function of Vt. When two of these functions are plotted on
the same x and y axes, the intersection point can be found on a standard
graphing calculator. The resulting x and y values of the intersection
represent the values of Vt and kn(W/L), respectively, that satisfy the
measured data points. This holds true for both the NMOS and PMOS test
circuits studied here.
CIRCUIT DESCRIPTION
NMOS test circuit
In this circuit, the voltage VGS, provided by the DC power supply, is
applied to the gate input of the NMOS device. This static voltage creates a
channel for conduction between the drain and source of the device. The size
of the N-channel, which varies directly proportionally with respect V GS,
dictates the observed rDSn, with a larger channel creating less resistance, as
more current can flow. Thus, it should be observed that r DS varies inversely
proportionally to VGS. The Digital Multi meter at the right of the figure is set
up to measure the value of rDSn when VGS = 2 V, 3 V, and 5 V. These gathered
data points are then used for calculation.

Figure 1.1: NMOS test circuit

PMOS test circuit

The circuit seen in figure 1.2 is identical in function to that of figure
1.1, except that the positive lead of the DC power supply feeds the source of
the PMOS device, and the negative lead feeds the gate, as is necessary to set
up a conduction channel between the P-type regions of the MOSFET. The
same test procedure as described for the NMOS circuit is then applied here,
to measure the corresponding rDSp values that result when Vs = 2 V, 3 V, and 5
V.

Figure 1.2: PMOS test circuit

EXPERIMENTAL RESULTS
For the NMOS test circuit, the following table was created by
measuring the value of rDSn, while VGS is adjusted to 2, 3, and 5 volts.
VGS
rDSn (k)
(Volts)
2
0.959
3
0.411
5
0.238
Two of the data points from this table were then selected and used to
estimate the values of the process parameters k n(W/L) and Vt. The two
points where VGS = 2 V and 3V were selected for graphical analysis, as
described in the Theoretical Basis section, due to their proximity in terms of
the independent variable, VGS. From analysis of these two points, the following
values were found for the NMOS device, which fall within the specified ranges
of 1 V < Vtn < 2 V and 0.5 < kn(W/L) < 1.5 mA/V2.
Vtn = 1.25 V
kn(W/L) = 1.39 mA/V2
Identical analysis was then performed on the PMOS test circuit, yielding the
results seen below.
VGS
(Volts)
2
3
5

rDSn (k)
3.127
0.821
0.437

Vtp = 1.64 V
kp(W/L) = 0.898 mA/V2

The threshold voltage of the PMOS device, Vtp, is observed to be

roughly 1.3 times the value of Vtn, whereas kn(W/L) is roughly 1.5 times the
value of kp(W/L). Thus, the PMOS device requires a higher threshold voltage,
though the NMOS device has larger process parameter. From these
relationships it can be deduced that the NMOS and PMOS devices contained
in the MC14007 IC are fairly unbalanced, likely due to differences in
construction, although the estimation method may not be extremely accurate
due to inconstancies in data acquisition.

PART 2: CMOS Logic Inverter

INTRODUCTION
In many modern digital circuits, it is necessary to invert a stream of
bits to perform logical computations, with each bit being a logical 1 or 0,
represented by a voltage of 5 V or 0 V, respectively. However, even digital
applications are rooted in analog circuitry. In the case of the logic inverter, a
CMOS, or Complimentary MOSFET, pair of MOSFETS is used, in which the
drains of a PMOS and CMOS device are tied together. Due to the capacitive
functionality of each MOSFET device, propagation delays are incurred, in
which there is a slight delay in the switch between logical states.
Furthermore, if logical devices are used in series, the capacitance across the
Gate and body of subsequent transistor devices will augment the propagation
delays, as explored in the later portion of part 2.
Theoretical Basis
Each MOSFET devices physical construction makes use of an insulator
between the Gate terminal and the body of the device, effectively forming a
capacitor. The ability of the device to conduct electricity between the drain
and source relies on this capacitance causing a channel of conductive
particles to be attracted to the space between the drain and source. Thus,
the formation of this channel is dependent on the gate/body capacitance
reaching a specified threshold of charge. In context of a CMOS logical
inverter, the critical value is the point at which the voltage output by the
circuit reaches the halfway point between a logical 1 and logical 0, which in
this case, is 2.5 V. With this knowledge, the following equations can be
derived from the theoretical model of a charging capacitor.

tPLH = rDSp * C * ln(2)

tPHL = rDSn * C * ln(2)
tPLH = propagation time from logical low to logical high value, reliant on r DSp,
the drain to source resistance of the PMOS device, through which the DC
supply will charge the
output node.
tPHL = propagation time from logical high to logical low value, reliant on r DSn,
the drain to source resistance of the NMOS device, through which the output
node will be shorted to ground.
C = capacitive load between Vout node and ground, representing the
subsequent circuitry
following the CMOS inverter.

CIRCUIT DESCRIPTION
CMOS Logic Inverter without Capacitive load
The circuit pictured in figure 2.1 consists of NMOS and PMOS devices,
with their drains connected to each other, forming a node at which V out is
measured. The 100 kHz, 0 to 5 V pk square wave signal from the function
generator at Vin represents a stream of logical 0s and 1s that could be
carrying information. The 5 V DC source connected to the source of the
PMOS device provides a reference voltage for Vout to modulate to when the
PMOS device is turned on, and the NMOS device is turned off (in the event of
a logical 0 on Vin).

Figure 2.1: CMOS Logic Inverter without Capacitive load

CMOS Logic Inverter with Capacitive Load

The circuit pictured in figure 2.2 is identical to that of figure 2.1,

except that a 100pF capacitive load is added between the node where V out is
measured and the ground reference. This simulates the effect of capacitive
loading due to additional circuitry components that may be found attached in
series with a CMOS logical inverter in practical applications.

Figure 2.2: CMOS Logic Inverter with 100pF Capacitive load

EXPERIMENTAL RESULTS
In figure 2.3, the yellow trace denotes the Vin signal for the circuit
shown in figure 2.1. The blue trace depicts the waveform observed at Vout,
which is a mirror image of the input signal, indicating that the CMOS logic
inverter is performing effectively. Although ideally HIGH V in = 5 V and LOW Vin
=0 V, Vin was measured to be a 5.44 V pk square wave at 100 kHz, with a low
value of LOW Vin = - 80 mV. For this input, the measured HIGH V out = 5.35 V
(which despite being 90 mV shy of the HIGH Vin, is still a logical 1), whereas
the measured LOW Vout = - 80 mV, showing that the circuit is effectively
outputting a logical 1 when a 0 is received on Vin, and vice versa, thus
meeting its functional objective.

Figure 2.3: Vin and Vout of CMOS logic inverter w/o capacitive load

Figure 2.4 depicts the input and output waveforms for the circuit
depicted in figure 2.2, in which a 100pF capacitive load is added to the CMOS
logical inverter, at the point of Vin transitioning from logical 0 to logical 1.
Figure 2.5 depicts the propagation delays present at the transition from
logical 1 to logical 0.

Figure 2.4: Vin and Vout of CMOS logic inverter showing t PHL

Figure 2.5: Vin and Vout of CMOS logic inverter showing t PLH
In comparison to the waveforms seen in figure 2.3, figure 2.4 and 2.5
show sizeable propagation delays, where no sizeable delays were observed in
the absence of the 100pF capacitive load. The calculations obtained during
the prelab utilized given values for process parameters k n(W/L), kp(W/L), and

Vt, which were used to find the theoretical value of r DSp = 615 (via the
equation described in part 1s theoretical basis). When these calculated
values were substituted into the equations described in part 2s theoretical
basis, the predicted tPLH = 42.6 nSec, and tPHL = 21.3 nSec. These values are
sizably smaller than the observed propagation delays, for which t PLH = 86.0
nSec, and tPHL = 68.0 nSec (as seen in figures 2.5 and 2.4, respectively), due
to the inconsistencies between the estimated drain to source resistances, and
the actual values shown by the MOSFETS.
Because of the propagation delays observed, the circuit does not
function instantaneously, as directed by the function goal. Particularly, due
to the 89 nSec delay in switching from logical 0 to logical 1, this CMOS
inverter would not be effective at processer speeds above 11MHz, assuming
a 100pF capacitive load, which is orders of magnitude slower than modern
computing applications. To improve the instantaneous performance of this
CMOS inverter, a higher voltage could be used to represent logical 1, as the
increased gate drive would lower the propagation delay. The propagation
delay could also be minimized by reducing the value of the capacitive load, C,
attached to the Vout node.

Simulation Versus Experimentation

The simulation seen in figure 2.6 (from prelab), depicts propagation delays
that are not equivalent to those measured in part 2, due to the use of given
values for MOSFET parameters, rather than measured values. Figure 2.7,
however, depicts the same simulation, but with the parameters determined in
part 1 in place of the given values. as a result, the propagation delays noted
in figure 2.7 are much closer to the observed values to t PLH = 89.0 nsec and
tPHL = 68.0 nSec.

Figure 2.6: Simulation of propagation delays with given values (from

prelab)

Figure 2.7: Simulation of propagation delays with observed values

from part 1

PART 3: Voltage Controlled Oscillator

INTRODUCTION
An important functional block in communication circuits is the voltage
controlled oscillator, or VCO. This block is an oscillator for which the output
frequency is controlled by a voltage. The type of VCO seen in part 3 is a ring
oscillator, in which an odd number of CMOS inverters are connected in series,

and the output is connected back to the input, effectively forming a ring. Due
to the odd number of inversions, there is no stable state for V out to achieve,
thus each inverter is constantly oscillating between a logical 1 and 0, at a
rate determined by the propagation delays of each inverter.
Theoretical Basis
The propagation delays of each inverting block are the only limiting
factor on the frequency of the VCO. If the delays of both the PMOS and NMOS
devices are identical and equal tPD, the resulting frequency for a ring of N
stages (where N is an odd number) is
f vco = 1 / N tPD. As noted in part 2,
the supply voltage, VDD, is a governing factor in the propagation delay.
Increasing VDD augments the gate drive to the MOSFETs, reducing r DSn and
rDSp, thus reducing the total propagation delay (as seen in part 2s theoretical
basis). Thus, adjusting VDD should allow for control of the VCOs frequency.
Circuit Description
Figure 3.1 depicts the VCO circuit architecture used in part 3, as 3
identical CMOS logic inverters connected in series, with the output linked
back to the input, and VDD provided by the DC power supply.

Figure 3.1: Filtered Full-wave Rectifier with Zener regulator

EXPERIMENTAL RESULTS
Figure 3.2 depicts the output frequency, in the order of MHz, of the
VCO against the input voltage, VDD. The values of VDD were confirmed with
the digital multimeter to be within 5 mV of the described value. Based on the
directly proportional relationship between V DD and the frequency of Vout, the
VCO is meeting the design goals described for part 3.

Figure 3.2: VCO output frequency in MHZ versus VDD

PART 4: Motor Speed Control with Pulse-Width

Modulation

INTRODUCTION
Pulse Width Modulation, or PWM, is a method of control for electronic
devices, in which power is supplied by a pulse train of varying duty cycle %,
rather than a DC signal. thus, the peak voltage delivered will always be the
same specified value, although the average power supplied to the device will
vary, depending on the percentage of on time of the pulse train, in relation
to its overall period. This method results in far more efficient drive circuitry
by reducing power losses. Part 4 investigates the use of PWM in controlling
the speed of a motor.
Theoretical Basis and Circuit Description
The duty cycle (% ON-time) of the control signal determines the
average DC voltage applied to the motor, thus controlling its speed. The
MOSFET switch has a low resistance when on (ideally 0) and a high
resistance when off (ideally infinite), thus very little power is dissipated in the
MOSFET during normal operation.
Figure 4.1 depicts the circuit used in part 4, in which the PWM signal
from the function generator turns the NMOS device on and off for time
intervals dependent on the duty cycle of the pulse train. When the MOSFET
is on, current flows from the 12 V DC source to ground. When the MOSFET if
off, the currents path to ground is blocked, thus the motor coasts. Thus, for
a 25% duty cycle, the motor is drawing power for 25% of the driving signals
period, and coasting for 75% of the period. Because the motor only increases
in speed while drawing current, thus the higher the percentage of the period
in which the driving signal is on, the faster the motor will spin.
The diode in the circuit of figure 4.1 is used as a free-wheeling diode
to provide a path for the current induced by the rotation of the motor (which
continues due to momentum) to flow during the time when the MOSFET is
off. Without this diode, a high voltage spike would occur across the MOSFET
during turn-off, possibly destroying the P-N junctions within the devices.

Figure 4.1: PWM Drive circuit for motor speed control.

Experimentation Versus Simulations

For 25% Duty Cycle:
Measurements identically match simulations, with Vin being a 25% duty cycle,
10 Vpk pulse train, and Vout being a 75% duty cycle, 12.5 Vpk pulse train for
both cases. Overshoot is also noted at transitional edges in the signals.

For 50% duty cycle:

Measurements identically match simulations, with Vin being a 50% duty
cycle, 10 Vpk pulse train, and Vout being a 50% duty cycle, 12.5 Vpk pulse
train for both cases. Overshoot is also noted at transitional edges in the
signals.

For 75% Duty Cycle:

Measurements identically match simulations, with Vin being a 75% duty cycle,
10 Vpk pulse train, and Vout being a 25% duty cycle, 12.5 Vpk pulse train for
both cases. Overshoot is also noted at transitional edges in the signals.

Summary of Lab 4

Lab 4 covered a vast range of MOSFET theory and application. The

highlighted relationships between the process parameters of NMOS and
PMOS devices, and the propagation delays that result, concisely tie together
the family of equations that were taught in lecture. Furthermore, through the
VCO implementation example, the use of propagation delays to meet
functionality requirements was illustrated excellently, providing an
observable change in output frequency, as caused by timing delays that are
otherwise far to small for humans to detect, in the order of nanoseconds. The
final example of PWM as motor speed control provided an observable
example of a control method that is used everywhere, from lighting, to class
D amplification, while backing up perceived changes in speed with simulation
and oscilloscope measurements.