DOWNLINK

4.615 ms (1 TDMA Frame)

->>>>

577 us

OMCR -->

MS1

MS2/ MS3

BCC

SDC

TCH

TCH

TCH

TCH

TCH

TCH

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

These TSs (0 -> 7) will take the foll. Forms each 4.615 ms

120 ms
235.365 ms

TDMA Frame 0

FCH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 1

SCH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 2

BCCH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 3

BCCH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 4

BCCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 5

BCCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 6

PAGCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 7

PAGCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 8

PAGCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 9

PAGCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 10

FCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 11

SCH

SDCCH(2)

TCH/F

TCH/H

PAGCH

SDCCH(3)

SACCH

SACCH for
MS2

TDMA Frame 13

PAGCH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 14

PAGCH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 15

PAGCH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 16

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 17

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 18

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 19

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 20

FCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 21

SCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 22

PAGCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 23

PAGCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 24

PAGCH

SDCCH(6)

TCH/F

TCH/H

PAGCH

SDCCH(6)

IDLE

SACCH for
MS3

TDMA Frame 26

PAGCH

SDCCH(6)

TCH/F

TCH/H

TDMA Frame 27

PAGCH

SDCCH(6)

TCH/F

TCH/H

TDMA Frame 28

PAGCH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 29

PAGCH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 12

TDMA Frame 25

ms
TDMA Frame 30

FCH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 31

SCH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 32

PAGCH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 33

PAGCH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 34

PAGCH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 35

PAGCH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 36

PAGCH

SACCH(1)

TCH/F

TCH/H

TDMA Frame 37

PAGCH

SACCH(1)

TCH/F

TCH/H

PAGCH

SACCH(1)

SACCH

SACCH for
MS2

TDMA Frame 39

PAGCH

SACCH(1)

TCH/F

TCH/H

TDMA Frame 40

FCH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 41

SCH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 42

PAGCH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 43

PAGCH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 44

PAGCH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 45

PAGCH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 46

PAGCH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 47

PAGCH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 48

PAGCH

IDLE

TCH/F

TCH/H

TDMA Frame 49

PAGCH

IDLE

TCH/F

TCH/H

TDMA Frame 50

IDLE

IDLE

TCH/F

TCH/H

FCH

SDCCH(0)

IDLE

SACCH for
MS3

TDMA Frame 52

SCH

SDCCH(0)

TCH/F

TCH/H

TDMA Frame 53

BCCH

SDCCH(0)

TCH/F

TCH/H

TDMA Frame 54

BCCH

SDCCH(0)

TCH/F

TCH/H

TDMA Frame 55

BCCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 56

BCCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 57

PAGCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 58

PAGCH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 59

PAGCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 60

PAGCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 61

FCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 62

SCH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 63

PAGCH

SDCCH(3)

TCH/F

TCH/H

PAGCH

SDCCH(3)

SACCH

SACCH for
MS2

TDMA Frame 65

PAGCH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 66

PAGCH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 67

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 68

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 69

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 38

TDMA Frame 51

TDMA Frame 64

TDMA Frame 70

PAGCH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 71

FCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 72

SCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 73

PAGCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 74

PAGCH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 75

PAGCH

SDCCH(6)

TCH/F

TCH/H

TDMA Frame 76

PAGCH

SDCCH(6)

TCH/F

TCH/H

PAGCH

SDCCH(6)

IDLE

SACCH for
MS3

TDMA Frame 78

PAGCH

SDCCH(6)

TDMA Frame 79

PAGCH

SDCCH(7)

TDMA Frame 80

PAGCH

SDCCH(7)

TDMA Frame 81

FCH

SDCCH(7)

TDMA Frame 82

SCH

SDCCH(7)

TDMA Frame 83

PAGCH

SACCH(4)

TDMA Frame 84

PAGCH

SACCH(4)

TDMA Frame 85

PAGCH

SACCH(4)

TDMA Frame 86

PAGCH

SACCH(4)

TDMA Frame 87

PAGCH

SACCH(5)

TDMA Frame 88

PAGCH

SACCH(5)

TDMA Frame 89

PAGCH

SACCH(5)

TDMA Frame 90

PAGCH

SACCH(5)

TDMA Frame 91

FCH

SACCH(6)

TDMA Frame 92

SCH

SACCH(6)

TDMA Frame 93

PAGCH

SACCH(6)

TDMA Frame 94

PAGCH

SACCH(6)

TDMA Frame 95

PAGCH

SACCH(7)

TDMA Frame 96

PAGCH

SACCH(7)

TDMA Frame 97

PAGCH

SACCH(7)

TDMA Frame 98

PAGCH

SACCH(7)

TDMA Frame 99

PAGCH

IDLE

TDMA Frame 100

PAGCH

IDLE

TDMA Frame 101

IDLE

IDLE

TDMA Frame 77

so, each TS (e.g.SDCCH) will repeat after 4.615 ms - 577 us

26 Frame Traffic Channel MF

TCH

51 Frame Control Channel MF

BCC

51 Frame Control Channel MF

SDC

Every TCH & SDCCH has one SACCH

associated with it.
Four PAGCH TSs = one CCCH block, so
9 CCCH block in DL for paging and access
Through parameters, we can set e.g.
2 blocks for AGCH and 7 blocks for PCH
in each 51 frame MF

One "PCH block" corresponds to one

"paging subgroup" if repeated after 'n'
51 frame MFs called a ''paging cycle"
e.g. n=8

1 paging cycle contains 1 paging

block of each paging group

first FCH occupies TS0 then SCH in next frame, then BCCH
completed in 102 frames

UPLINK
4.615 ms

(e.g. each RACH TS will be received in 4.615 ms)

577 us

OMCR -->

MS1

MS2/ MS3

120 ms
235.365 ms

BCC

SDC

TCH

TCH

TCH

TCH

TCH

TCH

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

TDMA Frame 0

RACH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 1

RACH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 2

RACH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 3

RACH

SDCCH(0)

TCH/F

TCH/H

TCH

TCH

TCH

TCH

TDMA Frame 4

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 5

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 6

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 7

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 8

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 9

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 10

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 11

RACH

SDCCH(2)

TCH/F

TCH/H

RACH

SDCCH(3)

SACCH

SACCH for
MS2

TDMA Frame 13

RACH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 14

RACH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 15

RACH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 16

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 17

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 18

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 19

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 20

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 21

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 22

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 23

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 24

RACH

SDCCH(6)

TCH/F

TCH/H

RACH

SDCCH(6)

IDLE

SACCH for
MS3

TDMA Frame 26

RACH

SDCCH(6)

TCH/F

TCH/H

TDMA Frame 27

RACH

SDCCH(6)

TCH/F

TCH/H

TDMA Frame 28

RACH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 29

RACH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 30

RACH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 31

RACH

SDCCH(7)

TCH/F

TCH/H

TDMA Frame 12

TDMA Frame 25

TDMA Frame 32

RACH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 33

RACH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 34

RACH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 35

RACH

SACCH(0)

TCH/F

TCH/H

TDMA Frame 36

RACH

SACCH(1)

TCH/F

TCH/H

TDMA Frame 37

RACH

SACCH(1)

TCH/F

TCH/H

RACH

SACCH(1)

SACCH

SACCH for
MS2

TDMA Frame 39

RACH

SACCH(1)

TCH/F

TCH/H

TDMA Frame 40

RACH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 41

RACH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 42

RACH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 43

RACH

SACCH(2)

TCH/F

TCH/H

TDMA Frame 44

RACH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 45

RACH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 46

RACH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 47

RACH

SACCH(3)

TCH/F

TCH/H

TDMA Frame 48

RACH

IDLE

TCH/F

TCH/H

TDMA Frame 49

RACH

IDLE

TCH/F

TCH/H

TDMA Frame 50

RACH

IDLE

TCH/F

TCH/H

RACH

SDCCH(0)

IDLE

SACCH for
MS3

TDMA Frame 52

RACH

SDCCH(0)

TCH/F

TCH/H

TDMA Frame 53

RACH

SDCCH(0)

TCH/F

TCH/H

TDMA Frame 54

RACH

SDCCH(0)

TCH/F

TCH/H

TDMA Frame 55

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 56

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 57

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 58

RACH

SDCCH(1)

TCH/F

TCH/H

TDMA Frame 59

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 60

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 61

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 62

RACH

SDCCH(2)

TCH/F

TCH/H

TDMA Frame 63

RACH

SDCCH(3)

TCH/F

TCH/H

RACH

SDCCH(3)

SACCH

SACCH for
MS2

TDMA Frame 65

RACH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 66

RACH

SDCCH(3)

TCH/F

TCH/H

TDMA Frame 67

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 68

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 69

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 38

TDMA Frame 51

TDMA Frame 64

TDMA Frame 70

RACH

SDCCH(4)

TCH/F

TCH/H

TDMA Frame 71

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 72

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 73

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 74

RACH

SDCCH(5)

TCH/F

TCH/H

TDMA Frame 75

RACH

SDCCH(6)

TCH/F

TCH/H

TDMA Frame 76

RACH

SDCCH(6)

TCH/F

TCH/H

RACH

SDCCH(6)

IDLE

SACCH for
MS3

TDMA Frame 78

RACH

SDCCH(6)

TDMA Frame 79

RACH

SDCCH(7)

TDMA Frame 80

RACH

SDCCH(7)

TDMA Frame 81

RACH

SDCCH(7)

TDMA Frame 82

RACH

SDCCH(7)

TDMA Frame 83

RACH

SACCH(4)

TDMA Frame 84

RACH

SACCH(4)

TDMA Frame 85

RACH

SACCH(4)

TDMA Frame 86

RACH

SACCH(4)

TDMA Frame 87

RACH

SACCH(5)

TDMA Frame 88

RACH

SACCH(5)

TDMA Frame 89

RACH

SACCH(5)

TDMA Frame 90

RACH

SACCH(5)

TDMA Frame 91

RACH

SACCH(6)

TDMA Frame 92

RACH

SACCH(6)

TDMA Frame 93

RACH

SACCH(6)

TDMA Frame 94

RACH

SACCH(6)

TDMA Frame 95

RACH

SACCH(7)

TDMA Frame 96

RACH

SACCH(7)

TDMA Frame 97

RACH

SACCH(7)

TDMA Frame 98

RACH

SACCH(7)

TDMA Frame 99

RACH

IDLE

TDMA Frame 100

RACH

IDLE

TDMA Frame 101

RACH

IDLE

TDMA Frame 77

26 Frame Traffic Channel MF

TCH

51 Frame Control Channel MF

BCC

51 Frame Control Channel MF

SDC

1 Burst =

1 TS

only RACH received by BTS in uplink

completed in 102 frames

Superframes
Hyperframes

1326 TDMA frames (26 x51)

2048 superframes

6.12 sec = 51 (26 Frame) or 26 (51 Frame ) MF

3 hr 28 min 53 sec 760 ms

Important
It is not by accident that the control channel multiframe is not a direct multiple of the
traffic channel multiframe. From the diagram, it can be seen that any given frame
number will only occur simultaneously in both multiframes every 1326 TDMA frames (26
x 51). This number of TDMA frames is termed a superframe and it takes 6.12 s to
transmit. This arrangement means that the timing of the traffic channel multiframe is
always moving in relation to that of the control channel multiframe and this enables a MS
to receive and decode BCCH information from surrounding cells.
If the two multiframes were exact multiples of each other, then control channel timeslots
would be permanently masked by traffic channel timeslot activity. This changing
relationship between the two multiframes is particularly important, for example, to a MS
which needs to be able to monitor and report the RSSIs of neighbour cells (it needs to be
able to see all the BCCHs of those cells in order to do this).
The hyperframe consists of 2048 superframes, this is used in connection with ciphering
and frequency hopping. The hyperframe lasts for over three hours, after this time the
ciphering and frequency hopping algorithms are restarted.

SACCH Multiframe - SACCH TSs in four consecutive 26-Frame TCH MFs or two 51 frame SDCCH MFs
As the MS only transmits or receives its own physical channel (normally containing TCH
and SACCH) for one-eighth of the time, it uses the remaining time to monitor the BCCHs
of adjacent target cells.
It completes the process every 480 ms, or four 26-TCH MFs. (104 consecutive assigned TS) in dedicated
mode and 470.73 ms in idle mode ( 2 51-frame MFs)
The message that it sends to the BSS (on SACCH, uplink) contains the
RxLev, RxQual, RxLev_ncell(n)
The measurements are made over each SACCH multiframe, which is 104 TDMA frames (480 ms)
for a TCH and 102 TDMA frames for an SDCCH (idle & dedicated modes respectively)
1 SACCH message = 4 SACHH TSs = complete measurement report

Transmission Timing
To simplify the design of the MS, the GSM specifications specify an offset of three
timeslots between the BSS and MS timing, thus avoiding the necessity for the MS to
transmit and receive simultaneously.
Timing Advance TA
The synchronization of a TDMA system is critical because bursts have to be transmitted
and received within the real time timeslots allotted to them.
The GSM BTS caters for this problem by instructing the MS to advance
its timing ((that is, transmit earlier) to compensate for the increased propagation delay.
This advance is then superimposed upon the three timeslot nominal offset.
This advance is then superimposed upon the three timeslot nominal offset.
The maximum timing advance is approximately 233 s. This caters for a maximum cell
radius of approximately 35 km.
BTS-MS
TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

TS0

TS1

TS2

TS3

TS4

MS-BTS
- TA

TS5

TS6

TS7

1TS
1TS
1 bper
156.25 bper
s=v x t
v
t
s

577
156.25
3.6928
577

micro sec (15/26)

bits
micro sec 577/156.25
micro sec

3.00E+08 m/s
5.77E-04 sec
1.73E+05 m

or 1 TS or 156.25 bper
or 173 km

468.75