Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Small Cells
China Small Cell Symposium
Oct 2012
Zhihong Lin
Strategic Marketing Manager, Multicore Processors
Texas Instruments
Samsung
HTC
In 2016, 4G will be 6 percent of connections, but 36 percent of total traffic. In 2016, a 4G connection
will generate 9 times more traffic on average than a non-4G connection. --- Cisco VNI Mobile, 2012
300Mbps LTE
42Mbps HSDPA
384Kbps
Rel99
14Mbps
Rel 6
HSPA
1Gbps LTE-A
168Mbps HSDPA
300Mbps LTE
84Mbps HSDPA
28Mbps
Rel 7
HSPA+
Rel 8
LTE
2000
2005
2007
2008
2009
2011-2012
HetNet Challenges
More small cells
= more interference
Macro Cell
Interference
Enhanced inter-cell
interference
coordination (eICIC)
8x8 DL MIMO
4x4 UL MIMO
Enhanced SU- MUMIMO
Using multiple
eNodeB point joint
TX and/or RX
to/from a single UE
HetNet load
balancing, offload
macro cell traffic into
small cell
Improves peak
spectral efficiency
CoMP Set
(CA)
Up to 5 carriers
and 100MHz BW
Improves peak
data rate
CC1
CC2
10M
Hz
10M
Hz
Scheduler
Hz
Hz
Mux
Non-Contiguous Carrier
1
UE1
8
eNodeB
Scheduler
20Mhz
CW1
UE1 Channel
coding CW2
Data Modulation
UE1
UE2
Data
Mux
CW1
Channel
coding
Modulation
eNodeB
CW2
Precoding
Carrier CC2
10M
separation
10M
CC1
Precoding
Contiguous Carrier
DL SU-MIMO
CRE
UE1
Pico eNodeB
UE connects to macro
eNodeB without CRE and to
pico eNodeB with CRE
UE does not connect
to strongest cell with CRE
Signal
UE2
DL MU-MIMO
Carrier Aggregation
Signal
Macro eNodeB
Motivation
Implementation
Complexity
Frequency Band
Carrier Aggregation
CoMP
CoMP Set
Signal
Signal
eICIC
CRE
Complexity
Pico eNodeB
UE connects to macro
eNodeB without CRE and to
pico eNodeB with CRE
UE does not connect
to strongest cell with CRE
Macro eNodeB
High performance
low power
processing horse
power
Low latency
memory access to
eliminate latency
bottlenecks
Sufficient on chip
throughput for
LTE-A data rates
Small Cell
SoC
Architecture
High level of
integration for
small footprint
and energy
efficiency
KeyStone
Small cell
System
on
Chip
TX / RX
Antenna
System Control
O & M/Processing
Transport/Security
Processing
MAC/PHY
Digital Front End
TI Software Investment
Transport
L2, L3, L4
Baseband
Processing
Baseband
Processing
Digital
Front End
Digital
Front End
Analog
Front end
Analog
Front end
Power
Amplifier
Low Noise
Amplifier
Antennas
Antennas
Downlink
User Equipment
Uplink
+ * +
- << - DSP Cores
ARM shared L2
Large on chip
memory and
Low latency
external
memory access
DSP L2
EMIF
I2C
Power Mgr
SysMon
Debug
EDMA
Layer 1 Acceleration
Radio processing
High
throughput
zero copy, low
latency SoC
infrastructure
TeraNet
High
performance
low power
cores for
sufficient small
cell processing
DDR3 L
64/72b
SPI
UART
Ethernet Switch
USIM
USB 3
CPRI/OBSAI
JESD204B
Ethernet
JESD204B High Speed Serial data converter interface enabling LTE high data rate
9.8Gbps CPRI 5.0 with support LTE-A carrier aggregation
multiport ethernet with build in switch reduce data transfer latency
Multi-RAN
layer 1
acceleration
power and
area efficient
Digital radio
front end,
eliminate extra
FPGA for data
converters
interface, DPD
enables PA
efficiency and
reduces overall
system power
Layer 2, 3,
transport
acceleration, on
chip Ethernet
switch, reduce
BoM and
transport
latency
Conclusion
High end LTE enabled smart devices will continue
to drive the data demands on the mobile
networks
Thank You!