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Section 6.1
Let us consider the amplifier in Fig. 6.1. This is an ordinary amplifier which is not
cascoded. We first perform some experiments so that we can understand how it
should be improved.
6-1
VDD
RL 1
1
11
0
3.3V
300k
.param W1=5u
M1 11 2
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG 2
Vin 4
VDS
4
0
11
0.6v
0V
0
0V
.DC VDS 0
3.3V 0.1V
.PROBE I(M1) I(RL)
.end
IDS1
Fig. 6.1-2 The I-V curve and its load line of M1 in Fig 6.1-1
In this section, we should introduce a new kind of amplifier, called the cascode
amplifier. Fig. 6.1-3 shows such a typical amplifier. In a cascode amplifier, two
NMOS transistors are connected together. One is on top of the other.
6-2
1
1
0
11
3.3V
300k
.param
M2
W1=5u
11 2
3
6-3
I(M2)
VOUT
Fig. 6.1-4 The I-V curve of the cascoded transistor
To understand why the I-V curve is much flatter and its current much smaller in a
cascode amplifier, let us redraw a non-cascode amplifier and a cascoded amplifier
together in Fig. 6.1-5.
6-4
6-5
Let us pay attention to V DS1 and ask the following questions: Suppose RL
changes, Vout will of course change. Will V DS 1 also change? The answer is no.
Note that I DS 2 remains the same as long as M2 is in the saturation region. This
means that VGS 2 has to remain roughly the same. Thus V DS 1 has to be roughly the
same because V DS 1 VG 2 VGS 2 and VG 2 is a constant. On the other hand,
Vout VDS 2 VDS 1 . If Vout changes, VDS 2 may change as V DS 1 remains
unchanged.
Experiment 6.1-3 Comparing the I-V Curves of the Two Amplifiers, the NonCascoded and the Cascoded, Shown in Fig. 6.1-5
The program for the cascoded amplifier is shown in Table 6.1-3, that for the noncascoded one is shown in Table 6.1-4 and the results are shown in Fig. 6.1-7. As can
be seen from Fig. 6.1-7, the current in the cascoded amplifier is much smaller than
that in the non-cascoded one.
Table 6.1-3 Program for the cascoded amplifier
Cascoded Amplifier
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
RL
1
1
0
11
3.3V
500k
.param W1=5u
M2
11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1
3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2
2 0
1v
6-6
VGS1
0v
Vin
6
0
0
Vout
11 0
0
.DC Vout 0 3.3v 0.1v SWEEP VGS1 0 3.3v 0.1v
.PROBE I(M1) I(M2) I(RL)
.end
Table 6.1-4 Program for the non-cascoded amplifier
Non-cascode Amplifier
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
RL
1
1
0
11
3.3V
500k
.param W1=5u
M1
11 2
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG
2
4
0v
Vin
4
0
0V
VDS1
11 0
0V
.DC VDS1
0
3.3V 0.1V SWEEP VG 0 3.3v 0.1v
.PROBE I(M1) I(RL)
.end
6-7
Cascoded
Vout
NonCascodedd
Vout
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
RL
1
1
0
11
3.3V
500k
.param W1=5u
M2
11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1
3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2 2 0
VGS1
4
2v
6
Vin 6
Vout 11
0
0
0
0
0v
6-9
Vout
Fig. 6.1-8 The I-V curves for a higher VG 2
Experiment 6.1-5 The Decrease of VG2
In this experiment, we reduced VG 2 from 1V to 0.8V. This will further put a
higher constraint for V DS 1 to grow and the highest current was decreased from
0.3mA to 0.09mA, as shown in Fig. 6.1-9. The program is shown in Table 6.1-6.
Table 6.1-6 Program for Experiment 6.1-5
Ex6.1-5 Cascoded
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
RL
1
1
0
11
3.3V
500k
.param W1=5u
M2
11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1
3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
6-10
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2
VGS1
2
4
0
6
0.8v
0v
Vin
Vout
6
11
0
0
0
0
Vout
Fig. 6.1-9 The I-V curves for a lower VG 2
Experiment 6.1-6 The Comparison of Input/Output Curves for Non-Cascoded
Amplifiers and Cascoded Amplifiers
We draw the two amplifiers in Fig. 6.1-10. This experiment is to see the
difference between Input/Output curves for non-cascoded and cascoded amplifiers.
The program for testing the non-cascoded amplifier is in Table 6.1-7 and its result is
in Fig. 6.1-11 The program for testing the cascoded amplifier is in Table 6.1-8 and the
result is in Fig. 6.1-12. We can see that the input-output is much shaper for the
cascode amplifier than that for the non-cascoded amplifier.
6-11
1
11
0
3.3V
500k
.param W1=5u
M1 11 2
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG 2
0
0
.DC VG 0 3.3v 0.1v
.end
6-12
Vout
VGS1
Fig. 6.1-11 The input/output curve of the non-cascoded amplifier
Table 6.1-8 Program to obtain the VGS 1 / Vout curve for the cascoded amplifier
Example 6.1-6 Cascode Case
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
RL 1
1
11
0
3.3V
500k
.param W1=5u
M2 11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1 3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2
1v
6-13
VGS1
VOUT
VGS1
Fig. 6.1-12 The input/output of the cascoded amplifier
Experiment 6.1-7 The Changing of VDS 2 , VDS 1 and I DS1 as RL Changes
In this experiment, we increased R L from 100k to 500k. The purpose was
to examine how VDS 2 , VDS 1 and I DS 1 change when RL is increased. As
expected, I DS1 will not change much because M2 is in the saturation region. VGS 2
cannot change much because I DS 2 is almost a constant. Therefore, VDS 1 will not
change much because V DS 1 VG 2 VGS 2 . Since Vout decreases as R L increases,
V DS 2 decreases. The program is shown in Table 6.1-9. The result is shown in Table
6.1-10.
Table 6.1-9 Program for Experiment 6.1-7
Example 6.1-7
.PROTECT
.OPTION POST
.LIB 'c:\mm0355v.l' TT
.UNPROTECT
.op
VDD
RL 1
1
11
0
3.3V
500k
6-14
.param W1=5u
M2 11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1 3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2
2
0
1v
VGS1
4
0
0.6v
.PROBE I(RL) I(M2)
.end
VDS2
VDS1
IDS1
100k
2.445V
0.351V
5.014u
200k
1.954V
0.344V
4.999u
300k
1.466V
0.337V
4.985u
400k
0.981V
0.330V
4.969u
500k
0.499V
0.323V
4.954u
Example 6.1-8
.PROTECT
.OPTION POST
.LIB 'c:\mm0355v.l' TT
.UNPROTECT
.op
VDD
RL 1
1
11
0
3.3V
XVAL
.param W1=5u
M2 11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1 3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2
2
0
1v
VGS1
4
0
0.6v
Vout 11 0
0V
.DC Vout 0 3.3V 0.1V SWEEP XVAL
.PROBE I(RL) I(M2)
.end
100k
6-16
500k
100k
IDS2
RL decreasing
I(M2)
Vout
Fig. 6.1-13 The changing of Vout with respect to the changing of RL
1
11
0
3.3V
XVAL
6-17
Rv 3
.param W1=5u
M2 11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1 9
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2
2
0
1v
VGS1
4
0
0.6v
VDS1
9
0
0V
.DC VDS1 0 3.3V 0.1V SWEEP XVAL
.PROBE I(M1) I(Rv)
.end
100k
500k
100k
IDS1
RL decreasing
I(M1)
VDS1
Table 6.1-10 The program to investigate the relationship between Vout and V DS 1
Example 6.1-10
.PROTECT
.OPTION POST
.lib 'D:\model\tsmc\MIXED035\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
3.3V
RL
1
11 500k
.param W1=5u
M2
11 2
3
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
M1
3
4
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VG2 2 0
VGS1
4
1v
6
0.6v
Vin
6
0
0
Vout
11 0
0
.DC Vout 0 3.3v 0.1v
.PROBE I(M1) I(M2) I(RL) I(rm)
.end
6-19
6-20
(b) The small signal equivalent circuit for the cascoded amplifier
Fig. 6.2-1 The AC analysis of the cascoded amplifier
We perform node analysis at various nodes.
At S2:
v1 v1 vout
g m1v gs1 g m 2 v gs 2
ro1
ro 2
g m1vin g m 2 v1
ro1
ro 2
v
1
g m 2 out g m1vin
ro 2
ro1 ro 2
v1
At D2:
v1 vout
v
g m 2 v gs 2 out
ro 2
RL
6-21
(6.2-1)
1
1
g m 2 v out
ro 2
ro 2 R L
v1
(6.2-2)
(6.2-3)
v out
g m ro1 (1 g m 2 r02 ) R L
vin
r01 (1 g m 2 ro 2 ) ro 2 RL
(6.2-4)
(6.2-5)
Since ro 2 is quite large because of the cascoding, we expect a rather high gain
from Equation (6.2-5). Note that we obtain this result under the assumption that the
load resistor is very large. A large resistor can now be used because the current in the
transistors is very low. The reader is encouraged to consult Fig. 6.1-4. The I-V curve
is flat and the current is low. A large resistor can thus be used. But it is not a practical
idea because a large resistor can hardly be implemented in a VLSI chip.
In the next section, we shall introduce cascoded amplifiers with active loads. As
can be imagined, the gain is much higher.
Section 6.3
Consider Fig. 6.3-1. The circuit is a cascoded amplifier with active loads. The
purpose of the active load is to provide an even higher load so that we will achieve a
higher gain.
6-22
1
vout
1
0
vout_1
1_1
5V
0
0
6-23
.param
M4
3
2
1_1
1
+pch L=1u
W='W4' m=1
+AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'
M3
vout
4
3
1
+pch L=0.5u W='W3' m=1
+AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M2
vout_1 6
7
0
+nch L=0.5u W='W2' m=1
+AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M1 7
8
0
0
+nch L=1u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
Vin 8
VG19
VG26
VG34
VG42
9
0
0
0
0
0
0.817V
1.8V
3V
4V
Vout vout_1 0
0
.DC Vout 0 5v 0.1v
.PROBE I(M2) I(Rm3)
.end
6-24
I(M2)
Vout
Fig. 6.3-2 The matching of the I-V curve of M2 with its load curve
Fig. 6.3-2 shows that the load curve is very flat and the load curve, which is the
I-V curve of M3, is also very flat. We may say that the ro of M2 almost matches
exactly with the ro of M3. This cannot be achieved with a resistive load.
Experiment 6.3-2 The VGS1 and Vout Relationship of the Cascoded Amplifier in
Fig. 6.3-1
We further drew the VGS 1 vs Vout curve. The program is in Table 6.3-2 and
the result is in Fig. 6.3-3. We can now see that the Vout drops sharply and thus will
induce a very high gain, as confirmed in the next experiment.
Table 6.3-2 Program for Experiment 6.3-2
Ex6.3-2
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
Rm3vout vout_1
Rm11
1_1 0
.param
5V
0
6-25
M4 3
2
1_1 1
+pch L=1u
W='W4' m=1
+AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'
M3 vout 4
3
1
+pch L=0.5u W='W3' m=1
+AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M2 vout_1 6
7
0
+nch L=0.5u W='W2' m=1
+AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M1 7
8
0
0
+nch L=1u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
Vin 8
VG19
VG26
VG34
VG42
9
0
0
0
0
0
0V
1.8V
3V
4V
6-26
I(M(9)
Vout
VGS1
Fig. 6.3-3 Vout vs VGS 1 for the cascoded amplifier in Fig. 6.3-1
Experiment 6.3-3 The Gain of the Cascoded Amplifier in Fig. 6.3-1
The program to find the gain is in Table 6.3-3. The result is shown in Fig. 6.3-4.
The gain was found to be 3000.
Table 6.3-3 Program for Experiment 6.3-3
Ex6.3-3
.protect
.lib 'c:\mm0355v.l' TT
.unprotect
.op
.options nomod post
VDD
1
0
Rm2vout vout_1
Rm11
1_1 0
.param
5V
0
M4 3
2
1_1 1
+pch L=1u
W='W4' m=1
+AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'
M3 vout 4
3
1
+pch L=0.5u W='W3' m=1
6-27
+AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M2 vout_1 6
7
0
+nch L=0.5u W='W2' m=1
+AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M1 7
8
0
0
+nch L=1u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
Vin 8
9
sin(0v 0.0001v 10k)
VG19
0
0.817V
VG26
0
1.8V
VG34
0
3V
VG42
0
4V
.tf v(vout) vin
.tran 0.1us 600us
.end
6-28
The gain and the characteristics of this amplifier are quite similar to the cascoade
amplifier in Fig. 6.3-1.
Section 6.4
VDD=3.3V
M1
50/2
M3
50/
2
M2
50/2
2
M4
50/
2
M10
2/2
4
VBIAS5 = 1.9V
V-
1.65V
VBIAS9 =0.6V
M5
100/
2
M6
100/2
M7
100/
2
M8
100/2
VBIAS6 = 1.9V
Vo
Vout
V+
M11
85/2
AC
M9
100/2
VBIAS11 = 0.6V
1.65V
VSS=0V
VSS=0V
.op
VDD
VDD! 0
VSS VSS! 0 0V
M1 1
M2 2
M3 3
M4 4
M5 3
M6 4
M7 5
M8 6
M9 7
M10 Vo
M11 Vo
3.3V
1
VDD!
1
VDD!
3
1
3
2
VB7 5
VB8 6
Vi- 7
Vi+ 7
VB9 VSS!
4
10_1
VB11 VSS!
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VDD!
PCH
W=2U
VSS!
NCH
L=2U
L=2U
L=2U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
L=2U
W=85U
L=2U
VIN+
Vi+ 0 sin(1.65 0.000001 10k)
VINVi- 0
1.65
VBIAS7 VB7 0
1.9V
VBIAS8 VB8 0
1.9V
VBIAS9 VB9 0
0.6V
VBIAS11 VB11 0
0.6V
Rm10
VDD!
.tf V(vo)
*.tran
1u
.end
10_1
vin+
10m
6-31
3.3V
1
VDD!
1
VDD!
3
1
3
2
VB7 5
VB8 6
Vi- 7
Vi+ 7
VB9 VSS!
4
10_1
VB11 VSS!
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VDD!
PCH
W=2U
VSS!
NCH
VIN+
Vi+ 0 0
VINVi- 0
1.65
VBIAS7 VB7 0
1.9V
VBIAS8 VB8 0
1.9V
VBIAS9 VB9 0
0.6V
VBIAS11 VB11 0
0.6V
Rm10
VDD!
.DC VIN+
0
.end
10_1
0
3v 0.1v
6-32
L=2U
L=2U
L=2U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
L=2U
W=85U
L=2U
Vout
V+
Fig. 6.4-2 Vout vs V for the amplifier in Fig. 6.4-1
Experiment 6.4-3 The I-V Curve of M9 in Fig. 6.4-1 and Its Load Curve
It is perhaps informative to take a look at the I-V curve of M9. The program is in
Table 6.4-4 and its load curve is shown in Fig. 6.4-3. We can see that the current in
M9 is very small, only 50u. It is this small current which makes its I-V curve very
flat and thus its high gain possible.
There is also a load line in Fig. 6.4-3. So, one may ask, what is the load of M9?
The answer is: Vi or Vi . As V DS 9 increases, VGS 7 VGS 8 decreases. Thus the
load line shows that the current of M9 decreases.
Table 6.4-4 Program for Experiment 6.4-3
Experiment 6.4-3
.PROTECT
.OPTION POST
.LIB "C:\mm0355v.l" TT
.UNPROTECT
.op
VDD
top 0 3.3V
VSS VSS! 0 0V
R4 44 4
0
M1 1
M2 2
1
1
VDD!
VDD!
VDD!
VDD!
PCH
PCH
6-33
W=50U L=2U
W=50U L=2U
M3
M4
M5
M6
M7
M8
M9
3
44
3
4
5
6
7
VIN+
VINVBIAS5
VBIAS6
VBIAS9
Vout1
RM9
VDS9
.DC
.probe
.END
3
1
VDD! PCH
W=50U
3
2
VDD! PCH
W=50U
VB5
5
VSS!
NCH
VB6
6
VSS!
NCH
Vi7
VSS!
NCH
Vi+
7
VSS!
NCH
VB9 VSS! VSS!
NCH
Vi+
ViVB5
VB6
VB9
4
0
top
0
0
0
0
1.65
0
1.65
1.9V
1.9V
0.6V
0
VDD!
7
0
0
VDS9
0 3.3v 0.1v
I(M9) I(Rm9)
6-34
L=2U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
I(M9)
Load current of M9
VDS9
Fig. 6.4-3 The operating points of M9 in Fig. 6.4-1
Experiment 6.4-4 The I-V curve of M10 and its load line.
In this experiment, we show the I-V curve of M10 and its load line. Table 6.4-5
is the program and Fig. 6.4-4 shows the result. As can be seen, the I-V curve of M10
and its load line are not very flat. This is due to the fact that they only a CMOS
transistor circuit is used. If a cascaded amplifier is used in the second stage, the gain
will be 150 times of that of the present circuit. This gain will be too large.
Table 6.4-5 The program for Experiment 6.4-4
Experiment 6.4-1_M10
.PROTECT
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.op
VDD
VDD! 0
VSS VSS! 0 0V
3.3V
6-35
M1 1
M2 2
M3 3
M4 4
M5 3
M6 4
M7 5
M8 6
M9 7
M10 Vo
M11 Vo
1
VDD!
1
VDD!
3
1
3
2
VB7 5
VB8 6
Vi- 7
Vi+ 7
VB9 VSS!
4
10_1
VB11 VSS!
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VDD!
PCH
W=2U
VSS!
NCH
VIN+
Vi+ 0 sin(1.65 0.000001 10k)
VINVi- 0
1.65
VBIAS7 VB7 0
1.9V
VBIAS8 VB8 0
1.9V
VBIAS9 VB9 0
0.6V
VBIAS11 VB11 0
0.6V
Rm10
VSD10
VDD!
VDD!
10_1
Vo 0
.DC VSD10 0
3.3v 0.1v
.probe I(Rm10) I(M11)
.end
6-36
L=2U
L=2U
L=2U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
L=2U
W=85U
L=2U
I(M10)
VSD10
Fig. 6.4-4 The I-V curve of M10 and its load line
In the following example, we shall present an experiment to investigate the
voltages and currents of the two-stage cascoded amplifier
Experiment 6.4-5 An investigation into the voltages and currents of the twostage cascoded amplifier.
Let us first present the circuit as in Fig. 6.4-5 for the simplicity of discussion.
VDD=3.3V
VDD=3.3V
M1
50/2
M3
50/
2
M2
50/2
2
M4
50/
2
M10
2/2
4
VBIAS5 = 1.9V
V-
1.65V
VBIAS9 =0.6V
M5
100/
2
M7
100/
2
M6
100/2
M8
100/2
VBIAS6 = 1.9V
Vo
Vout
V+
M11
85/2
AC
M9
100/2
VBIAS11 = 0.6V
1.65V
VSS=0V
VSS=0V
6-37
1
2
3
4
3
4
5
6
7
VIN+
VINVBIAS7
VBIAS8
VBIAS9
3.3V
1
VDD!
1
VDD!
3
1
3
2
VB7 5
VB8 6
Vi- 7
Vi+ 7
VB9 VSS!
Vi+ 0
vi- 0
VB7 0
VB8 0
VB9 0
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VDD!
PCH
W=50U
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
VSS!
NCH
0v
1.65v
1.9V
1.9V
0.6V
6-38
L=2U
L=2U
L=2U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
W=100U
L=2U
VBIAS11 VB11 0
Rm10
VDD!
0.6V
10_1
6-39
VG10
V SG4
V D3
VGS5
VD9
VGS6
VGS8
VSD4
V+
6-40
(4) VGS 6 increases all the time until V 1.65V and is kept a constant afterwards.
That VGS 6 increases is due to the fact that VGS 8 increases. If VGS 8 increases,
V DS 8
will
decrease
because
any
transistor
is
an
inverter.
V DS 8 V D 8 VS 8 V D 8 V D 9 . V D 9 is a constant all the time. Thus as V DS 8
decreases, V D 8 VS 6 decreases and VGS 6 increases because VG 6 is a constant.
(5) VSD 4 0 when V is small. Note that as V is small, I ( M 4 ) I ( M 8 ) 0 .
But, there is still a sizable V SG 4 which means that M 4 is on, but without current.
As discussed before in Chapter 4, V SD 4 must be 0.
(6) VG10 V D 4 is 3.3V when V is smaller than 1.65V. That is, it is very high
when V is small. VG10 V D 4 drops to roughly equal to V D 9 when V is
larger than or equal to 1.65V. That is, it is low when V is large. That
VG10 V D 4 3.3V when V is smaller than 1.65V is due to the fact that
VSD 4 0 when V is small as discussed in (5) above. That it drops to V D 9
indicates that M 8 is actually in the linear region. Note also that V D 9 is a lower
bound of VG10 . VG10 cannot become lower than V D 9 .
Let us further investigate the phenomenon that VG10 drops. Note that when
V is equal to 1.65V, the circuit is completely balanced. Thus, VG10 V D 4 must
be equal to V D 3 . But V D 3 is low all the time and VG10 is high before V is
equal to1.65V. Therefore VG10 must drop to such an extent that it is equal to V D 3
(7) V SG 4 is constant from Vi 1V to Vi 1.5V . This is because V SG 3 is a
constant during this period. It is a constant because I ( M 3 ) is a constant during this
period. Then I ( M 3 ) decreases and this causes VSG 3 to decrease as M 3 is a diode.
Thus V SG 4 V SG 3 also decreases after Vi 1.5V and before it reaches 1.65V.
After Vi 1.65V , V SG 4 remains a constant because I ( M 4 ) is a constant
afterwards.
It will be a big puzzle for readers to observe that as V SG 4 decreases for the
period from Vi 1.5V to Vi 1.65V , I ( M 4 ) actually increases. This is quite
unusual because we would think that the current in a PMOS transistor will decrease if
its V SG decreases. To understand this, so far as M 4 is concerned, its load is M 8 .
VGS 8 is increasing all the time. Therefore, we may say that the load of M 4 , which
is M 8 , is decreasing. That is, two phenomenon are happening to M 4
simultaneously: (1) Its V SG is decreasing and (2) its load is also decreasing. This
situation is illustrated in Fig. 6.4-8. From Fig. 6.4-8, we can see that the current may
increase as V SG decreases because the load is also decreasing. Note that V SD is
extremely small, in fact 0, to start with.
6-41
1
2
3
4
3
4
5
1
10_1
1
10_1
3
1
3
2
VB7 5
VB8 6
Vi- 7
3.3V
VDD!
VDD!
VDD!
VDD!
VSS!
VSS!
VSS!
PCH
PCH
PCH
PCH
W=50U
L=2U
W=50U
L=2U
W=50U
L=2U
W=50U
L=2U
NCH
W=100U
NCH
W=100U
NCH
W=100U
6-42
L=2U
L=2U
L=2U
M8 6
M9 7
Vi+ 7
VB9 VSS!
VSS!
VSS!
NCH
NCH
W=100U
L=2U
W=100U
L=2U
VIN+
Vi+ 0 0
VINvi- 0 1.65v
VBIAS7 VB7 0
1.9V
VBIAS8 VB8 0
1.9V
VBIAS9 VB9 0
0.6V
VBIAS11 VB11 0
0.6V
VDS9
7
VSS!
0
Rm10
VDD!
10_1
IDS9
Vi+ increasing
VDS9
Fig. 6.4-9 I-V curve of M9 and its load curves for different Vi+
Let us now try to explain another property of this cascaded amplifier. The inputoutput curve of this amplifier is very sharp as shown in Fig. 6.4-2 which is now
displayed in Fig. 6.4-10. Our question is: How can the curve be so sharp?
6-43
VDD=3.3V
M1
50/2
M3
50/
2
M2
50/2
2
M4
50/
2
M10
2/2
4
VBIAS5 = 1.9V
5
V-
1.65V
VBIAS9 =0.6V
M5
100/
2
M7
100/
2
M6
100/2
M8
100/2
VBIAS6 = 1.9V
Vo
Vout
V+
M11
85/2
AC
M9
100/2
VBIAS11 = 0.6V
1.65V
VSS=0V
VSS=0V
VG10
V SG4
V D3
VGS5
VD9
VGS6
VGS8
VSD4
V+
6-45
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.UNPROTECT
.op
VDD
VDD! 0
VSS VSS! 0 0V
3.3V
M10 Vo 4
10_1
M11 Vo VB11 VSS!
VDD!
PCH
VSS!
W=2U
NCH
L=2U
W=85U
VIN+
4 0
sin(1.4V 0.5V 10k)
VBIAS11 VB11 0
0.6V
Rm10
VDD!
*VSD10 VDD!
10_1
Vo 0
*.DC
VSD10 0
3.3v 0.1v
*.probe I(Rm10) I(M11)
.tran 0.1us 0.5ms
.end
6-46
L=2U