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Table 0-1 Revision History

sv_vd_front block represents one part of the H.264 video decoder block used on the
7411D0 chip. The timing on this block is data-path dominated, with some critical paths
that also include memories.

8K ARC core: The ARC is a 32b embedded CPU with 8kB instruction cache and 4kB
data memory used in the H.264 video decoder. This core represents a block with high
performance requirements, and the critical paths in this block are memory dominated.

The two blocks were analyzed using PT-SI. The sv_vd_front block uses a 4.16ns clock
with 150ps uncertainty (20% margin and OCV of 10%). The ARC core uses a 4.0 ns
clock with 150ps uncertainty (20% margin and 10% OCV)

5.1 sv_vd_front block

The following experiments were run using the multi-Vt library:

Swap HD library with cells from multi-Vt library

In the first test-case, the HD_* cells (tsmc13hd library) in the vd_front block were replaced
with the HDS_ cells from the multi-vt library (tsmc13hdvt). The wns slack out of PT-SI went
from -145ps to -700ps. The total endpoints increased from 409 to 6155. This change in slack
was due to the new characterized library with the 9x9 tables. This design was a prime
candidate for the multi-Vt optimization tool (details below in Section 7). This tool takes a
Primetime saved session with SVT/HVT cells and produces ECO commands to swap in lowVt cells to achieve timing closure. After running through one round of optimization, the tool
swapped in 9358 low-Vt cells (~5% of total cell count) to achieve timing closure. The wns
slack changed to -52ps after 1 iteration. A similar experiment was carried out wherein HD_*
cells were swapped with HDL_* cells, extracted and timed in PT-SI. The design had +42ps of
slack.

Standard-Vt flow (SVT)

In the second test-case, the vd_front block was run from synthesis through pnr, in the Astro
flow with SVT cells (HDS_*). The wns slack out of primetime-SI was -660ps (1463
endpoints). After 1 iteration using the multi-Vt tool, the slack went down to +10ps. The tool

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swapped in 4522 low-Vt (~2.3% of stdcell count) cells to achieve timing closure. The leakage
power out of Design Compiler (DC) was 4.7 mW. Final stdcell area out of Astro: 1.99 mm 2

Vd_front summary using multi-Vt flow (Note: macro area of 2.026 mm 2 not included below)
HD-HDS swap
SVT
LVT
Multi-Vt
HVT

+42ps
+10ps
+12ps
-91ps
n/a

187842
196777
183680
195965
n/a

1.88 mm2
1.99 mm2
1.82 mm2
1.96 mm2
n/a

4.7mW
25.9mW
5mW
n/a

5.2 arc_8ki_4kd_core block

The following experiments were run using the multi-Vt library:

Standard-Vt flow (SVT)

In this case, the arc block was run from synthesis through pnr, in the Astro flow with SVT
cells (HDS_*). The wns slack out of primetime-SI was -573ps (791 endpoints). After 1
iteration using the multi-Vt tool, the slack went down to +11ps. The tool swapped in 3535
low-Vt (~17% of stdcell count) cells to achieve timing closure. The leakage power out of
Design Compiler (DC) was 1.2 mW. Final stdcell area out of Astro: 0.24 mm 2

Low-Vt flow (LVT)

In this case, the arc block was run from synthesis through pnr, using the Astro flow with LVT
cells (HDL_*). The wns slack out of primetime was +104ps. The total leakage power out of
DC was 1.4 mW. Final stdcell area out of Astro: 0.197 mm 2

Leakage Optimization using multi-Vt library (Multi-Vt)

In this case, the arc block was run through the flow using all types of cells in the multi-V t
library. The leakage optimization feature in physical compiler was used for optimization. The
tool added quite a few HDH cells to minimize leakage power and swapped in HDL cells on
timing critical paths where needed (9422 HDH cells, 7301 HDL cells, 1729 HDS cells). wns
out of PT-SI: -122ps (~90 endpoints). With one round of optimization (HDS-HDL swap)
using multi-Vt tool, the slack changed to -62ps. 195 cells were swapped. Timing
improvements could be made by swapping different combination of cells. Leakage power out
of PC was 0.97 mW. Total stdcell area out of Astro: 0.204 mm 2

High-Vt flow (HVT)

In this case, the arc block was run with HVT cells but timing out of DC/PC was really bad.
The wns was -1.7ns. The frequency target could not be achieved with the HDH* cells. The
only way to test this would be to reduce frequency targets using these cells, then change
performance goals using the multi-Vt tool. The netlist out of PC was not a good starting point.

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The ARC core did not see significant improvement using the multi-V t flow. The timing slack from
the standard library (tsmc13hd using HD* cells) was +42ps, hence the gain in performance was
not substantial. Since the critical paths in the arc were through memories that had a large access
time, low-Vt memories would an option. The low-Vt memory has an improvement of ~15%
(220ps) according to the library group. Based on this data, there would be some improvement in
the frequency targets, but this would require further analysis when the libraries are made
available.
ARC block summary using multi-Vt flow (Note: macro area of 0.441 mm 2 not included below)
SVT
LVT
Multi-Vt
HVT

slack
+11ps
+104ps
-62ps
n/a

stdcell count
21495
18548
18892
n/a

stdcell area
0.240 mm2
0.197 mm2
0.204 mm2
n/a

leakage power
1.7 mW
1.0 mW
0.97 mW
n/a

In summary, the methodology chosen would depend on the design requirements. In the case of
the vd_front block the best solution would be to use SVT cells from synthesis through place and
route, and then swap out with LVT cells using the Broadcom internal multi-V t tool for timing
critical paths. The leakage optimization flow produced designs with smaller area than the SVT
flow, and the timing was in the range that could be fixed with a few ecos. Number of low-V t cells
inserted depends on the distribution of negative slack paths in the design. Reducing negative
slack results in larger area (i.e. larger drivers). For some high speed blocks, it would be
worthwhile to only use LVT cells. This would translate to good performance/area but the leakage
power would be ~10x. In the case where multiple libraries (regular HD and multi-vt) are used in a
design, extra mask (adjusting voltage thresholds) would lead to higher manufacturing costs.
Static leakage current at the 90 nanometer (and below) process node is design enemy number one.
It is an increasing concern as the developers of SoC applications seek to gain the performance
and functionality benefits that this geometry can offer without paying the penalty in power
consumption. The methodology described in this review is specifically dedicated to the power
versus performance optimization of a design using both high and low V t libraries concurrently. It
enables power reduction whilst at the same time maximizing design performance. Adopting such
a new methodology for nano-class process technology will be essential to achieving both design
and consequentially business success.

7. Broadcom Multi-Vt tool

You must set your environment variable BCMDIR:
setenv BCMDIR /projects/BCMDEV/work/bcm
To run the tool, you create a Primetime saved-session that contains a timing run for your block at
the desired target frequency. The netlist should be an all-LVT netlist (except the clock-tree and
scratch logic which can be put at whichever vt you desire and which are not touched by the flow).

To run the flow, you simply execute:

$BCMDIR/bin/multivt
The tool will invoke primetime (according the version set in your environment variable
PTIMEVER), query the database for timing information, and produce two outputs files:

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eco.tcl - a list of sizeCell commands that eco HVTcells into LVT cells. The sizeCell function is
defined in the script $BCMDIR/synopsys/tcl/lib/multivt_eco.tcl

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