Slides Parte2 Rev2010

Design of CMOS Amplifiers
December, 2008 (revised, Jan. 2010)
Joo Goes (DEE) - 2010
Contents:
Basic amplifier topologies
Current-mirrors
Basic cascode topologies and differential-pair
Single-stage transconductance amplifiers
Two-stage Miller-compensated amplifiers
Advanced two-stage amplifier topologies
Basic Amplifier Topologies

(common-source amplifier)
Vdd
MB
Gain stage with high input impedance

M2
vout
vin
M1
For low frequencies:
Av = gm1 (rds1 rds 2 )

gm1
=
gds1 + gds 2

(common-source amplifier)
For high-frequencies we have:
Vdd
MB
Av(s ) =
M2
vout
vin
M1
R0 gm1 + R0 C gd 1 s
1 + R0 C gd1 + C L' s
R0 = rds1 rds2
C L' = C L + Cdb1 + Cdb 2 + C gd1 + C gd 2
The output impedance is given by:
R0 rds1 rds 2

(common-drain amplifier or source-follower)
Vdd
vin
I
Voltage buffer;
DC level shifter;
M1
vout
MB
M2
In low-frequencies and considering

body effect:
gm1
Av =
1
gds1 + gds 2 + gmb1 + gm1

For high-frequencies:
Av(s ) =
Vdd
vin
I
M1
M2
(gm1 + gds1 + gds2 + gmb1 ) + (C gs1 + C L' ) s
C L' = C L + C sb1 + Cdb 2 + C gd 2 + C gs1

vout
MB
gm1 + C gs1 s
The zero has negative real part!!

Stability problems may arise.
The output impedance is given by:
1
1
R0 =
gds1 + gds 2 + gmb1 + gm1

gm1

Since we have
1
R0
gm1
For the emitter-follower:
For the source-follower:
TJBs :
MOSs :
Ic
gm =
VT
2 ID
gm =
(Vovd )
This means that, for the same current, the emitter-follower

has a 4 times lower impedance than the source-follower!
(Assuming VDSsat = VGS -VTn = 200 mV).

(common-gate amplifier)
Low input-impedance
Current-gain stage
Vdd
MB
In low-frequencies:
M2
vout
vbias
M1
rin
vin
gm1
Av
gds1 + gds 2
1
rin
gm1
rds 2
1 +
rds1

(Summary of single-transistor amplifier topologies)
Amplifier
Voltage gain,
Input
Output
configuration
AV
impedance, Rin
impedance, Rout
Common-source
g m (r ds || r out )
High
High
Common-gate
g m (rds || rout )
Low
High
Common-drain
High
Low
(source-follower)

(Enhanced Voltage Followers)
(a)
(b)
(c)
Enhanced Voltage Followers: (a) NMOS-type supper-source follower (SSF); (b)

NMOS-Flipped-voltage follower (FVF); (c) NMOS enhanced voltage follower with
current feedback.
Basically it employs, in a fully differential implementation, two NMOS ordinary source
followers (SFs) and negative feedback is applied from the drain of the NMOS devices
to the low-impedance nodes of the amplifier (sources of the NMOS). The current
sources force the input transistors (NMOS) to conduct a fixed bias current. Thus these
NMOS device operate as simple SFs and copy the input signal at their gates to the
output. The second devices (PMOS) act as a class-A amplifier in a closed-loop
configuration. Due to the feedback, the output impedance can be made very small.
Current-Mirrors
Improved current-mirrors
(Basic current-mirror with degenerated-source)
Vdd
Main goal: increase rout!

I
Iout
rout
At low-frequencies:
M1
RS
M2
RS
RS
rout = rds 2 1 + gm2 RS +
rds 2
rds 2 (1 + gm2 RS )
(Wilson Current-mirror)
Vdd
Iout
rout
M3
M4
M1
M2
Disadvantage: Output dynamicrange decreases!

(Vout > 2*Vdsat +VTn)
For low-frequencies:
gm4 rds4
rout rds1
(Cascode Current-mirror)
Vdd
Iout
rout
M3
M4
M1
M2
Disadvantage: Output dynamicrange decreases!

(Vout > 2*Vdsat +VTn)
In low-frequencies:
1

rout = rds 4 1 + rds 2 gm4 +
rds 4
rds 2 (rds 4 gm4 )

Improved Cascode-current-mirrors
(Wide larger output dynamic-range)
Improved dynamic-range
Vdd
Vdd
Vout > 2*Vdsat if n=1!
Ibias = Iin / k
Iin
W/L
(n+1) 2*k
Iout
M6
MB
W/L M7
W/L
(n) 2
M8 W/L
Systematic offset problem

due to an asymmetry in the mirror!
(VDS7 > VDS8, since the drain
impedances are different)!
(Wide larger output dynamic-range)
Vdd
Vdd
Ibias = Iin / k
Iin
W/L
(n+1) 2*k
MB
W/L
(n) 2
M5
W/L M7
Iout
M6
W/L
(n) 2
Much better solution!

Improved output dynamic-range
Vout > (n+1)*Vdsat!
M8 W/L
M7 e M8 biased in the limit of

triode/saturation region and M7
and M5 act like a single diode.
(Gain-boosting techniques)
Vdd
Iout
I
rout
M7
Sackinger, 1990].
Vbias
[Hosticka, 1979, Bult, 1990,
M6
M8
Use an extra amplifier in a

feedback loop to keep VDS8
constant.
rout ( gm 6 rds 6 ) rds 8 (1 + A )

(Gain-boosting techniques)
Vdd
Vdd
Vdd
Ibias
Ibias
I
Iout
rout
2nd. option:
M5
M6
Mx2
M7
Mx1
M8
Use regulated-cascode employing a

single transistor amplifier.
Basic cascode Topologies

and differential-pair
Advanced amplifier topologies

(telescopic-cascode amplifier)
Vbias voltage should obey to:
Vdd
Ibias
vout
Vbias
M2
vin
M1
CL
Vbias > Vdsat-M1 +VGS-M2 = Vdsat-M1 +

+ VTn + Vdsat-M2
For maximum output dynamic-range:
Vbias = Vdsat-M1 + VTn + Vdsat-M2

(telescopic-cascode amplifier)
Vdd
It is basically a common-gate amplifier cascoded

with a common-source amplifier:
rout (gm2 rds1 rds 2 ) rout fonte
Ibias
Vbias
M2
gm2 rds 2 2
, only if we use a cascode current - source

2
vout
vs
vout
Av = M 2
vin vsM 2
CL
( gm1 (rds1 rds 2 )) gm2 rds 2 rout fonte

(gm rds )
))
vin
M1
Rougly!
Rule: Output impedance, rout, for 2 devices, M1 and

M2 in cascode configuration is given by: rds1
multiplied by the gain of M2 (gm2.rds2)!

(folded-cascode amplifier)
Similar circuit but with a PMOS cascode
Vdd
transistor
Ibias1
vin
M1
M2
(++) input and output common-mode levels

can be equal;
Vbias
vout
CL
Ibias2
(--) Slower, because the is a PMOS device

in the signal path;
(--) Worse power dissipation since there
are 2 current branches;
The differential-pair
For low frequencies we have:
ID1
V+
ID2
M1
M2
Ibias
iD1 =
V-
vind
gm
vind , since gm1 = gm2 = gm
2
1
1
+
gm1 gm2
iout d = iD1 iD 2 = gm vin
gm vin rout
Av =
= gm rout
vin
Basic differential amplifier

(with active loads)
Vdd
At low-frequencies:
M3
M1
M4
M2
vin
Ibias
rout
vout
Av = gm1 (rds 2 rds 4 )

gm1
=
gds 2 + gds 4
Single-stage operational transconductance

amplifiers (OTAs)
Operational Amplifiers
I=0
V-
Ideally:
ro
Open-Loop gain,
A, infinite;
Vo
ri
V+ -V-
A(V+-V-)
V+
I=0
Input Impedance, ri,

infinite and output
impedance, ro, zero.
In general :
Z2
v1
Z1
v2
Z3
vo
Z 4 Z1 + Z 2
Z2
vo =
v2
v1
Z 3 + Z 4 Z1
Z1
+
Z4
( Op-Amps )
For low finites open-loop gains, A, one must take into account the error
added by this parameter in order to define its specification.
In switched-capacitor (SC) circuits, since no resistors are used, the output
impedance is purely capacitive. Therefore, a single-stage
transconductance operational amplifier (OTA) might be used.
OTAs such as the folded-cascode, telescopic-cascode or mirror-cascode
can be considered amplifiers with a dominant pole and, hence, the
dynamic analysis is simple as well as its stability.
(definitions)
DC Differential gain, Ad: Open-loop low-frequency gain measured when a
differential input signal is applied; Typically: Ad = 40 to 120 dB;
Common-mode gain, Ac: Open-loop low-frequency gain measured when a
common-mode input signal is applied; Typically: Ac = 20 to 40 dB;
Common-mode rejection ratio, CMRR: CMRR = Ad/Ac.
Typically: CMRR = 40 to 80 dB;
Power-supply rejection ratio, PSRR: PSRR = Ad/Aps.
Typically: PSRR = 90 dB at DC and decreases when frequency increases;
(definitions)
Input offset voltage, Vos: Amount of voltage one has to apply at the inputs
in order to reach zero voltage at the output;
Typically Vos = 1 to 10 mV;
Output swing, OS: Maximum amplitude allowed at the outputs to get low
harmonic distortion;
Slew-rate, SR: (dvo/dt) max; Depends on the biasing currents and loads;
Measured by appying an input step with reasonable amplitude;
Typically: SR = 10 to 1000 V/us;
(definitions)
Gain-Bandwidth Product, GBW: frequency at which the open-loop gain is
0 dB;
Phase Margin, PM: Margin to 180 between the input and the output at
the unity-gain frequency. Usually it is desired PM > 60 to guarantee
monotonic response in unity-gain configuration;
Settling-time, ST: defined to 0.1% accuracy at unity-gain configuration;
(related to the GBW).
Single-stage transconductance amplifiers

(OTAs)
Very used in SC circuits
Simple to design using MATCAD
Topologies:
Telescopic-Cascode;
Mirror-Cascode;
Folded-Cascode
Single-stage transconductance amplifier (OTAs)

(Telescopic-cascode)
VDD
VB2
M7
M8
M5
M6
M3
(++) High DC gain,
vout
( gm1 rds1 )2
2
(++) Low current consumption

(only a single current branch);
M4
(--) small output swing

(5 transistors in stack);
v+
VB1
M1
M2
v-
(--) Normally different input and output

DC common-mode levels
M9

(Mirror-cascode)
(++) High DC gain,
VDD
M12
M10
v+
M11
M1
M2
M13
v-
M3
VB2
M4
M5
M6
M7
M8
VB1
M9
( gm1 rds1 )
(++) equal input and output common-mode

voltages;
(++) Better output swing;
vout
(--) Higher current consumption

(2 current branches);
(--) Dynamic performance (speed) very
dependent on the dynamic current mirror

(Folded-Cascode)
(++) High DC gain,
( gm1 rds1 )2
VDD
VB2
M10
(++) equal input and output common-mode

voltages
M11
I
I/2
I/2
M1
M2
I/2
I/2
M3
M4
VB3
vout
VB1
M9
M5
M6
M7
M8
(++) Better output swing;

(--) Higher current consumption
(2 current branches);
Single-stage OTAs
(folded-cascode amplifier with biasing circuitry)
VDD
VB2
MB4
MB1
M10
MB2
AMPOP CASCODE DOBRADO
M11
I/2
I/2
MB6
I/10
VB3
M1
I/10
I/10
I/10
M2
I/2
I/2
M3
M4
I/10
vout
VB4
MB5
VB1
MB3
VB3
M9
MB7
CIRCUITO DE POLARIZAO
VB4
M5
M6
M7
M8
Single-Stage OTAs
(folded-cascode)
gm1 (rds8 ( gm6 rds6 )) [(rds1 rds10 ) ( gm4 rds4 )]

Vout (s )
gm1 rout
Av =
=
=
Vin (s ) 1 + s rout C L 1 + s ( rds8 ( gm6 rds6 )) [(rds1 rds10 ) ( gm4 rds4 )] C L
At low frequency : Av gm1 (rds8 ( gm6 rds6 )) [(rds1 rds10 ) ( gm4 rds4 )]
At medium/high frequencies : Av
gm1
s CL
GBW is given by :
GBW =
gm1 (S )
2 C L (F )
(Hz )
The SR is given by :
I ( A)
SR = D 4
10 6 (V / s )
C L (F )
Single-Stage OTAs
(Mirror-Cascode with biasing circuitry)
VDD
MB1
M10
MB3
AMPOP CASCODE ESPELHADO

M11
M3a
M4a
MB2
M10a
MB4
I/10
VB3
M11a
I/2
I/10
I/10
vout
k*I/2
M2
k*I/2
I/10
VB2
MB6
MB5
VB1
VB3
I/2
M1
I/10
M4
M3
M9
MB7
CIRCUITO DE POLARIZAO
VB2
M5
M6
M7
M8
Single-Stage OTAs
(Mirror-Cascode)
Av =
Vout (s ) K gm1 rout

=
, normally K {2,3,4}
Vin (s ) 1 + s rout C L
At high frequencies : Av
K gm1
s CL
Gain - bandwidth product (GBW ) in unity gain is given by :

K gm1 (S )
(Hz )
GBW =
2 C L (F )
Slew - rate is defined by :
I
( A)
2
SR =
10 6
C L (F )
K
(V / s )
Frequency response of single-stage OTAs

(telescopic-cascode versus folded/cascode)
The maximum GBW for a given technology in a cascode configurat ion
is always defined by the non - dominant poles. It can be demonstrat ed that :
p 2 (max .) =
3 n , p Vdsat
GBW (max .) =
4 L2M 2
p 2 (max .)
2
, yielding :
, in order to have PM ~ 60 !
Example: Vdsat = 0.25V; Lmin = 0.6 m; n = 0.06 m2/V.s;

p = 0.02 m2/V.s; LM2 = 1.2 m (to avoid short-channel effects).
GBWmx. = ?
(Answer. 620 MHz, telescopic-cascode and 206 MHz folded-cascode)
Single-stage OTAs
Main OTA
(folded-cascode amplifier with gain-boosting)

SATn
SATp
Biasing
circuitry
Single-Stage OTAs
(Using MATCAD to design Single-Stage OTAs: #1)
Units
3
uA := 10
mA
um := 10
15
fF := 10
farad
19
q := 1.6 10
coul
12
pF := 10
farad
Initial Data
IB := 1000 uA
CL := 24 pF
VDsat1 := 100 mV
VDD := 1.2V
VDsat6 := 100 mV
L1 := 0.5 um
L4 := 0.5 um
Vbs1 := 100 mV
Vbs11 := 100 mV
VDsat8 := 100 mV
L6 := 0.5 um
L8 := 0.5 um
Vbs4 := 100 mV
VDsat4 := 100 mV
L11 := 0.5 um
Vbs6 := 100 mV
Technology Definitions
VTN := 0.38 volt
KN := 500 uA volt
VTP := 0.33 volt
KP := 100 uA volt
fF
CGSD0 := 0.30
= 0.026 V
drain/source minimumdrawing area

CJP := 0.953
:= 0.105
fF
CJSWP := 0.105
MJSWP
Junction potential
Adjust coeficient
MJP := 0.295
um
diode capacitance per unity area
PBP := 0.684 volt
MJN := 0.264
CJSWN := 0.0993
fF
um
PBN := 0.62 volt
MJSWN
300 K
gate capacitance per unity area
fF
um
KB
Sd_s := 0.4 um
um
um
CJN := 0.722
23 joule
KB := 1.38 10
overlap capacitance
fF
CGOX := 12.3
fF
Lateral capacitance per perimeter unit
um
:= 0.135
Ajusting coeficient
VDsat11 := 100mV
Single-Stage OTAs
Transistor's Equations
gm ID , VDsat
) := if VDsat
W_L N ID , VDsat
< KB
2 ID
) :=
KN VDsat
(
CgdP ( ID , VDsat
300 K
q
ID
2,
KB
, 2
300 K
ID
VDsat
W_L P ID , VDsat
2 ID
) :=
KP VDsat
)
(
)
, L) := W_L P( ID , VDsat ) L CGSD0
CgdN ID , VDsat , L := W_L N ID , VDsat L CGSD0
ID
g dsN ID , L :=
2060
2
2
CgsN ID , VDsat , L := W_L N ID , VDsat L CGOX
3000
CgsP ( ID , VDsat , L) := W_L P( ID , VDsat ) L CGOX
CdbN ID , VDsat , L, Vdb :=
CdbP ID , VDsat , L, Vbd :=
CsbP ID , VDsat , L, Vbs
) :=
um
ID
g dsP ID , L :=
mV
mV
um
( W_L N( ID , VDsat ) L) + Sd_s 2 CJSWN

+ W_L N( ID , VDsat ) L Sd_s
MJSWN
Vdb
1 +
PBN
( W_L P( ID , VDsat ) L) + Sd_s 2 CJSWP

+ W_L P( ID , VDsat ) L Sd_s
MJSWP
Vbd
1 +
PBP
W_L P ID , VDsat L ( Sd_s

MJP
Vbs
PBP
+ L) CJP
+
CJN
MJN
Vdb
1 +
PBN
CJP
(W_L P(ID , VDsat ) L + Sd_s ) 2 CJSWP

MJSWP
Vbs
PBP
MJP
1 +
PBP
Vbd
2 W_L P ID , VDsat L CJP
3 1
MJP
PBP
Vbs
Single-Stage OTAs
Circuit Equations
IB
g oP ( IB , VDsat4 , L1 , L4 , L11 ) := g dsP ( IB , L11 ) + g dsN

, L1
IB
g oN ( IB , VDsat6 , L6 , L8) := g dsN
, L8
2
g dsN
g dsP
IB
, L4
2
IB
,V
2 Dsat4
gm
IB
, L6
2
IB
,V
2 Dsat6
gm
IB
gm
, VDsat1
gain IB , VDsat1 , VDsat4 , VDsat6 , L1 , L4 , L6 , L8 , L11 :=

g oP IB , VDsat4 , L1 , L4 , L11 + g oN IB , VDsat6 , L6 , L8
Cout IB , VDsat6 , VDsat4 , L6 , L4 := CL + CdbN
IB
, VDsat1
fp2 IB , VDsat1 , VDsat4 , VDsat11 , L1 , L4 , L11 :=
, VDsat4
Cdif IB, VDsat1 , VDsat4 , VDsat11 , L1 , L4 , L11 2
) := VDD VDsat6
, VDsat11 , L11 + CgdN
Cout IB , VDsat6 , VDsat4 , L6 , L4 2
IB
OS VDD , VDsat6 , VDsat8 , VDsat4 , VDsat11
IB
) + CgdN
gm
IB
, VDsat1 , L1 , Vbs1 + CdbP ( IB, VDsat11 , L11 , Vbs11

2
gm
IB
IB
IB
IB
, VDsat6 , L6 , Vbs6 + CdbP , VDsat4 , L4, Vbs4 + CgdN , VDsat6 , L6 + CgdP , VDsat4 , L4
2
Cdif IB , VDsat1 , VDsat4 , VDsat11 , L1 , L4 , L11 := CdbN
GBW IB , VDsat1 , VDsat6 , VDsat4 , L6 , L4 :=
VDsat8 VDsat4 VDsat11 0.1V
IB
IB
IB
, VDsat1 , L1 + CgsP , VDsat4 , L4 + CsbP , VDsat4 , L4, Vbs4

2
Single-Stage OTAs
Optimization Graphics
i
VDsat := 70 mV +
150 mV
i
100
i := 1 .. 100
L := 1 um +
i
i
100
2 um
I := 10 uA +
i
i
100
500 uA
Ganho, var. Vdsats

1 .10
250
200
gain IB , VDsat , VDsat4 , VDsat6 , L1 , L4 , L6 , L8 , L11
GBW
IB , VDsat , VDsat6
i
gain IB , VDsat1 , VDsat , VDsat6 , L1 , L4 , L6 , L8 , L11

i
150
GBW
IB , VDsat1
, VDsat , VDsat4 , L6 , L4
7
i
5 .10
gain IB , VDsat1 , VDsat4 , VDsat , L1 , L4 , L6 , L8 , L11

i
GBW
IB , VDsat1
, VDsat6 , VDsat , L6 , L4
GBW, var. Vdsats
, VDsat4 , L6 , L4
100
50
0.05
0.1
0.15
VDsat
6 .10
0.2
0.25
0.08
6 .10
fp2 IB , VDsat1 , VDsat4 , VDsat11 , Li , L4 , L11
fp2 IB , VDsat1 , VDsat , VDsat11 , L1 , L4 , L11
fp2 IB , VDsat1 , VDsat4 , VDsat11 , L1 , Li , L11
fp2 IB , VDsat1 , VDsat4 , VDsat , L1 , L4 , L11 4 .108
0.14
Freq. 2 Polo, var Ls
(
)4 .108
(
)
fp2 ( IB , VDsat1 , VDsat4 , VDsat11 , L1 , L4 , Li) 2 .108
fp2 IB , VDsat , VDsat4 , VDsat11 , L1 , L4 , L11

i
5 .108
0.12
VDsat
Freq. 2 Polo, var Vdsats
0.1
3 .10
0.05
0.1
0.15
0.2
VDsat
0.25
0
6
1 .10
1.5 .10
2 .10
Li
2.5 .10
Single-Stage OTAs
Final Results and sizing
VDsat1 := 80 mV
VDsat4 := 80 mV
VDsat6 := 80 mV
VDsat8 := 120 mV
VDsat11 := 120mV
L1 := 0.25 um
L4 := 0.25 um
L6 := 0.25 um
L8 := 0.5 um L11 := 0.5 um
20 log gain IB , VDsat1 , VDsat4 , VDsat6 , L1 , L4 , L6 , L8 , L11

7 1
GBW IB , VDsat1 , VDsat6 , VDsat4 , L6 , L4 = 8.153 10
s
(
(
)) = 39.997
(
)
OS ( VDD , VDsat6 , VDsat8 , VDsat4 , VDsat11 ) = 0.7 V
9 1
fp2 IB, VDsat1 , VDsat4 , VDsat11 , L1 , L4 , L11 = 1.183 10
Single-Stage OTAs
(Exponential Linear Settling)
In a single - pole approximation we have a step - response like :
t
v(t ) = v( ) [v( ) v(t )] e

where represents the time - constant of the circuit. For the OTA
the step - response, Vstep , is then given by :
t
Vout (t ) = Vstep 1 e .
For a settling error smaller than 0.1%, we need :
n ln(0.001) 7 .
There will be no "Slew - Rate" , SR, limitations as long as :
SR >
V
d
= step
(Vout (t ))
t =0
dt
Single-Stage OTAs
Any SC circuit in a given phase can always be represented

in the form:
Cf
Ci
Vin
Cp
Vout
Cload
Single-Stage OTAs
In each phase of the SC operation we can define the feedback factor as :
1
Cf
s (Ci + Cp )
=
=
1
1
Ci + Cp + Cf
+
s(Ci + Cp ) s(Cf )
(series - parallel feedback
CL = Cload + (Ci + Cp )
A f (s ) =
A0
A(s )
, where A(s ) =
1 + A(s )
1 + s w
p1
c = 3dB = u =
u
A0
where u is the unity - gain frequency,
c frequency of the closed - loop pole.

=
1
u
Single-Stage OTAs
(Fully-differential Realizations)
Advantages:
better substrate-noise rejection;
better PSRR;
better output swing (dynamic range is improved by 2)
better robustness to charge-injection.
Drawbacks:
Passives are duplicated and there is a need o a CMFB circuit
Z2
Z2
v1
Z1
v1+
Z1
vo
v1-
Z1
-+
+ Z2
single-ended
fully-differential
vo+
vo-
Single-Stage OTAs
Fully-differential Folded-Cascode OTA

VDD
VB2
vin+
M10
AMPOP CASCODE DOBRADO

COMPLETAMENTE DIFERENCIAL
M11
I/2
I/2
M1
M2
I/2
I/2
vin-
M3
M4
VB3
vout+
vout-
VB1
M9
VB4
M5
M6
M7
M8
Circuito
de CMFB
Vcontrol
Single-Stage OTAs
Common-Mode feedback circuits (CMFB)

1 Continuous-time version:
Vdd
Vdd
Vdd
Vout-
Vout+
Ibias
20 k
20 k
Vref = Vdd/2
1.5 pF
Vcontrol
1.5 pF
Single-Stage OTAs
Common-Mode feedback circuits (CMFB)

2 SC version:
Vout+
1
Cs
Vcontrol
Vref = Vdd/2
Cc
1
Cs
Vout-
Vbias
Cc
1
Vref = Vdd/2
Vdd
Two-stage Miller-Compensated Amplifiers
Two-Stage Amplifiers
(Basic Topology)
Cc
Vin
A1
-A2
Vout
+
Andar diferencial
de entrada
2 andar de ganho
(fonte-comum)
buffer de sada
(Classe A, B ou AB)
(DC gain)
M5
Vbias
Vin-
M6
Vin+
M1
M2
Rc
Cc
Vout
v1
M3
M4
M7
AV = AV 1 AV 2 1
AV 1 = gm1, 2 rout = gm1, 2 (rds 2 rds 4)
AV 2 = gm7 (rds 6 rds 7 )
(Medium/High frequencies)
In node v1, the resulting equivalent capacitance is :
Ceq = Cc (1 + AV 2 ) [Miller Theorem, Sedra 1991]
v1
= gm1, 2 Zout
vin
1
, for medium/high freqs. :
Zout = rds 2 rds 4
s Ceq
1
1
.
Zout
s Ceq s Cc AV 2
AV 1 =
AV (s ) =
gm1, 2
gm1, 2
vout
AV 2
=
vin
s Cc AV 2
s Cc
GBW (a 0dB) = wu AV ( j wu ) = 1 wu =
I Cc max . I D 5 2 I D1, 2
d (vout )
=
=
=
SR =
dt max .
Cc
Cc
Cc
gm1, 2
Cc
(Frequency response and Compensation)
If the 2 poles are close to each other
a compensation capacitor is required
(Cc);
M5
Vbias
Vin-
M1
M6
Vin+
M2
Rc
Vout
Cc
The Miller compensation technique

consists in adding Cc (assuming Rc = 0)
in order to make Pole-splitting;
v1
M3
M4
M7
2 Polo
The Miller capacitance, Cc, moves the

first pole to lower frequencies;
1 Polo
The series-shunt feedback moves the

second pole to higher frequencies.
Rc
v1
Cc
Vout
gm1*vin
R1
C1
gm7*v1
R1 = (rds 4 rds 2)
R 2 = (rds6 rds7 )
C1 = Cdb 2 + Cdb 4 + Cgs 7
C 2 = Cdb7 + Cdb6 + Cgd 6 + CL
R2
C2
Assuming Rc = 0 and appying KVL to nodes v1 and vout :
v1
vout
+ s C 1 + (v1 vout ) s Cc + gm 1 vin = 0

R1
+ s C 2 + (vout v1) s Cc + gm 7 v1 = 0
R2
AV =
vout
= gm 1 R1 gm 7 R 2
vin
1 s Cc
gm 7
1 + s (R1 R 2 gm 7 Cc + R 2 (C 2 + Cc ) + R1(C 1 + Cc )) + s 2 (R1 R 2 [C 1 C 2 + Cc (C 1 + C 2 )])
The circuit has, in fact, 2 poles and a zero with positive real part :
1
p1
gm 7 R 1 R 2 Cc
p2
gm 7 Cc
gm 7
=
C1 C 2
C 1 C 2 + C 2 Cc + C 1 Cc
+ C 2 + C1
Cc
gm 7
wz =
Cc
In prcatical designs we have :
Cc >> C 1,
Cc C 2 ,
gm 1 >>
1
1
e gm 7 >>
, resulting in :
R1
R2
1
R1 C 1
gm 7
1
>>
p2
C2
R2 C 2
The dominant pole, P1, makes that :
p1 <<
GBW (a 0 dB ) = u = p1 AV ( f << ) =
=
1
gm 1
gm 1 gm 2 R1 R 2 =
gm 7 R1 R 2 Cc
Cc
In order to guarantee stability :
gm 7
gm 7
gm 1
, z =
<< p 2 =
(at least 2 times)
Cc
C2
Cc
Ideally gm 7 >> gm 1 and the zero is at very high frequencie s ,
GBW =
but sometimes is not like this! If Cc > C 2 and gm 7 gm 1

the zero degrades substantia lly the phase margin!
Solution : Use Rc in series with Cc , since the position of the pole
depends on Rc in the form :
1
z =
1
Rc Cc
gm 7
Better output swing
Always stable after proper compensation for CL< CLmx;
Very simple biasing circuit;
Lower power dissipation when feedback factors, ,
Are small;
Slower (50% of the speed is lost due to the compensation);
Requires Cc and Rc for compensation. Rc can be made
using a transistor;
Advanced Two-Stage Topologies
Two-stage cascode-compensated OTA (1)

VDD
Iout
VDD
Icas
I bias + cmfb
2
VDD
VBp1
VDD
VBn
VREFP
Mc
vcm
Mcp
voutp
nb
VBnc
VSS
M3
vinp
na
VSS
M6
M8
VBpc
M2
VDD
VBp2
VBp1
M1
vinn
voutn
VDD
M4 Ccomp
M5
M7
VSS
VSS
VBn
nc
Folded-cascode first-stage
followed by two common-source
second-stages;
Cascoded-Miller compensation.
Main OTA
Icmfb
VSS
SC CMFB
I PB
I PB
I Cas
mf
I Cas
mf
1
I Bias
+ I Cas
2
mf
I Bias
+ I Cas
2
mf
IOut
mf
Bias
Two-stage hybrid-compensated OTA (2)

followed by fully-differential
common-source second-stage;
Hybrid cascoded-Miller compensation.
Main OTA
2
I PB
I PB
I Cas
mf
I Cas
mf
2 I Out
mf
I Bias
mf
I Cas
mf
I Bias
+ I Cas
2
mf
Bias
I Out
mf
SC CMFBs
Two-stage OTA with positive feedback (3)

VCM2
VDD
VDD
VDD
VDD
IBias
VB5
n1
vinn
voutn
VB5
M1
M5 Ccomp/2
vinp VB4
M2
VDD
ICas
M8
M4
voutp
nb
nc
M3
na
M6 Ccomp/2
M7
VCM1
VSS
VSS
VB9
n2
M9
2IOut
Main OTA
VSS
followed by fully-differential
common-source second-stage;
Hybrid cascoded-Miller
compensation. Local positivefeedback applied to the NMOS
cascode devices of the first
stage.
[Randall Geiger and others,
ISCAS03, CICC03]
SC CMFBs
Design of multi-stage OTAs

(How to extract the equations for the Optimizer? Step #1)
Basic 3rd. Order

example
Step #1: Derive the small-signal model of half-circuit making a minimum

of simplifications;

(How to extract the equations for the Optimizer? Step #2)
Step #2: Separate all nodes

using the Y-parameters
technique

(How to extract the equations for the Optimizer? Steps #3 to #5)
Step #3: Find node equations (voltages, va, vb, vc=vo, etc and current);
Step #4: Solve, collect, simplify with using a symbolic solver and
get the open-loop transfer function (vo/vin);
Step #5: Port the open-loop transfer function into the Optimizer

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Design of CMOS Amplifiers

December, 2008 (revised, Jan. 2010)

Joo Goes (DEE) - 2010

Basic Amplifier Topologies

Joo Goes (DEE) - 2010

Basic Amplifier Topologies

Gain stage with high input impedance

For low frequencies:

Av = gm1 (rds1 rds 2 )

Basic Amplifier Topologies

Joo Goes (DEE) - 2010

Basic Amplifier Topologies

In low-frequencies and considering

Basic Amplifier Topologies

(gm1 + gds1 + gds2 + gmb1 ) + (C gs1 + C L' ) s

C L' = C L + C sb1 + Cdb 2 + C gd 2 + C gs1

The zero has negative real part!!

gds1 + gds 2 + gmb1 + gm1

Basic Amplifier Topologies

For the emitter-follower:

For the source-follower:

This means that, for the same current, the emitter-follower

Basic Amplifier Topologies

Joo Goes (DEE) - 2010

Basic Amplifier Topologies

Joo Goes (DEE) - 2010

Basic Amplifier Topologies

Enhanced Voltage Followers: (a) NMOS-type supper-source follower (SSF); (b)

Joo Goes (DEE) - 2010

Joo Goes (DEE) - 2010

Main goal: increase rout!

Joo Goes (DEE) - 2010

Disadvantage: Output dynamicrange decreases!

Joo Goes (DEE) - 2010

Disadvantage: Output dynamicrange decreases!

rds 2 (rds 4 gm4 )

Vout > 2*Vdsat if n=1!

Systematic offset problem

Joo Goes (DEE) - 2010

Much better solution!

M7 e M8 biased in the limit of

Joo Goes (DEE) - 2010

[Hosticka, 1979, Bult, 1990,

Use an extra amplifier in a

rout ( gm 6 rds 6 ) rds 8 (1 + A )

Use regulated-cascode employing a

Joo Goes (DEE) - 2010

Basic cascode Topologies

Joo Goes (DEE) - 2010

Advanced amplifier topologies

Vbias > Vdsat-M1 +VGS-M2 = Vdsat-M1 +

Joo Goes (DEE) - 2010

Advanced amplifier topologies

It is basically a common-gate amplifier cascoded

rout (gm2 rds1 rds 2 ) rout fonte

, only if we use a cascode current - source

( gm1 (rds1 rds 2 )) gm2 rds 2 rout fonte

Rule: Output impedance, rout, for 2 devices, M1 and

Joo Goes (DEE) - 2010

Advanced amplifier topologies

(++) input and output common-mode levels

(--) Slower, because the is a PMOS device

Joo Goes (DEE) - 2010

Joo Goes (DEE) - 2010