FIR FILTER DESIGN USING VERILOG

FIR filters are is widely used in different applications such as biomedical, communication
and control due to its easily implementation, stability and best performance. Its simplicity
makes it attractive for many applications where it is need to minimize computational
requirements.
Filters play an important role for removal of unwanted signal or noise from original input
signal by removing the selected frequencies from incoming signal. They became much
popular due to the increase of the digital signal processing.

Comparison between FIR and IIR Filters

The non recursive (FIR) and recursive (IIR) filters have different characteristics for
numbers of applications. The non recursive filters are chosen due to its best performance of
numerical operations, differentiation and integration. The table 2.1 below shows the comparison
between FIR and IIR filters.
IIR
More Efficient
Analog Equivalent

FIR
Less Efficient
No Analog Equivalent

May Be Unstable

Always Stable

Non-Linear Phase Response

Linear Phase Response

No Efficiency Gained by Decimation

Decimation Increases Efficiency

VERILOG CODE FOR FIR FILTER

// main module FIR
module filterfir(clk,rst,x,dataout);
input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
dff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
dff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
dff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
dff u8(clk,rst,d13,d14);
assign m5=d14>>h4;

assign dataout=d3+m5;
endmodule

module dff(clk,rst,d,q);// sub module d flipflop

input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:07:00 01/29/2014
// Design Name: filterfir
// Module Name: D:/fft/floating_mul/tst.v
// Project Name: floating_mul
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: filterfir
//
// Dependencies:
//
// Revision:

// Revision 0.01 - File Created

// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tst;
// Inputs
reg clk;
reg rst;
reg [7:0] x;
// Outputs
wire [9:0] dataout;
// Instantiate the Unit Under Test (UUT)
filterfir uut (
.clk(clk),
.rst(rst),
.x(x),
.dataout(dataout)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
x = 0;
#100;
rst = 1;
#100;
rst = 0;
x = 8'd5;
#100;
x = 8'd10;
#100;
x = 8'd12;
#100;
x = 8'd15;
#100;
x = 8'd16;

#100;

end
always begin #50 clk=~clk; end
endmodule

module fir_filter(
input clock,
input reset,
input wire[15:0] input_sample,
output reg[15:0] output_sample);
parameter N = 13;
reg signed[15:0] coeffs[12:0];
reg [15:0] holderBefore[12:0];
wire [15:0] toAdd[12:0];
always @(*)
begin
coeffs[0]=6375;
coeffs[1]=1;
coeffs[2]=-3656;
coeffs[3]=3;
coeffs[4]=4171;
coeffs[5]=4;
coeffs[6]=28404;
coeffs[7]=4;
coeffs[8]=4171;
coeffs[9]=3;
coeffs[10]=-3656;
coeffs[11]=1;
coeffs[12]=6375;
end
genvar i;
generate
for (i=0; i<N; i=i+1)
begin: mult
multiplier mult1(
.dataa(coeffs[i]),
.datab(holderBefore[i]),
.result(toAdd[i]));
end
endgenerate

always @(posedge clock or posedge reset)

begin
if(reset)
begin
holderBefore[12] <= 0;
holderBefore[11] <= 0;
holderBefore[10] <= 0;
holderBefore[9]
<= 0;
holderBefore[8]
<= 0;
holderBefore[7]
<= 0;
holderBefore[6]
<= 0;
holderBefore[5]
<= 0;
holderBefore[4]
<= 0;
holderBefore[3]
<= 0;
holderBefore[2]
<= 0;
holderBefore[1]
<= 0;
holderBefore[0]
<= 0;
output_sample
<= 0;
end
else
begin
holderBefore[12] <= holderBefore[11];
holderBefore[11] <= holderBefore[10];
holderBefore[10] <= holderBefore[9];
holderBefore[9]
<= holderBefore[8];
holderBefore[8]
<= holderBefore[7];
holderBefore[7]
<= holderBefore[6];
holderBefore[6]
<= holderBefore[5];
holderBefore[5]
<= holderBefore[4];
holderBefore[4]
<= holderBefore[3];
holderBefore[3]
<= holderBefore[2];
holderBefore[2]
<= holderBefore[1];
holderBefore[1]
<= holderBefore[0];
holderBefore[0]
<= input_sample;
output_sample <= (input_sample + toAdd[0] + toAdd[1] +
toAdd[2] + toAdd[3] + toAdd[4] + toAdd[5] +
toAdd[6] + toAdd[7] + toAdd[8] + toAdd[9] +
toAdd[10] + toAdd[11] + toAdd[12]);
end
end

endmodule