M

icroprocessor

A microprocessor is an electronic device which computes

on the given input similar to CPU of a computer. It is
made by fabricating millions(or billions) of transistors on
a single chip.

History of Microprocessor
Microprocessor journey started with a 4-bit processor
called 4004, it was made by Intel corporation in 1971. It
was 1st single chip processor. Then the idea was
extended to 8-bit processors like 8008, 8080 and then
8085 (all are Intel products). 8085 was a very successful
one among the 8-bit processors, however its application
is very limited because of its slower computing speed and
other
quality
factors.
Some years later Intel came up with its 1st 16-bit
processors 8086.

Intel

8086:

The 8086 is a 16-bit microprocessor chip designed by

Intel corporation in between early 1976 and mid-1978.
The release of Intel's 8086 microprocessor in 1978 was a
watershed moment for personal computing.

Elements of the 8086 Microprocessor

Architecture
The 80x86 has:
16-bit internal data bus
20-bit address bus: 220 = 1,048,576 = 1 megabyte
Control bus
Execution Unit
Bus Interface Unit
Among the on-chip peripherals are:
2 direct memory access controllers (DMA)
Three 16-bit programmable timers
Clock generator
Chip select unit
Programmable Control Registers

The 8086

Processor Model

The simplified block diagram of the 80x86 processor

model is organized
as two separate processors :
1)Bus Interface Unit (BIU)
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8086 Architecture

2)Execution Unit (EU).

Bus Interface Unit (BIU)

The BIU provides hardware functions. Including
generation of the memory and I/0 addresses for the
transfer of data between itself and the outside world.
Following functions are supported by BIU.
It provides a full 16 bit bidirectional data bus and 20
bit address bus.
It sends address of memory or I/O.
It fetches instruction from memory.
It reads data from port/memory.
It writes data into port/memory.
It supports instruction queuing .
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8086 Architecture

 It makes 8086s interface to the outside world.

The BIU uses a mechanism known as an instruction
stream queue to implement a pipeline architecture.
If the BIU is already in the process of fetching an
instruction when the EU request it to read or write
operands from memory or I/O, the BIU first completes
the instruction fetch bus cycle before initiating the
operand read / write cycle.
The BIU also contains a dedicated adder which is
used to generate the 20bit physical address.

Execution Unit (EU)

The EU receives program instruction codes and data from
the BIU, executes these instructions, and stores the
results in the general registers.
Following functions are supported by BIU.
The Execution unit is responsible for decoding and
executing all instructions.
The EU extracts instructions from the top of the
queue in the BIU.
During the execution of the instruction, the EU tests
the status and control flags and updates them based
on the results of executing the instruction.
If the queue is empty, the EU waits for the next
instruction byte to be fetched and shifted to top of
the queue.
The EU accesses the queue from the output end. It
reads one instruction byte after the other from the
output of the queue.
It tells BIU from where to fetch instructions or data,
decodes instructions & execute instructions.
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8086 Architecture

The main linkage between the two functional blocks is

the instruction
queue, with the BIU looking ahead of the current
instruction being executed in order to keep the queue
filled with instructions for the EU to decode and operate
on.

Instruction Queue
It is of 6 Bytes.
To increase the execution speed, BIU fetches as many
as six instruction bytes ahead to time from memory.
It operates on the principle first in first out (FIFO).
Then all bytes are given to EU one by one.
This pre-fetching operation of BIU may be in parallel
with execution operation of EU.

It improves the execution speed of the instruction.

The Fetch and Execute Cycle

The organization of the processor into a separate BIU and
EU allows the fetch and execute cycles to overlap. To see
this, consider what happens when the 8086 is first
started. Figure 3.2.

8086 Architecture

1. The BIU outputs the contents of the instruction pointer

register (IP) onto the address bus, causing the selected
byte or word in memory to be read into the BIU.
2. Register IP is incremented by one to prepare for the
next instruction fetch.
3. Once inside the BIU, the instruction is passed to the
queue: a first-in/first-out storage register sometimes
likened to a pipeline.
4. Assuming that the queue is initially empty, the EU
immediately draws this instruction from the queue and
begins execution.
5. While the EU is executing this instruction, the BIU
proceeds to fetch a new instruction. Depending on the
execution time of the first instruction, the BIU may fill the
queue with several new instructions before the EU is
ready to draw its next instruction.
6. The cycle continues, with the BIU filling the queue with
instructions and the EU fetching and executing these
instructions. The BIU is programmed to fetch a new
instruction whenever the queue has room for two
additional bytes. The advantage to this pipelined
architecture is that the EU can execute instructions
(almost) continually instead of having to wait for the BIU
to fetch a new instruction. This is shown schematically in
the following Figure

8086 Architecture

The Wait mode

There are three conditions that will cause the EU to enter
a "wait" mode.
I.

II.

When an instruction requires access to a memory

location. The BIU must suspend fetching instructions
and output the address of this memory location. After
waiting for the memory access, the EU can resume
executing instruction codes from the queue, and the
BIU can resume filling the queue.
When the instruction to be executed is a jump
instruction. In this case, control is to be transferred to
a new address. The EU must wait while the
instruction at the jump address is fetched. Any bytes
presently in the queue must be discarded (they are
overwritten).
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8086 Architecture

III.

During the execution of slow-executing instructions.

The 8086 Programming Model

The programming model for a microprocessor shows the
various internal registers that are accessible to the
programmer. The Following Figure is a model for the
8086. In general, each register has a special function.

Registers of 8086
General Purpose Registers
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8086 Architecture

Pointer and Index Registers

Segment Registers
Instruction Pointer
Status Flags

General Purpose Registers

There are four 16-bit general purpose registers:

AX
BX
CX
DX

Each of these 16-bit registers are further subdivided into

two 8-bit registers.
AX
BX
CX
DX

AH

AL

BH

BL

CH

CL

BH

DL

1. AX
Register: AX register is
also known as accumulator register that stores operands
for arithmetic operation like divided, rotate.
2.BX Register: This register is mainly used as a base
register. It holds the starting base location of a memory
region within a data segment.

8086 Architecture

3.CX Register: It is defined as a counter. It is primarily

used in loop instruction to store loop counter.
4.DX Register: DX register is used to contain I/O port
address for I/O instruction.

Pointers and Index Registers

Following four registers are under this category:
1. Stack Pointer (SP),
2. Base Pointer (BP),
3. Source Index (SI),
4. Destination Index (DI).
Following Registers can also be used as a general Purpose
Registers.
1. Stack Pointer (SP) is a 16-bit register pointing to
program Stack, also contains 16-Bit offset address.
2. Base Pointer (BP) is a 16-bit register pointing to data
in stack segment. BP register is usually used for
based indexed or register indirect addressing.
3. Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect
addressing, as well as a source data address in string
manipulation Instructions
4. Destination Index (DI) is a 16-bit register. DI is used
for indexed, based indexed and register indirect
addressing, as well as a destination data address in
string manipulation instructions.
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8086 Architecture

Segment Register
There are four segment registers in Intel 8086:
1. Code Segment Register (CS),
2. Data Segment Register (DS),
3. Stack Segment Register (SS),
4. Extra Segment Register (ES).

A segment register points to the starting address of a

memory segment.
For Example: The code segment register points to the
starting address of the code segment.
The data segment register points to the starting address
of the data segment, and so on.
The maximum capacity of a segment may be up to 64 KB.

Code segment (CS):It is a 16-bit register containing address of 64 KB segment

with processor instructions.
The processor uses CS
segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be
changed directly. The CS register is automatically
updated during far jump, far call and far return
instructions .

Stack segment (SS):It is a 16-bit register containing address of 64KB segment

with program stack. By default, the processor assumes
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8086 Architecture

that all data referenced by the stack pointer (SP) and

base pointer (BP) registers is located in the stack
segment. SS register can be changed directly using POP
instruction.

Data segment (DS):It is a 16-bit register containing address of 64KB segment

with program data. By default, the processor assumes
that all data referenced by general registers (AX, BX, CX,
DX) and index register (SI, DI) is located in the data
segment.

Extra segment (ES):It is a 16-bit register containing address of 64KB segment,

usually with program data. By default, the processor
assumes that the DI register references the ES segment
in string manipulation instructions. It is possible to
change default segments used by general and index registers
by prefixing instructions with a CS, SS,DS or ES prefix.

Concept of Segmented Memory

It allows the memory addressing capacity to be 1
Mbytes.
It allows instruction code, data stack and portion of
program to be more than 64KB long.
It facilitates use of separate memory areas for
program, data and stack.
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8086 Architecture

 It permits a program or its data to be put in different

areas of memory
In this program can be relocated which is very useful
in multiprogramming i.e.multitasking becomes easy.

Instruction Pointer
The Instruction Pointer (IP) in 8086 acts as a Program
Counter. It points to the address of the next instruction to
be executed. Its content is automatically incremented
when the execution of a program proceeds further. The
contents of the IP and Code Segment Register are used to
compute the memory address of the instruction code to
be fetched. This is done during the Fetch Cycle.
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8086 Architecture

Status Flags
Status Flags determines the current state of the
accumulator. They are modified automatically by CPU
after mathematical operations. This allows to determine
the type of the result. 8086 has 16-bit status register. It is
also called Flag Register or Program Status Word (PSW).
There are nine status flags and seven bit positions remain
unused.

The following Figure shows the bit definitions for the 16bit flag register.
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8086 Architecture

 Six of the flags are status indicators reflecting

properties of the result of the last arithmetic or logical
instruction
8086 flag word. DF, IF, and TF can be set or reset to
control the operation of the processor.
The remaining flags are status indicators. Bits marked X
are undefined.

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8086 Architecture