III.A.3.

Control System Design Using Root locus

Basic Idea:
Performance specifications
yield Allowable Region for closed loop poles
+
Root locus
yield trajectories of closed loop poles as K:0

Possible design
if portion of root locus inside Allowable Region

Graphical interpretation:
Allowable
Region

Root locus
Possible
Design
Point

( Method yields ballpark design values, may need fine tuning)

Recall: Performance specifications and allowable region

P.O. specification
Ts specification
Tp specification

Allowable Region
for the set of
specifications

cos

 Design Case 1: Gain controller (C(s)=K)

TextBook Example 7.4
R(s)

E(s)

G (s)

U(s)

G(s)

Y(s)

1
s ( s 4 )[( s 4 ) 2 16 ]

- Specification: 0. 707

Allowable Region: 45 0

- Root locus meet allowable region at s0 1.4 1.4 j

- Take s0 1.4 1.4 j as design point

- Corresponding value for K? Use MR

1
K
s0 s0 4 s0 4 4 j s0 4 4 j 126
| G(s0 ) |
1.9 2.9

3.8

6.0

- Note: system is 4th order another pair of complex roots

from the other two loci
- System is type I, K v ?

126
Kv lim s
2
s 0

16
s
(
s
)
(
s
)
4
4

ess for ramp input 1

- Judge: design acceptable?

 Design Case 2: Dynamic controller (C(s) known)

R(s)

E(s)

+
-

G(s)

C(s)

U(s)

G(s)

Y(s)

1
, p 1 0, p 2 1
s ( s 1)

- Design Objectives: P.O. 16 %, Ts 0.95 sec

0.5, n 4.2

Allowable Region: 60 0 , n 4.2

- Root locus with C(s)=K never in Allowable Region,

design not possible with Gain controller
- Use dynamic controller:

C (s)

K ( s 2)
( s 10)

, root locus

pass through Allowable Region, design possible!

- Take s0 4.3 6.4 j as design point

- K=?

s 0 s 0 1 s 0 10

70

| s0 2 |
- CL system has a third pole technique to estimate its value:
s[( s 10)(s 1)] 70( s 2) ( s r3 )[( s 4.3)2 6.4 2 ] r3 2.4

Third pole close to zero at s= -2

CL dynamics dictated by complex pole pair and residual
effects of approximate pole/zero cancellation
- System is type I, Kv = ?
70 s ( s 2)
K v lim
14
s 0 s ( s 1)( s 10 )

- Judge: design acceptable?

- More details: closed loop system:

70(s 2)
70(s 2)
Y (s)
s(s 1)(s 10)

70
(

2
)
s
(s 2.4)[(s 4.3)2 6.42 ]
R(s) 1
s(s 1)(s 10)
Additional 3rd pole

Actual P.O. is 21%

because system is not
strictly 2nd order

Complex pole
corresponding to
0.56, n 7.7

P.O . 14 %

 Design Case 3: Dynamic controller (C(s) unknown)

R(s)

E(s)

+
-

G (s)

C(s)

U(s)

Y(s)

G(s)

1
, p1 0 , p 2 1
s ( s 1)

- Design Objectives: P.O. 16 %, Ts 0.95 sec

0.5, n 4.2

Allowable Region: 60 0 , n 4.2

- Root locus with C(s)=K never in Allowable Region,

design not possible with Gain controller
- Try dynamic controller of the form:

C (s)

K (s z)
( s p)

- C(s) has zero location at s = - z, and pole location at s = - p

- To determine K, z, p
(i) Pick design point inside allowable region:

s0 4.5 j4.5 3
(ii) Place zero location somewhere to the left of s0 , e.g.,
z= 7 (Controller zero at s = -z = -7)
CE becomes:
K ( s 7)
a( s ) 1

s( s 1)( s p )

(iii) Use PR to determine pole location (or value of p)

72.2o 120o 114.2 o 180o 360o l

s0

18o x 24 p 28.5
Controller pole
at s=-p = -28.5

72.20
-7 -4.5

114.20 120

-1

s 0 s 0 1 s 0 28 . 5
240
- K= ? MR K
| s0 7 |

- Third pole? s( s 1)(s 28.5) 240( s 7)

( s r3 )[(s 4.5) 4.5 3 ]

2

r3 20.5

Third pole far from zero at s= -7

Closed loop dynamics dictated by complex pole pair
and additional effects of a pole and a zero
- System is type I, Kv ?
240 s( s 7 )
58 .9
s 0 s( s 1)( s 28 .5)

K v lim

- Judge: design acceptable?

- More details: closed loop system:

240(s 7)
240(s 7)
Y (s)
s(s 1)(s 28.5)

240
(

7
)
s
R(s) 1
(s 20.37)[(s 4.57)2 (4.57 3)2 ]
s(s 1)(s 28.5)
Additional 3rd pole
Complex pole
corresponding to
Actual P.O. is 36%
because system is not
strictly 2nd order and not
much pole zero
cancellation

0.5028, n 9.08

P.O . 16 %

III.A.4. PID Controller

Use a 2nd order system for illustration
System
R(s)

where

e(t)

C(s)

u(t)

G(s)

Y(s)

A
G(s)
( 1s 1)( 2 s 1)

System of various orders and forms can follow similar

steps for analyzing PID controllers

P (Proportional)
Controller
Control
Signal

u(t) = K e(t)
C(s) = K

I (Integral)
Controller
u (t )

C ( s)

Root
Locus

Transient
Performance

Steady State
Performance

K
TI

e( )d ,

PI (ProportionalIntegral) Controller
u(t ) Ke(t )

ess

1
,
1 Kp

K p KA

e( )d ,

C ( s ) K 1
T
s
I

K
TI s

Larger K
Smaller
Higher P.O.
Actually,
( 1 2 )

1 2 (1 KA)
- Type 0
- ess for step input:

K
TI

- Add a pole in origin

- Root locus:
-- Lower
-- Instability at large K
- Inferior than P-control

- Add a zero and a pole

- Root locus:
-- No instability for large K
-- loci better damped
than I-control
-- Still inferior than P-control

- Type 1
- ess for ramp input:

- Type = 1
- ess for ramp input:

ess

1
KA
, Kv
TI
Kv

- Better than P-control

ess

1
KA
, Kv
TI
Kv

- Similar as I-control (or better

because no instability)

PID (Proportional-IntegralDerivative) Controller

1
u(t ) K e(t )
TI

Control
Signal

Root
Locus

Transient
Performance

Steady State
Performance

e( )d TD

de(t )
,
dt

1
C ( s ) K 1
TD s
TI s

or

- Add two zero and a pole

- Root locus:
-- No instability for large K
-- loci better damped
than P-control
- Type 1
- ess for ramp input:
ess

1
KA
, Kv
TI
Kv

- Similar as PI-control

oo

xx

 Disk Drive Read System using Root Locus Design

- Case 1: Proportional Control C(s)=Ka
Disturbance

* Recall performance in II.A.3 and II.C.

5.10

* Performance agree with Root Locus

1

K a 80

K a 5000
0
s( s 20)( s 1000)

* For large Ka, loci cross

imaginary axis and
become unstable

K a 10

K a 20

K a 10

K a 20

(Textbook Fig. 4.36)

K a 80

* 3rd pole at s=-1000 going

towards ve infinity
* System closely approximated
as 2nd order system
Closed loop responses

- Case 2: Proportional-Derivative (PD) control

C ( s ) K D ( s 1) (choosing K P K D )

7.51

* Root Locus
1

K D ( s 1)5000
0
s( s 20)( s 1000)

* No passing of imaginary
axis System stable
for all KD
* Choose design point:
KD=91.3
Closed loop poles: -509.52 + 464.66j , -0.96

Y(s)
Head position

* Closed loop zero and pole near -1

their effects roughly cancel out
* System roughly approximated as 2nd order system
* Closed loop response at design point
For time from 0 to 0.1 sec

For time from 0 to 2 sec

Slow drift to
final value
Quick rise to 97%
of final value

* Performance

Desired
performance
Achieved!