TABUNAN, JHON DAVID H.

JAN. 12,2014
EE42FB1

MICROPROCESSOR
ASSIGNMENT Midterm

The control characters in ASCII

0 (null, NUL , \0 , ^@ ), originally intended to be an ignored character, but now used by

many programming languages to mark the end of a string.

7 (bell, BEL , \a , ^G ), which may cause the device receiving it to emit a warning of some
kind (usually audible).

8 (backspace, BS , \b , ^H ), used either to erase the last character printed or to overprint it.

9 (horizontal tab, HT , \t , ^I ), moves the printing position some spaces to the right.

10 (line feed, LF , \n , ^J ), used as the end of line marker in most UNIX systems and
variants.

11 (vertical tab, VT , \v , ^K ), vertical tabulation.

12 (form feed, FF , \f , ^L ), to cause a printer to eject paper to the top of the next page, or
a video terminal to clear the screen.

13 (carriage return, CR , \r , ^M ), used as the end of line marker in Mac OS, OS9, FLEX (and variants). A carriage return/line feed pair is used by CP/M-80 and its derivatives
including DOS and Windows, and by Application Layer protocols such as HTTP.

27 (escape, ESC , \e (GCC only), ^[ ).

127 (delete, DEL , ^? ), originally intended to be an ignored character, but now used in some
systems to erase a character. Also used by some Plan9 console programs to send an interrupt
note to the current process.

TASM COMMAND LINES

The acceptable 6502 opcode mnemonics for TASM are as follows:
ADC
BRK
INC
PHP
STX

AND
CLC
INX
PLA
STY

ASL
CLD
INY
PLP
TAX

BCC
CLI
JMP
ROL
TAY

BCS
CLV
JSR
ROR
TSX

BEQ
CMP
LDA
RTI
TXA

BNE
CPX
LDX
RTS
TXS

BMI
CPY
LDY
SBC
TYA

BPL
DEC
LSR
SEC

BVC
DEX
NOP
SED

BVS
DEY
ORA
SEI

BIT
EOR
PHA
STA

TASM also supports the following instructions that are part of the Rockwell R65C02
and R65C00/21 microprocessor instruction sets. Those that are marked as set A are
applicable to the R65C02 and those marked as set B are applicable to the R65C00/21
(A+B for both):
Mnemonic
Description
Address Mode Set
--------------------------------------------------------------ADC
Add with carry
(IND)
A
AND
And memory with A
(IND)
A
BIT
Test memory bits with A
ABS,X
A
BIT
Test memory bits with A
ZP,X
A
BIT
Test memory bits with A
IMM
A
CMP
Compare memory with A
(IND)
A
DEC
Decrement A
A
A
EOR
Exclusive OR memory with A (IND)
A
INC
Increment A
A
A
JMP
Jump
(ABS,X)
A
LDA
Load A with memory
(IND)
A
ORA
OR A with memory
(IND)
A
SBC
Subtract memory form A
(IND)
A
STA
Store A in memory
(IND)
A
STZ
Store zero
ABS
A
STZ
Store zero
ABS,X
A
STZ
Store zero
ZP
A
STZ
Store zero
ZP,X
A
TRB
Test and reset memory bit ABS
A
TRB
Test and reset memory bit ZP
A
TSB
Test and set memory bit
ABS
A
TSB
Test and set memory bit
ZP
A
BRA

Branch Always

REL

A+B

BBR0
BBR1
BBR2
BBR3
BBR4
BBR5
BBR6
BBR7

Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch

on
on
on
on
on
on
on
on

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

0
1
2
3
4
5
6
7

Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset

ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL

A+B
A+B
A+B
A+B
A+B
A+B
A+B
A+B

BBS0
BBS1
BBS2
BBS3
BBS4
BBS5
BBS6
BBS7

Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch

on
on
on
on
on
on
on
on

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

0
1
2
3
4
5
6
7

Set
Set
Set
Set
Set
Set
Set
Set

ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL
ZP,REL

A+B
A+B
A+B
A+B
A+B
A+B
A+B
A+B

MUL

Multiply

Implied

PHX
PHY
PLX

Push Index X
Push Index Y
Pull Index X

Implied
Implied
Implied

A+B
A+B
A+B

PLY

Pull Index Y

RMB0
RMB1
RMB2
RMB3
RMB4
RMB5
RMB6
RMB7

Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset

Memory
Memory
Memory
Memory
Memory
Memory
Memory
Memory

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

SMB0
SMB1
SMB2
SMB3
SMB4
SMB5
SMB6
SMB7

Set
Set
Set
Set
Set
Set
Set
Set

Memory
Memory
Memory
Memory
Memory
Memory
Memory
Memory

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

Implied

A+B

0
1
2
3
4
5
6
7

ZP
ZP
ZP
ZP
ZP
ZP
ZP
ZP

A+B
A+B
A+B
A+B
A+B
A+B
A+B
A+B

0
1
2
3
4
5
6
7

ZP
ZP
ZP
ZP
ZP
ZP
ZP
ZP

A+B
A+B
A+B
A+B
A+B
A+B
A+B
A+B

Addressing modes are denoted as follows:

ABS
ZP
ABS,X
ZP,X
ABS,Y
ZP,Y
A
(IND,X)
(IND),Y
(IND)
#IMM
REL
ZP,REL
Implied

Absolute
Zero Page
Absolute X
Zero Page X
Absolute Y
Zero Page Y
Accumulator
Indirect X
Indirect Y
Indirect
Immediate
Relative (Branch instructions only)
Zero Page, Relative
Implied

Note that Zero Page addressing can not be explicitly requested. It is used if the value
of the operand is representable in a single byte for the applicable statements.
The '-x' command line option can be used to enable the extended instructions. A '-x'
with no digit following will enable the standard set plus both extended sets. The 6502
version of TASM uses three bits in the instruction class mask to determine whether a
given instruction is enabled or not. Bit 0 enables the basic set, bit 1 enables set A
(R65C02) and bit 2 enables set B (R65C00/21). The following table shows various
options:
Class Mask

Enabled Instructions
BASIC
R65C02 R65C00/21
-------------------------------------------1
yes
no
no
2
no
yes
no

3
4
5
6
7

yes
no
yes
no
yes

yes
no
no
yes
yes

no
yes
yes
yes
yes

Thus, to enable the basic set plus the R65C02 instructions, invoke the '-x3' command
line option.

HEXADECIMAL ASCII CODE