INTRODUCTION

In this experiment, we were required to design a simple office

automation system in Figure 4.1 as stated in the lab manual. The design of
the logic circuit is to control the door, light and fan in the office. An encoder
will generate a binary number from 000 to 111 according to the office time
as shown in the figure. The system is an 8-bit as the timer has 8 different
time to be its input to the encoder.

This report consists of procedures and results from laboratory 4 and

laboratory 5 experiments. In laboratory 4, Quartus II and ModelSim-Altera
was used to draw a logic circuit and to simulate the design to get the
waveform.
In laboratory 5, 74 series ICs (integrated circuits) was used to
construct the circuit designed from laboratory 4. Students need to
understand how to connect ICs on a digital experimenter. Students also
need to fully understand the concept of truth table, Boolean equation, and
logic gates to perform both experiments smoothly, since it will be used.

OBJECTIVES
1. To recast word problems into design specifications
2. To derive Boolean equation from a truth table.
3. To obtain minimized Boolean Expression using minimization
techniques.
4. To design and simulate circuits using software design tools
5. To build digital circuits in the lab using different type of TTL
components and interconnecting them
6. To learn techniques of troubleshooting
7. To verify functionality of the circuit by applying proper test
inputs.

PROCEDURE
LABORATORY 4
Part 1: Circuit Design
Firstly, we tabulated the truth table for the input A, B and C (Output of
encoder) and output D, F and L (Output of logic circuit).
Output of Encoder
A
0
0
0
0
1
1
1
1

Output of Logic Circuit

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

D
1
1
1
1
1
0
0
1

F
0
1
1
1
1
0
0
0

L
1
1
1
1
1
0
0
0

Then, we obtained the Boolean equations for each output D, F and L. By

using the K-Map method, we managed to obtain these equations.

A\BC

00
0
1

A\BC

01
1
1

00
0
1

L: A+BC

11
1
0

01
0
1

1
1

11
1
0

D: A+(B+C)

10
1
0

F: A+(B+C)

10
1
0

1
0
A\BC

00
0
1

01
1
1

11
1
0

10
1
0

1
0

After we obtained the Boolean equation, we design the circuit.

There are five logic gates used in the circuit. It consists of two NAND
gates, two XOR gates, and one OR gate.

Logic Gate
NAND
OR
XOR

IC part no.
7408
7432
7486

Part 2: Circuit Simulation

For the circuit simulation, we used the software provided in the lab
computer which is Quartus II for logic circuit design simulation and

ModelSim Altera for the timing simulation. Firstly, we inserted the

schematic design into the Quartus II software, compile it and simulate it to
check whether the circuit is functioning or not.

The schematic design works functionally well after we simulated it. Then
we opened ModelSim Altera and added the schematic design from
Quartus II which is the .vho file to compile and produce the timing
simulation for the design that we have done. The timing simulation has
been obtained and it matched with the truth table of the logic circuit.

LABORATORY 5
Part 3: Circuit Construction
To construct our circuit, we used the IDL800 digital experimenter provided
in the lab and a set of chips containing 74 series ICs that we received in
our first experiment. We put all the required ICs which are 7408, 7432 and
7486 on the digital experimenter and connect them together with jumper
cables according to the schematic design.

Input

8-bits Data

A
B
C

Switches Port
SW7
SW6
SW5

Output
D
F
L

8-bits LED
Displays Port
LED 2
LED 1
LED 0

The circuit constructed was tested and it worked functionally according to

the truth table and the simulation that we have done. The recorded
observation of the constructed circuit is shown on the Results section.

RESULTS
In Laboratory 4, we used the software Quartus II to design and compile the
circuit design that was obtained from the truth table. ModelSim Altera was
used to simulate the circuit and to obtain the result in the form of timing
diagram. Then we get an approval from our lab instructor to make sure
that its indeed correct. The figure below is the result that was obtained
from ModelSim Altera.

In Laboratory 5, we constructed the circuit from Laboratory 4 using TTL

components to verify its functionality. The circuit constructed was tested
to get the desired outputs from the truth table. Then, we demonstrated
the circuits functionality to our instructor. The outputs obtained from the
circuit are recorded in the table below.

SW7
OFF
OFF
OFF

SW6
OFF
OFF
ON

SW5
OFF
ON
OFF

LED2
ON
ON
ON

LED1
OFF
ON
ON

LED0
ON
ON
ON

OFF
ON
ON
ON
ON

ON
OFF
OFF
ON
ON

ON
OFF
ON
OFF
ON

ON
ON
OFF
OFF
ON

ON
ON
OFF
OFF
OFF

ON
ON
OFF
OFF
OFF

DISCUSSIONS
A logic gate is a switching circuit that is applied in computers and
other electronic devices. It is the basic building block used in computers
and many other digital devices. It performs logical operation in a digital
system. A digital system is where the input and the output only involve two
levels of voltage, logic 1 and logic 0. The logic gates are called gates
because they give a 1 on the output only when a particular combination
of 0 and 1 is present on the inputs. This combination is the key to open
the gate which is the output.
For this case, we designed the circuit such that it is automated and it
can control the door, light and the fan in an office. Even though there were

many circuit designs that can be implemented for this purpose, the ideal
number of gates to be used in this circuit is 5 gates. This requires less
work done and saves time. Usage of too many logic gates will result in
more work and increases the risk of getting faulty outputs. It also
complicates our circuit design. This experiment was done to prove that
logic gates can be combined to perfom specific tasks assigned by
humans. During the implementation of the circuit we have designed, we
had a problem with one of the chips due to some faults with the chips
pins. We managed to overcome the problems by using troubleshooting
techniques and we finally managed to get the correct output that matches
the output in the truth table. We used 2 NAND gates, 1 OR gate, and 2
XOR gates.

CONCLUSIONS
It can be concluded that we have successfully implemented our
circuit design that has been converted from word problems stated earlier.
We also managed to derive Boolean equations from a truth table and
minimized it using minimization techniques. We managed to get the
desired result in the form of timing diagram in ModelSim Altera and we

also successfully verify the circuit design by using TTL components and
get the desired outputs that matched the truth table. The ICs were tested
individually to check their functionality and they worked perfectly fine
after the circuits assembly. It was seen that the functionality of the circuit
was tested with a positive result.

DIGITAL LOGIC DESIGN LAB

(EEEB161)
LABORATORY REPORT
EXPERIMENTS 4 & 5
COMBINATIONAL LOGIC CIRCUIT

Ahmad Hafizuddin Bin Ismail

EP090995
Nurfarah Ain Binti Nahar
EP094401
INSTRUCTOR: Puan Yanti Erana Binti Jalil
Section 08

CONTENTS

1. INTRODUCTION
2. OBJECTIVES
3. PROCEDURE
4. RESULTS
5. DISCUSSIONS
6. CONCLUSIONS