FPGA-Based Implementation of Digital Control for a Magnetic Bearing

F. Krach, B. Frackelton, J. Carletta, and R. Veillette

Department of Electrical and Computer Engineering
The University of Akron

Abstract1
An FPGA-based digital controller is presented for a
magnetic bearing control application. A side-by-side
comparison of the FPGA- and DSP-based controllers
demonstrates the advantages of using an FPGA in terms of
design procedures, performance, and hardware utilization.
The FPGA-based controller runs two orders of magnitude
faster than the DSP-based controller does. The flexibility to
customize the bit-widths of the internal variables makes the
FPGA-based implementation more accurate than the DSPbased implementation, without increasing total register
space. The increased accuracy in the control computation is
especially important as fast sampling causes increased
computational sensitivity.

Introduction

Digital controllers are traditionally implemented using

digital signal processors (DSPs). The field programmable
gate array (FPGA) presents an alternative to the DSP for
digital control. FPGAs allow the use of customized bitwidths for the appropriate level of precision at each point in
the calculation. They also exploit hardware parallelism for
greater computational speed. These characteristics make
the FPGA ideal for high-bandwidth controls applications
such as magnetic bearings.
Previous work has reported FPGA-based implementations
of both digital filters and digital feedback controllers.
Although most work in digital filters does not cover the
implementation issues dealt with in this work, many of the
same issues, such as the flexibility that an FPGA affords
and finite bit-width effects with respect to fast sampling, are
addressed in [10].
Finite bit-width issues are also
recognized in [13] and [14]. The previous work in FPGAbased digital control presents some of the advantages
available with an FPGA-based control implementation,
including the concurrent mathematical operation [16] [17]
[15], the flexibility of a VHDL implementation [16] [17],
and the high-speed execution [15] [8]. The authors of [17]
point out the cost disadvantage of FPGAs with respect to
DSPs.

Although the FPGA is more expensive, it can operate at a

far greater sampling rate than the DSP can. It also allows
greater flexibility for choosing the precision of the internal
variables of the controller. The judicious use of nonuniform bit-widths allows the FPGA to operate with
sufficient precision at the higher sampling rate, without
wasting hardware. The results illustrate the FPGA-based
controllers superiority over the DSP.
The magnetic bearing application is introduced in Section
2. The analog control solution is covered in Section 3. The
experimental set-ups for the DSP- and FPGA-based
controllers are then given in Section 4. Section 5 reviews
the results based on experimental data. Finally, some
conclusions are drawn in Section 6.

The Magnetic Bearing

Magnetic bearings are well suited to applications requiring

high rotational speeds [7], and to those where lubrication is
problematical [1]. Of course, magnetic bearings require
feedback control as the open-loop system is unstable.
The magnetic bearing system used is an MBC 500 made by
Magnetic Moments, LLC. This system consists of a rotor
supported by two active radial magnetic bearings, and
includes the necessary position sensors, power amplifiers,
and controllers. Each bearing has two axes of control, with
separate control loops. The magnetic force along each axis
is generated by a pair of opposing horseshoe electromagnets
in a push-pull arrangement. The position of the shaft is
measured by means of a Hall-effect sensor along each axis.
The transfer function from the power-amplifier input
voltage to the sensor output voltage, including the actuator
and sensor gains, and the power-amplifier dynamics [11], is
P(s) =

(227.3) (106 )
.
( s + 4545)( s + 223.6)( s 223.6)

(Eq. 1)

The Analog Compensator

The magnetic bearing was controlled using the secondorder, continuous-time compensator
C (s) = ( K )

This work directly compares FPGA- and DSP-based control

implementations for a magnetic bearing application.

( s + 1.93 104 )( s + 1124)

( s + 3.223 105 )( s + 3226)

(Eq. 2)

This controller may not be the best one possible; however,

it does stabilize the magnetic bearing. In this study, it
serves as the target for digital approximation.
This material is based upon work supported by the National
Science Foundation under Grant No. 0113168.
0-7803-7896-2/03/$17.00 2003 IEEE

1080

Proceedings of the American Control Conference

Denver, Colorado June 4-6, 2003

The circuit in Figure 1 was used to test the closed-loop

response of the system to a disturbance input. A plot
showing the disturbance input as a step, along with the
outputs from the plant and the compensator, is shown in
Figure 2. The plots were obtained using a gain factor of
K 200 , which was chosen experimentally by finding the
narrow middle ground between an overly soft bearing (K
too low) and audible ringing (K too high). Figure 3 shows
the analog controllers experimental open-loop response to
a step input.
For the step input size chosen, the
input
disturbance
compensator
output

P(s)

plant
output

compensator output saturates near the 15-Volt supply

voltages during the brief transient following each step.
For digital implementations, discrete-time approximations
of this controller are determined and implemented on FPGA
and DSP platforms. The plots of Figures 2 and 3 provide a
basis for comparison to similar plots for the digital
controllers that are included in Section 5.

Experimental Set-up

The FPGA- and DSP-based implementations are discretized

versions of the continuous-time second-order compensator
given in Equation 2. The basic set-up is the same for both
implementations and can be seen in Figure 4.

C(s)
P(s)

Figure 1: Block diagram of input disturbance

experiment

Signal
Conditioning

Signal
Conditioning

DAC

C(z)

ADC

Figure 4: Block diagram of digital control system for the

magnetic bearing application

Figure 2: Closed-loop response of the analog

controller to a step disturbance

Both digital controllers were implemented on evaluation

boards. Each board had an analog-to-digital converter
(ADC) and a digital-to-analog converter (DAC), in addition
to the processing device used to implement C(z). An
analog interface signal conditioning circuit is required to
connect the magnetic bearing to the FPGA and DSP boards
due to a mismatch between the input and output spaces of
the magnetic bearing rig and the respective ADC and DAC.
Table 1 shows a comparison of parts for the FPGA and
DSP platforms with their respective part numbers.
Table 1: Components and part numbers for the
evaluation boards
DSP
Board

FPGA
Board

Figure 3: Open-loop step response of the analog

controller

1081

Device
Motorola part #
XC56F805FV80
Clock: 80 Mhz

Altera APEX part #

EP20K200EBC6521X
Clock: 40 MHz

ADC
Integrated in
the DSP
Conversion
time: 1.7 s
12-bit (10 bits
used)
THS5651AIPW
Conversion
time: 25 ns
10-bit

DAC
MAX5251B
Conversion
time: 200 ns
10-bit
AD9203ARU
Conversion
time: 25 ns
10-bit

Proceedings of the American Control Conference

Denver, Colorado June 4-6, 2003

Discretization was performed in MATLAB using both the

Tustin and matched transform methods. Tustin was the
preferred method; however, the matched transform was
used whenever Tustin resulted in a controller that suffered
from ringing. Both the FPGA- and DSP-based controllers
were implemented in a direct-form realization, which
implements the difference equation
y (k ) =

a u (k ) + b u (k 1) + c u (k 2)
d y (k 1) e y (k 2)

(Eq. 3)

where u(k) is the input to the controller, y(k) is the output of

the controller, and a through e are the constant coefficients.
This realization requires four registers: two for past values
of u(k) and two for past values of y(k).
At each iteration, the controller must read a sample of
position sensor data from the ADC, compute the
appropriate value of y(k) using Equation (3), and send the
result to the DAC to provide the current amplifier input.
The maximum sample rate is determined by how quickly
the hardware can achieve these three steps. The FPGA far
outperforms the DSP, not only because it computes more
quickly, but also because it tolerates more overlap between
operations from one iteration to the next.

4.1

DSP-Based Implementation

To obtain the maximum possible speed, the DSP was

programmed for fixed-point arithmetic. The difference
equation is implemented as a C-level instruction and
optimized by the Metrowerks Codewarrior [9] compiler.
Three interrupt service routines (ISRs) trigger all
operations. The first starts an analog-to-digital conversion.
The second reads the ADC result, computes y(k), and starts
the DAC. The third forwards the value of y(k) to the DAC
output. Since two ISRs cannot execute concurrently,
overlap of iterations is limited. The timing of the iterations
is shown in Figure 5. The thicker lines depict the actual
execution of instructions on the processor and the
downward pointing arrows indicate the interrupts. The
shortest possible sampling period was found to be 11 s.

4.2

Volts to the plant. However, the input space of the ADC

and the output space of DAC are 2 Volts peak-to-peak.
Conversion functions, implemented as simple binary point
shifts, are required because of the mismatch in the ranges of
the controller and the ADC and DAC. Overhead for the
code includes a counter to trigger events and phase-locked
loop code for the DAC clock.
The entire difference equation is computed using
combinational logic. Each multiplication operation has its
own hardware multiplier. The five resulting products are
computed in parallel and then summed. The ability to
parallelize the computations gives the FPGA a large speed
advantage over the DSP, which must do the multiplications
one at a time on a single multiplier. The output of the
controller is saturated at 8 Volts, which is the maximum
magnitude that the magnetic bearing plant can accept, and
then truncated to 10 bits, to match the input to the DAC.
The recursive feedback is truncated, but not saturated;
however, enough bits are used so that overflow does not
occur. Input and output are 10 bits and are registered at the
sampling frequency. Worst-case propagation delays were
calculated at 85 ns. After adding a safety margin, a
sampling time of 100 ns was chosen. The timing for the
FPGA system is shown in Figure 6. By comparing this
figure with Figure 5, it is evident that the FPGA allows
significantly more overlap from iteration to iteration than
the DSP.
Unlike the DSP, the FPGA allows customized bit-widths in
any point of a computation. Although this means that
careful attention must be paid to binary point placement, it
turns out to be a major advantage of FPGA-based
implementation. There is only one variable that has a fixed
precision: the sample obtained from the ADC, which is
fixed at 10 bits. Other than that, the precision in the
coefficients, the products, and the recursive terms is left up
to the designer.
Many bit-widths were experimented with to determine the
appropriate precision for each calculation. The intention
was to use only as many bits as necessary to obtain

FPGA-based implementation

Two versions of FPGA-based control were implemented.

One maximized the sampling frequency, and the other had
the same sampling frequency as the fixed-point DSP
version. Both FPGA-based designs were implemented with
VHDL using Alteras Quartus II version 1.1 development
tool [3]. There are three main components to the hardware:
conversion functions mapping the ADC to the controller
and the controller to the DAC, miscellaneous overhead, and
the controllers difference equation. The ADC and DAC
are hard-wired to run continuously, so no additional
VHDL-generated hardware is required for their control. All
numbers relevant to the control of the system are
represented as twos complement.
The controller is programmed to expect an output range of
16 Volts from the plant and to produce an input range of 8
1082

iteration i

ADC

Computation

iteration i+1

DAC
ADC

Computation

DAC

time

Figure 5: Timing for DSP-based implementation

iteration i

iteration i+1

ADC

Computation

ADC

DAC

Computation

DAC

time

Figure 6: Timing for FPGA-based implementation

Proceedings of the American Control Conference
Denver, Colorado June 4-6, 2003

acceptable controller performance. The representation of

the controller coefficients was considered first. The
resolution of the coefficients was chosen to ensure that the
poles and zeros of the compensator would be sufficiently
close to their nominal values. As sampling frequency
increases, the poles and zeros approach the unit circle, and
the effect of the truncation on the coefficients become more
critical. As a result, higher resolution coefficients are
required as sampling frequency increases.
The number of bits to feed back in the recursive terms of
the difference equation was considered next. The required
number of bits depends on the maximum range, and the
desired resolution of the variable y(k). The minimum
number of feedback bits needed to stabilize the system was
experimentally determined for each version of the
controller implemented. As with the coefficients, more
accuracy, in the form of larger bit-widths, is required as the
sampling time decreases.

Results

In terms of speed, the FPGA really shines. The FPGAbased implementation is two orders of magnitude faster
than the DSP-based implementation. For the second-order
magnetic bearing controller, the FPGA has a computation
time of 85 ns and a sampling period of 100 ns, while the
DSP has a computation time of 7 s and a sampling period
of 11 s. Both the 100-ns FPGA and the 11-s DSP
realizations are fully optimized. The difference in speed is
overwhelming, and should bring attention to the use of
FPGA-based controllers for applications where digital
control was previously impractical because of the short
sampling period required.
Figure 7 shows experimental plots of the open-loop step
response of the 11-s version of the DSP-based controller,
and the 11-s and 100-ns versions of the FPGA-based
controller. For each controller, the open-loop response
saturates at 8 Volts during the transient following each

step because the code was written to saturate the output of

the compensator at 8 Volts. The FPGA-based controllers
both have less noise than the DSP-based controller has.
This is because the DSP implementation requires the use of
16 bits throughout the computation, but the FPGA
implementation uses more resolution in the recursive terms,
where the computation is more sensitive to truncation
effects, and less for the coefficients, where the sensitivity is
not as great. Table 2 details the bit-widths used in the
different implementations. Fewer total bits are used in the
FPGA-based controller than in the DSP-based controller;
hence, the FPGA gives better performance (less noise),
using less register space (fewer total bits).
To compare the disturbance rejection properties of the
controllers, a step disturbance input was applied to the
closed-loop system using the set-up shown in Figure 1.
Results are shown in Figure 8 for the DSP-based 11-s,
FPGA-based 11-s, and FPGA-based 100-ns controllers.
Each plot shows the disturbance, the output from the plant,
and the output from the controller. As with the analog
controller, the gain of each digital controller was chosen by
experimental tuning. The FPGA-based controllers use a
gain factor of K 100 , and the DSP-based controller uses a
gain factor K 60 . The closed-loop response amplitudes
show that the FPGA-based controllers regulate the plant
output better than the DSP-based controller.
An additional disturbance rejection experiment tested how
large an impulse type disturbance the controller could
tolerate and still control the magnetic bearing. The MBC
500 system has a light that turns on to indicate that a
particular axis is floating; for this experiment, the criterion
for tolerating the disturbance is that the light is steadily
on. The results from this experiment can be seen in Table
3. The FPGA-based implementations tolerated larger
disturbances than the DSP-based implementation.
A cost comparison of the two platforms of digital controller
implementation involves only the cost of the hardware

Table 2: Bit-widths used in each implementation. The bit-width notation is (n, f), where there are n total bits and
the least significant bit is in the 2fs place
Quantity
100 ns
FPGA
11 s
FPGA
11 s
DSP

a
(28, -20)

Compensator Coefficients
b
c
d
(29, -20) (28, -20) (21, -20)

e
(22, -20)

Feedback
y(k-1)
(32, -18)

Feedback
y(k-2)
(32, -18)

Total
Bits
160

(14, -8)

(13, -6)

(14, -8)

(14, -18)

(13, -12)

(20, -10)

(20, -10)

108

(16, -10)

(16, -10)

(16, -11)

(16, -15)

(16, -15)

(16, -6)

(16, -6)

112

Table 3: Comparison of tolerance of impulse-type disturbance

Implementation
DSP 11 s
FPGA 11 s
Largest Amplitude Impulse Disturbance Tolerated
0.77 volts
1.75 volts

1083

FPGA 100 ns
1.84 volts

Proceedings of the American Control Conference

Denver, Colorado June 4-6, 2003

components. Table 4 breaks down the costs of the required

components. The price of the FPGA reported is not for the
FPGA used. The FPGA used was part of a development
board and much larger than what was required for this
design. Therefore, the price reported is for an Altera
EPF10K30EFC256-1 FPGA, which is large enough to
support the hardware design required for this work. Since
the DSP used has a built-in ADC, that component is not
listed in the table. As seen in the table, the FPGA is more
expensive than the DSP.
Table 4: Cost breakdown of required components in
U.S. dollars
FPGA
DSP

Processing
Device
122.00 [4]
21.93 [6]

ADC

DAC

17.21 [12]
N/A

10.81 [12]
13.94 [6]

Total
Cost
150.02
35.87

[1] Allaire, P.E., E.H. Maslen, R.R. Humphris, C.R. Knospe,

D.W. Lewis, Magnetic Bearings, CRC Handbook of
Lubrication and Tribology, Vol. III, 1994, pp. 577 600.
[2] Altera Corporation, APEX DSP Development Board
(Starter Version), Data Sheet, April 2002.
[3] Altera Corporation, www.altera.com.
[4] Arrow Electronics Inc., www.arrow.com.
[5] Bleuler, H., C. Gahler, R. Herzog, R. Larsonneur, T. Mizuno,
R. Siegwart, Application of Digital Signal Processors for
Industrial Magnetic Bearings, IEEE Trans. on Control
System Technology, Vol. 2, No. 4 December 1994, pp. 280
289.
[6] Digikey, www.digikey.com.

A hardware comparison is difficult to make because the

DSP hardware is fixed and the FPGA hardware is custom
generated. A brief comparison will be presented on a
hardware component level. Since ultra-high performance
was sought for the 100-ns FPGA-based controller, all of the
multiplies and adds are done in parallel. This amounts to
five 2-input multipliers and four 2-input adders. However,
this amount of parallelism is not really required; it was used
only to show the capabilities of an FPGA-based controller.
An FPGA-based controller could be scheduled to use one
multiplier and one adder. It would then have approximately
the same hardware components as the DSP, but would still
be more than an order of magnitude faster. An advantage
of the FPGA is the ability to make a trade-off between
hardware size (cost) and speed; high performance systems
utilize parallel hardware, requiring a larger FPGA, while if
cost is an issue, serial hardware can be made to fit on a
smaller, less expensive FPGA.

References

Conclusions

An FPGA-based digital controller was shown to have many

advantages over a DSP-based implementation in a direct
comparison of the controllers in a magnetic bearing test rig.
The FPGA offers a computation speed two orders of
magnitude faster than a DSP. In addition, the flexibility in
choosing bit-widths for proper resolution in various points
of the computation was stressed as a major advantage of the
FPGA-based controller. The results showed that this
flexibility in the resolution resulted in a controller that
contains less noise in its response, and has a higher
tolerance for noise, without using more register space than a
DSP-based controller. While the FPGA does cost more, the
benefits achieved out-weigh the cost disadvantage for this
application.

[7] Humphris, R.R., R.D. Kelm, D.W. Lewis, P.E. Allaire,

Effect of Control Algorithms on Magnetic Bearing
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[8] Jung, S.-L., M.-Y. Chang, J.-Y. Jyang, L.-C. Yeh, and Y.-Y.
Tzou, Design and Implementation of an FPGA-Based
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[9] Metrowerks Inc., Code Warrior C Compiler Reference, rev.
July 2000.
[10] Mishra, A., A.E. Hubbard, A Cochlear Filter Implemented
with a Field-Programmable Gate Array, IEEE Trans. on
Circuits and Systems II: Analog and Digital Signal
Processing, Vol. 49, Issue 1, Jan. 2002 pp. 54 60.
[11] Morse, N., R. Smith, B. Paden, MBC 500 Magnetic Bearing
System Operating Instructions, December 15, 1999.
[12] Newark Electronics, www.newark.com.
[13] Re, M., G.C. Cardarilli, A. Del Re, R. Lojacono, FPGA
Implementation of a Demux Based on a Multirate Filter
Bank, Proc. of the 2000 IEEE Intl. Symp. on Circuits and
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[14] Sasidaran, D., A. Azam, K.E. Nelson, M.A. Soderstrand,
FPGA Implementation of a Tunable Band-Pass Filter Using
the Basic Heterodyne Block, Proc. of the IEEE Intl. Conf.
on Acoustics, Speech, and Signal Processing, Vol. 2 , 2001
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[15] Tazi, K., E. Monmasson, J.P. Louis, Description of an
Entirely Reconfigurable Architecture Dedicated to the
Current Vector Control of a Set of AC Machines, Proc. of
the 25th Annual Conf. of the IEEE Industrial Electronics
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[16] Zumel, P., A. de Castro, O. Garcia, T. Riesgo, J. Uceda,
Concurrent and Simple Digital Controller of an AC/DC
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[17] Zumel, P., A. de Castro, O. Garcia, T. Riesgo, J. Uceda, A
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Vol. 2, 2001, pp. 943 948.

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Proceedings of the American Control Conference

Denver, Colorado June 4-6, 2003

(a) the DSP-based 11 s controller

(a) the DSP-based 11 s controller

(b) the FPGA-based 11 s controller

(b) the FPGA-based 11 s controller

(c) the FPGA-based 100 ns controller

Figure 7: Open-loop step responses of the digital
controllers

(c) the FPGA-based 100 ns controller

Figure 8: Closed-loop responses of the digital controllers
to a step disturbance

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Proceedings of the American Control Conference

Denver, Colorado June 4-6, 2003