Digital

g
Design
g Flow
Tips

Paine Chuang
13/Aug/2013
g

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis
A l i C
Coverage T
Tools
l
Incisive Comprehensive
p
Coverage
g ((ICC))
Incisive Metrics Center (IMC)

Low Power Design

Summary

Chip Planning Syystem

Incisive Enterp
prise Simulator
Incisive Enterprrise Verification
Encounter RT
TL Compiler

F
FrontEnd
d Design
n
FrontEnd
F
d Design

Iniitial Design
In
nitial Dessign

Digital IC Flow
Functional Specification
Initial Engineering specification
incl. Technology
Model specification

Test specification

Model - coding

Testbench - coding
Model Verification
f tests
RTL specific

RTL coding
RTL Verification

Encounter Digital Impleme

ent
Encounte
er Power System
m
Tem
mpus Timing

BackE
End Desiign
BackE
End Desig
gn

Synthesis / DFT
Floor planning

Timing Analysis

Place&Route
Completed Design Package
Project SignOff

Product History Leading to IES Base Sims

IES L
IES-L

05+

96-08 with
several
exceptions

IES XL
IES-XL

IUS and
d XLD

IDTS

NC-Sim

NC-SC

NC V il
NC-Verilog

NC VHDL
NC-VHDL

IEV XL
IEV-XL

S
Specman

VIP

Veristyd to
cdslmd
cds
d
Language-based
packages

Verification Cockpit
(EOL)
SystemC TB

05-10
92-98

Leapfrog
(EOL)

87+ Verilog-XL

First Native Compile

Verifault-XL

Earliest simulators

Specman

VIP
Verisity Products

IES Central to Advanced Verification

Multi-language simulation for low-power, metric-driven,
mixed-signal
mixed
signal verification
Coverage Analysis
Verification
Plan

Simvision Unified Debug System

SystemC
Verilog
VHDL
PSL

Tracking & Status

Session
Specification

SystemV

Failure Analysis

HAL/
eAnalyzer

Incisive Enterprise
Simulator
((Testbench, Assertions,
Simulation)

Incisive
Analog
Mixed
Signal

Incisive
System
Extension
HW/SW

Incisive
Formal
Verifier

VIP
uVCs
C

LSF or other Load Sharing Tool

Workstation Simulation Farm

Incisive Accelerator/Emulator

Coverage, Failure, & Debug Databases

IES Core Benefits

Incisive Enterprise Simulator is the engine at the heart
of digital, low-power, and mixed-signal verification.

High-performance execution generates critical data

need
d ffor Enterprise
E t
i Manager
M
enabling
bli b
both
th single-run
i l
and project level optimization speed convergence.
Comprehensive support for IEEE standard
verification languages enabling support across
systems low-power
mixed-signal
systems,
low power, and mixed
signal abstractions
abstractions.
Unique debug capabilities and support for common
power format and metric driven verification enable
continuous verification in the context of intent.

IES 12.x Update

Performance improvement
Performance issue in loading big snapshots
At times, Simulation loading time is a big part of the overall simulation time.
This happens mainly due to large sized snapshots residing over a remote disk.

Options to Improve Snapshot Loading Time

Use zlib option with NC binaries (ncvlog, ncvhdl, ncelab) to generate compressed data.
Added a new -libcache <localdirpath>
p
switch with ncsim.

Optimized usage of always blocks inside generates.

Always blocks inside the generate scope is becoming a common modeling style
Common always
y block optimizations
p
were disabled inside g
generate scope.
p
IES12.1 will improve these blocks.
30% improvement seen with this optimization on an important benchmark. Similar modeling style seen in many other
large customers.

Elaboration memory reduction by optimizing gate sharing for complex expressions.

expressions
Enhanced Gate Sharing Optimization for complex expressions.
Gate Sharing enabled for such gates with common complex code.
Reduces elaboration peak memory
y
12 % peak memory reduction seen on real case.
Reduces simulation memory

20% of simulation memory reduction seen on real case.

IES 12.x Update

New features
Random initialization of registers
Support for encryption of SDF files
Improved SDF annotation reporting mode directive in the source file.
Remove requirement that a create_isolation_rule -force command
must have either a -from or a -to option
New advanced profiler with instance and call graph support
Show LP isolation cells in schematic for SimVision
Additional SystemVerilog coverage support for IMC

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis
A l i C
Coverage T
Tools
l
Incisive Comprehensive
p
Coverage
g ((ICC))
Incisive Metrics Center (IMC)

Low Power Design

Summary

Incisive HDL Analysis and Lint

Identify and resolve problems early in the flow

Strong Rule-set
S
R l
Detailed Message for Easy Debug
R l C
Rule
Customization
t i ti
Extensive Language Support
Report Generation
Graphical User Interface for
Detailed Message Analysis
Schematic View for Structural
Checks
Graphical User Interface for Rule
Customization

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis
A l i C
Coverage T
Tools
l
Incisive Comprehensive
p
Coverage
g ((ICC))
Incisive Metrics Center (IMC)

Low Power Design

Summary

Incisive Simulator
Compile, elaborate, and simulate using the standard single-step flow

Single Step Execution

% irun [Sources] top [lib.]cell(.view) [Other_Switches]

How to Use irun to Work

Parses the command line
Invokes appropriate
compiler for each specified file
Invokes the elaborator (ncelab)
to elaborate the design and create
Invokes
I
k th
the simulator
i l t
(
(ncsim)
i )
to simulate the snapshot

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis Coverage Tools
Incisive Comprehensive Coverage (ICC)
Incisive Metrics Center (IMC)

Low Power Design

Summary

SimVision
Unified GUI for all verification engines

SimVision
Does it All!
HDL Waveforms
Signal/Transactions
Analog/Digital
Multi-Language
Debugging

Coverage Information
Assertion Browser

Schematic Tracing

Unique Capabilities of SimVision Architecture

Full Drag&Drop support
Interactive & Post Process
debug at the same time
Advanced SystemVerilog
y
g
Low-power Debug
The power of Tcl/Tk
Full SimVision command language
for scripting
Extensible GUI using SimVision
Plug-in capability

SimVision

Service
Manager

Control

Verification
Engine

SST2 db

SimVision
Common Window Schematic Tracer & Source Browser
Schematic Tracer

p y a
The Schematic Tracer displays
design as a schematic diagram
and lets you trace a signal through
th design.
the
d i

Source Browser

The Source Browser g

gives yyou
access to the design source code.

SimVision
Common Window Memory Viewer & Waveform
Memory Viewer

The Memory Viewer lets you

observe changes in the internal state
of memory locations. During
simulation, it also lets you set
breakpoints, and force and deposit
values to memory locations.
Waveform

The Waveform window plots

simulation data along an X and a Y
axis.
i D
Data
t iis usually
ll shown
h
as signal
i
l
values versus time, but it can be any
recorded data.

SimVision
Special Support for AMS & Low-Power
the SimVision
environment offers
when running
with the AMS
simulator.

Low Power Debug

g
Analog
Debug
g Mixed-Signal
g
g
SimVision lets you
y
view power domains
and power
conditions during
simulation.

SimVision
Toolbar introduction
Standard toolbar

SimVision window
Time toolbar

Simulation
toolbar
S
u at o too
ba

Trace toolbar

Display Value

Side toolbar

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis
A l i Coverage
C
Tools
T l
Incisive Comprehensive
p
Coverage
g ((ICC))
Incisive Metrics Center (IMC)

Low Power Design

Summary

Incisive Comprehensive Coverage (ICC)

Comprehensive instrumentation and
scoring
Single database for all coverage
Unified GUI to analyze coverage
High performance native code implementation

Provides comprehensive code coverage

Includes block, branch, expression, toggle, and
FSM
No additional instrumentation or compilation steps

Adds extensive functional coverage

g
Includes control, FSM, data, and transaction
Supported via PSL, SVA, covergroups, and
transaction recording

Total coverage solution with Enterprise

Manager
g
Uses coverage to track the overall verification
plan to closure

Incisive Metrics Center (IMC) Introduction

Easy-to-use and visually intuitive GUI minimizes learning curve
Unified
U ifi d metrics
i center ffor allll llanguages and
d allll coverage metrics
i types

Code (block / expression / toggle)

FSM
Functional (any language)
Assertions

New GUI to browse and analyze coverage

Instance and Type based views
Robust filtering and sorting capability
Intuitive page navigation

Unified
U
ifi d b
batch
t h mode
d C
Command
d Li
Line IInterface
t f
(CLI)
Comparable performance with ICCR and Specview
G d merge with
Good
ith b
basic
i rank
k & refinement
fi
t ((marking)
ki ) capabilities
biliti
Text based reporting

The New Incisive Metrics Center (IMC)

Productivity For Managing & Viewing Metrics

Code
Functional
Assertion

Unified Coverage in Incisive

Incisive Tools
ICCR

SpecView

Unified coverage visualization

Higher performance for larger design files
Easier to use and much more intuitive
Integrated
I t
t d assertion
ti coverage & checks
h k
Consistency for merging / ranking / marks, etc

Incisive Metrics Center Summary Page

List overall information to rapid debug
Unified
instance/type
verification
metrics tree

Page
Navigation

Information
Tabs

In context Table
filtering and sort

S
Search
h on a tree
t

Per coverage
type metrics tree

IMC FSM Coverage

Did I reach all of the states and cover all possible transitions or arcs?

New analysis
y
page shown in
navigation area

FSM bubble
diagram

Overview window

IMC Toggle Coverage

Provide information about the change of signals and ports

Local or recursive
grades and
covergroups

Detailed cover bin

metrics

Can filter here to

only
l display
di l
uncovered cross
bins

Bins of cross

Cross highlighted in
source
Cross selected

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis
A l i C
Coverage T
Tools
l
Incisive Comprehensive
p
Coverage
g ((ICC))
Incisive Metrics Center (IMC)

Low Power Design

Summary

Low Power Overview

Power treads
Pleakage
= cell leakage
l k
Summary of library cell leakage
Can be state-dependent
p

Powe
er Densitty (W/cm
m2)

1400
1200

Requires switching activity

1000

Pdynamic = Pinternal + Pwires

800
600

Pinternal = TR*(cell dynamic power)

400

Pwires = * CL * V2 * TR
CL: Capacitive loading (pin and net)

200
0

90nm 65nm 45nm 32nm 22nm 16nm

Driven
Di
b
by slew
l
and
d capacitance
i
Use the most accurate view of wires
available

V: Voltage
V
V lt
llevell
TR: Toggle rate
Default, annotated, or simulation

Low Power Overview

Common low power design techniques

Difficulty Design Flow Impact

Low Impact

PSO
~95% leakage
g

Powe
er Saviing

High
S i
Saving

Low
L
Saving

Popular
choice

Popular
choice

MVT
~60% leakage

Popular
choice

Clock Gating
~20% dynamic

High Impact
Adaptive Voltage/
Frequency Scaling
(AVFS)
40%-70% dynamic

DVFS
30%-60%
30%
60%
dynamic
Adaptive
MSV
Body Bias
~40% leakage
g and
~40% leakage
dynamic

Dual/Quad
Flops
5%-25%
dynamic
y

Pulse Latches
~20% dynamic

Services
Assistance
Available

Low Power Overview

Low power total solution
Formal
Analysis

Simulation

Hardware

Synthesis

Management

Power
Information
((CPF))

SVP

Equivalence
Checking

Place &
Route

Test

IP

Libraries

Common Power Format (CPF)

Common Power Format = Single specification of power intent used
throughout design, verification, and implementation
HDL Language neutral
ASCII File that captures:
Design intent
Power domain
Logical: hierarchical modules as
domain members
Physical: power/ground nets
and connectivity
Analysis view: timing, library
sets for power domains
Power Logic
Level Shifter Logic
Isolation Logic
g
State-Retention Logic
Switch Logic & Control Signals
Power Mode
Mode and Transitions

Technology information

Level shifter cells

Isolation cells

State-retention cells

Switch cells

Al a s on cells
Always-on

CPF Instruction
Minimal command set for different design stages
create_power_domain
create_nominal_condition
create_power_mode
create_state_retention_rule
create_isolation_rule
create_level_shifter_rule

S
Specify
if power intents
i t t
verification and simulation
design exploration
early power estimation

define_library_set
update nominal condition
update_nominal_condition
update_power_mode

More implementation details

synthesis
y
formal verification
DFT, ATPG
gate level power estimation

create_ground_nets
create_power_nets
update_power_domain
create_power_switch_rule
create_analysis_view
create_operating_corner
t
ti

Complete physical implementation details

silicon virtual prototyping
power planning
physical synthesis
structural verification
sign-off power analysis

CPF Verification
Shut-off function verification
create_power_domain -name PDD -default
create_power_domain -name PD1 -instances uL1 -shutoff_condition uPMU/pso
create_isolation_rule -name ISO_PD1 -from PD1
-isolation_output low -isolation_condition !uPMU/isoen
create_nominal_condition -name ON12 -voltage 1.2
create_power_mode -name PM1 -domain_conditions {PDD@ON12 PD1@ON12} -default
create_power_mode -name PM2 -domain_conditions {PDD@ON12}
CPF

(PDD)
pso

uPMU

pso

RTL

uL1 (PD1)

isoen

(PDD)

IES

uPMU

isoen

uL1 (PD1)

Agenda
Incisive Platform Overview
Incisive HDL Analysis and Lint
Incisive Simulator
Debug by SimVision
Analysis
A l i C
Coverage T
Tools
l
Incisive Comprehensive
p
Coverage
g ((ICC))
Incisive Metrics Center (IMC)

Low Power Design

Summary

Summary
IES: Heterogeneous single-kernel architecture
IES: Comprehensive standards support
IES:
IES HDL and
d testbench
t tb
h analysis
l i
IES: Unified SimVision debug environment
IMC:
C Total
ota co
coverage
e age analysis
a a ys s
CPF: Native low-power analysis