3rd International Conference on Computing, Communication and Sensor Network, CCSN2014

Dynamic Self Controllable Surfing for Differential On-Chip

Wave-Pipelined Serial Interconnect: A sample Template of CCSN2014
Bhaskar. M, Srinivas Gantasala, Venkataramani. B
Department of Electronics and Communication Engineering
National Institute of Technology, Tiruchirappalli 620015, INDIA
bhaskar@nitt.edu, srighantasala123@gmail.com,bvenki@nitt.edu

ABSTRACT
Papers for CCSN2014 should be of type: research paper,
survey paper, tutorial paper or published paper taking
permission from previous authority for reprinting. This
word document will be considered as standard template of
paper preparation in all respects like header, paragraphheader, fonts, space, two-columns, caption of figure,
reference etc. Paper page limit is maximum six pages of
A4 size paper. The Title of the paper should be of 14
points, authors names are of 11 points, affiliations and
other body points should be of 10 points of Times New
Roman font. It is a sample text of a paper that got 1 st
award in one of our conference Micro2014 which was
held in Hyatt Regency, a 5 Star Hotel, in Kolkata, India
during 11th to 13th of July 2014. Here, texts of that paper is
deleted/distorted as it is waiting to be published in a
Springer Journal. Authors should follow all other points
mentioned in this papers as caption of figure(9pts),
caption of Tables(8pts capital letter), equations numbering
should be right aligned as fonts mentioned here. No page
numbers should be inserted. Header should contain the
conference name as mentioned in this document.
References should be inserted as [3][4].
Keywords: Controllable inverter pair, Differential
interconnect, Method of logical effort, Repeater insertion,
Self controllable, Serial link, Surfing, Wave-pipelining
I.

Introduction

xxxAs the CMOS technology scales down, transistor

sizes get reduced and this in turn increases the speed of
the logic blocks [1]. However, interconnects used for
routing signals between logic blocksxxx.
xxxThe method of logical effort is proposed in [16] in
order to design a CMOS circuit such that it operates at a
particular frequency consuming the least area and power.
In this paper, the proposed circuits are designed using the
method of logical effortxxx.
XxxThe paper is organized as follows: Section II, III
describe the design of differential wave-pipelined serial
interconnect with surfing using UR and NUR
respectively. Section V provides the post layout
simulation results and the observations. The concluding
remarks are given in Section VIxxx.
II. Drawing figures
All figures should be in black and white color. Our
proceeding book is printed in B/W color. Some Color

figures become non visible after printing in B/W.

Drawing figures, the common problems are: placing all
components inside a same figure, putting text inside the
boxes, giving arrow symbol, making label text inside. To
solve these problems, it is suggested to draw figure within
a canvas drawing area(in word-it is available
insert>shapes>new drawing canvas). In different versions
of word it may be found in different menu-submenu. But
drawing must be within a fixed boundary that if texts of
the paper is deleted or edited, components of figures may
remain in same positions. MSWord version is required for
the printing press where reediting(in some cases) become
easier for press people. They need MSWord version of the
paper.
Figures caption should be as mention in this document.
All texts mentioned within figure should be readable. No
color fonts should be used for proceeding book but after
conference if the paper is selected for Journal publication,
then paper should be reformatted according to the authors
guide line of that particular journal. In digital journal,
number of pages may be more and color figures can give
better outlook. As color printing cost is more, we avoid
color figures for proceeding printed book. But, sometime,
for reference color photo may be required to use but we
shall print it in B/W color.
Another way of converting your figure to a picture is that:
press print Screen button from keyboard and then insert
in a place of document, then paste the thing pressing
ctrl+v, then double click on the figure, press crop, cut
unnecessary portion of figure and making a picture with
all of its components is done and there are no chance to
be displaced of components of figure.

3rd International Conference on Computing, Communication and Sensor Network, CCSN2014

Fig. 1. Schematic diagram of differential wave-pipelined serial

interconnect with surfing and UR.

True

True
out
Comp
out
Comp
RX

Dynamic self Controllable Inverter Pair

Comp

True

Fa

Fas

Fig. 2. Schematic diagram of wave-pipelined segment.

3

TOUT

M1
CIN

TOUT

M2

(a)
a)

Surfing signal

3
M3 COUT
TIN

M5

3
M7
TOUT

1
M4

COUT

1
M6

COUT

1
M8

(b)

Fig. 3. Dynamic Self Controllable inverter pair

Surfing circuit for complement path b) Surfing circuit
for true data path.

3rd International Conference on Computing, Communication and Sensor Network, CCSN2014

A. Margin: top, bottom and columns

All margins should be like this paper template. It is found
in Page Layout>Margin>custom margin (it may be in
other menu of other version, this document is prepared
under windows vista). For our paper, margins are like:
Top=2.49cm, bottom=2.01, orientation=portrait, two
column, paper size= A4(21x29.7cm), width=21cm,
height=29.7cm. header= 1.52cm, footer=1.02cm. Left and
right margins =2.0cm. Other issues not mentioned should
be as applied within this paper.True
B. Line spacing, Indent

TX

The designs of differential wave-pipelined surfing

interconnect with UR and NUR is carried out for 40mm
metal 4 interconnect in UMC 180nm technology. The post
layout simulations are carried out using Cadence Virtuoso
tool.
NUR in [15] and the proposed self controllable surfing for
differential wave-pipelined serial interconnect for UR and
NUR are given in Table IV.
TABLE III
DELAY AND POWER OF THE INTERCONNECT WITH NUR
FOR DIFFERENT INTERCONNECT RATIO

Ratio of
interconnect
segments (r)

Line spacing will be one, space before paragraph and

after paragraph should be as Comp
used in this documents. Do
not use condensed spacing or more than single line
spacing. No indenting at beginning of the paragraph.

Delay of the
longest
segment in
NUR(ps)

C. Equations

In
[15]

This
paper

In
[15]

This
paper

1.5
5
2.7
3

2.60

All equations should be in 10 pts. Right aligned, clearly

mentioning subscript, superscript, power, symbols etc.
using especial fonts is a problem in equations printing. In
this document Cambria Math font of 10pts is used.
Spacing and position of power symbols, subscript etc can
be adjusted through equation editor.

2.00

643.0

384.6

3.00

366.0

340.0

The absolute delay (D) of a circuit consisting of N stages

is given by [16]

VI. CONCLUSION

D = (N F1/N + P)

(2)

where,
F - path effort
P - parasitic delay of the path (sum of parasitic delay of
each stage)
- technology constant (12ps for 180nm)

T p =0.69 R b Cb 0ntt
+ 0.69

2
N-1
R b Cw
ar a r
ar
a+ + 2 ++ N-1
L
f f
f

R C
+ 0.69 w b [ a+arf+a r 2 f 2 ++a r N-1 f N-1 ]
L
+ 0.38

R w Cw
L

2.94

xxxIn this paper, dynamic self controllable inverter pair is

proposed for surfing the differential wave pipe-lined
serial interconnect. The design of the transceiver with self
controllable surfing scheme for uniform repeater and non
uniform repeater insertion is carried out using the method
of logical effort and their performances are compared.
The proposed surfing interconnects with UR and NUR
have higher data transfer rates and allow higher input
jitter. The proposed schemes can be used for higher data
transfer rates through differential on-chip global
interconnectxxx.
R b N-1

Rb
.f Cb ++ N-1 . f Cb
f References
fshould contain: authors names, title of the
book, paper, pub name, year, vol. issue numbers. Text size
of references should be of 9pts.
References
[1]

International Technology Roadmap for Semiconductors,

(2001). Semiconductor Industry Association, 2001,
Interconnects section, p. 4

[2]

R.Ho, K.W.Mai, and M.A.Horowitz, The future of

wires, Proc. IEEE, vol. 89, no 4, 2001, pp. 490-504.

[ a 2 +a 2 r 2 + a 2 r4 ++ a2 r 2(N-1)
]
[3]

(5)
[4]

V RESULTS

Max.
operating
frequency in
Gb/s

H.B.
Bakoglu,
and J.D.
Meindl,
Optimal
interconnection circuits for VLSI, IEEE Trans. Electron
Devices ED-32 (5), 1985, pp. 903909.
C.J. Alpert, A. Devgan, J.P. Fishburn, and S.T. Quay,
Interconnect synthesis without wire tapering, IEEE
Trans. Computer-Aided Design Integrated Circuits and
Systems 20 (1), 2001, pp. 90104.