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Alex Ruderman
Jan Melkebeek
VDC
S3
VDC
2
S2
S1
C2
C1
C1
S1
VDC
2
VDC
2
S2
C2
C2
C1
(b) Interval 3
VDC
2
VDC
2
(c) Interval 2
VC
c1
c2
c3
VDC
2
(a) Interval 1
S3
VDC
(1)
(d) Interval 4
VDC
2
VDC
6
4
t
Fig. 2. Voltage modulation strategy for a 4-level flying capacitor converter for 1/3 < D < 1.
instantaneous voltage command VC is compared with triangular waves, one for each complementary switch pair. When
the voltage command is higher then carrier wave ci , Si is
switched on and Si is switched off, for i = 1, 2, 3.
This PWM voltage modulation strategy creates a switch
sequence that determines the output voltage. This output
(2)
The state space matrix A and vector B are obtained by solving linear time invariant differential equations on individual
(4)
with T1 = RC1 .
For interval 2 (Fig. 3(c)), with both capacitors connected:
t
+ C1
C exp
6 2
T2
6
6
C1 + C2
6
A2 = 6
6
6 C1 exp t
+ C1
4
T
2
3
t
C2 exp
+ C2
7
T2
7
7
C1 + C2
7
7,
7
t
C1 exp
+ C2 7
5
T
(5)
(6)
(13)
(1 D)
Tpwm . Combining (11)-(13)
2
V1 =
(7)
(8)
(9)
(14)
;
,
dt
Tpwm dt
Tpwm
with T3 = RC2 .
VDC
,
X (Tpwm ) = AX (0) + B
2
A = A3 A2 A1 ,
B = A3 (A2 B1 + B2 ) + B3 .
(12)
0
B3 =
,
1 exp (t/T3 )
V2 (0) t
; V1 = 0,
RC2
V2 =
C1 + C2
C1 + C2
3
2
t
C2 1 exp
7
6
T2
7
6
7
6
C1 + C2
7
6
B2 = 6
7,
7
6
t
7
6 C1 1 exp
5
4
T2
C1 + C2
C1 C2
R.
with T2 =
C1 + C2
change on a single PWM period. This small-parameter assumption does not include the load time constant, because the
absence of inductance.
Suppose VDC = 0 and pre charged capacitors at their normal
voltage. This results in free capacitor discharge (homogenous
system). Assumption (10) leads to following equations for
interval 1:
V1 (0) t
; V2 = 0,
(11)
V1 =
RC1
for interval 2:
(15)
exp
; (17)
2
TD
2VDC
V1 (0) + V 2(0) VDC
t
+
exp
3
2
TC
V2 (0) V1 (0) VDC /3
t
exp
, (18)
2
TD
V2 (t) =
VDC
2
(19)
S4
S1
S3
R
C1
c2
C2
VDC
2
c1
S2
S1
S3
S2
S4
c3
Fig. 5. A 3-level H-bridge flying capacitor multilevel converter circuit topology.
VCOM
c13
c24
VC
VL
VDC
2
VDC
6
-VC
VDC
6
VL
VDC
2
Fig. 4. Voltage modulation strategy for 4-level flying capacitor converter for 0 < D < 1/3.
(1/3 + D)
Tpwm ;
2
(20)
(1/3 D)
t5 = t6 = t7 =
Tpwm .
2
Although conduction paths differ, the instantaneous equivalent circuit topology for switch intervals 5, 6 and 7 are the
same as in 3, 1 and 2, respectively. This means the effect on
the capacitor voltage is the same in the corresponding switch
intervals.
Combining the switch interval durations for the same capacitor voltage effect results in:
t1 = t2 = t3 =
Tpwm
. (21)
3
This proves that for 0 < D < 1/3 voltage balance dynamics
do not depend on D and are identical to that for D = 1/3.
t1 + t6 = t2 + t7 = t3 + t5 =
1234
1234
1234
1234
1234
1234
1234
1234
1234
(22)
Just like in the 4-level case, for every switch interval a linear time invariant system can be deduced with state equations
(2). As the instantaneous topologies are similar to those of
the 4-level case, the same matrices Aj and Bj for corresponding switch intervals can be chosen. For switch intervals 1 and
5, there is no voltage supply in the topology, so Bj is a zero
vector in this case.
A similar homogeneous system as for the 4-level converter
can be calculated and with assumption (10) a similar approximation can be made. This results in similar equations as (11)-
R
C2
(b) Interval 5
VDC
2
VDC
+
2
C1
(a) Interval 1
C1
V2 (t) =
(c) Interval 3
V1 (0) + V 2(0) VDC
t
exp
2
TC
V2 (0) V1 (0)
t
exp
, (26)
2
TD
R
VDC
2
RC
,
1D
RC
TC =
.
D
TD =
C1
(d) Interval 7
(27)
C2
R
C1
C2
T1 =
(a) Interval 2
(28)
(b) Interval 6
5. SIMULATIONS
VDC
2
(c) Interval 4 and 8
RC1
RC2
; T2 =
1D
1D
VDC
+
2
Model
50
40
30
VC1
(24)
For equal capacitances C1 = C2 = C, an averaged voltage balance dynamics solution for non zero supply voltage is
given by following equations:
V1 (t) =
Real voltage
VC2
60
V (V)
1 2D
1/C
1
1
V1
V 1
C1
=
1 2D
V .
V 2
2R
2
1/C2
C2
70
V1 (0) + V 2(0) VDC
t
exp
2
TC
V2 (0) V1 (0)
t
exp
; (25)
2
TD
20
10
0
0
0.002
0.004
0.006
0.008
0.01
time (s)
VC1
VC2
50
45
40
7. ACKNOWLEDGMENT
30
VC (V)
35
25
20
15
10
5
0
0
0.002
0.004
0.006
0.008
0.01
8. REFERENCES
time (s)
100
90
80
VC (V)
60
Model
40
Real voltage
30
20
VC2
10
0
0
[2] S.S. Fazel, S. Bernet, D. Krug, and K. Jalili Design and Comparison of 4-kV Neutral-Point-Clamped, Flying-Capacitor, and
Series-Connected H-Bridge Multilevel Converters, IEEE
Trans. on Industrial Applications, vol. 43, no. 4, pp. 10321040, Jul./Aug. 2007.
[3] B.P. McGrath and D.G. Holmes, Analytical Modelling of
Voltage Balance Dynamics for a Flying Capacitor Multilevel
Converter, Proc. IEEE APEC07, Orlando, Florida, USA, pp.
543-550.
VC1
70
50
[1] J.-S. Lai and F.Z. Peng, Multilevel Converters - A New Breed
of Power Converters, IEEE Trans. on Industry Applications,
vol 32, no. 3, pp. 509-517, May/June 1996.
3
time (s)
5
3
x 10
6. CONCLUSIONS
A time domain approach to construct a family of flying capacitor converter dynamics models by stitching of analytical
solutions for consecutive switching intervals is presented.
[6] R.H. Wilkinson, T.A. Meynard, and H. du Toit Mouton, Natural Balance of Multicell Converters: The Two-Cell Case,
IEEE Trans. on Power Electronics, vol. 21, no. 6, pp. 16491657, Nov. 2006.
[7] D.G. Holmes and T.A. Lipo, Pulse Width Modulation for
Power Converters: Principles and Practice, IEEE Press, Piscataway, NJ, 2003.
[8] A. Ruderman, B. Reznikov, and M. Margaliot, Simple Analysis of a Flying Capacitor Converter Voltage Balance Dynamics
for DC Modulation Proc. EPE/PEMC 2008, Aachen, Germany, pp. 260-267.