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J SUFFIX
LOGIC DIAGRAM (Each Flip-Flop) CERAMIC
CASE 632-08
14
1
SET (SD)
4 (10)
Q
5 (9)
CLEAR (CD)
1 (13) N SUFFIX
PLASTIC
CLOCK 14 CASE 646-06
3 (11)
Q 1
6 (8)
D
2 (12)
D SUFFIX
SOIC
14
1 CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ Ceramic
MODE SELECT — TRUTH TABLE SN74LSXXN Plastic
SN74LSXXD SOIC
INPUTS OUTPUTS
OPERATING MODE
SD SD D Q Q
Set L H X H L
LOGIC SYMBOL
Reset (Clear) H L X L H
*Undetermined L L X H H 4 10
Load “1” (Set) H H h H L
Load “0” (Reset) H H l L H
2 D SD Q 5 12 D SD Q 9
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then 3 11
CP CP
we cannot guarantee to meet the minimum level for VOH.
H, h = HIGH Voltage Level 6 8
L, I = LOW Voltage Level
CD Q CD Q
X = Don’t Care
i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time 1 13
i, h (q) = prior to the HIGH to LOW clock transition.
VCC = PIN 14
GND = PIN 7
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
AC WAVEFORMS
D* 1.3 V 1.3 V
th(H)
th(L)
ts(L) tW(H) ts(H)
tW(L)
1.3 V 1.3 V
CP
1
fMAX
tPHL tPLH
Q
1.3 V 1.3 V
tPHL
tPLH
1.3 V 1.3 V
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
tW
SET
1.3 V 1.3 V
tW
CLEAR
1.3 V 1.3 V
tPLH tPHL
1.3 V 1.3 V
Q
tPHL tPLH
Q
1.3 V 1.3 V