EE1022 Electronic Engineering

S9: Semiconductor Device Fabrication

By: Dr. S. Thayaparan

ELX304 Electronic Systems Design, Lecture Notes, University of Sunderland, UK

Slide contents are extracted from the following source of origin :

1.

Diode Principles and Applications

Bipolar Junction Transistor
Field Effect Transistors
Operational Amplifiers
Gates and Logic Design
Combinational Logic Design
Sequential Logic Design
Programmable Logic Devices
Semiconductor Device Fabrication

Course Outline
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9. Semiconductor Design Fabrication

9.1 VLSI Realization Process

9.2 Integrated Circuits (IC)

9.2.1 Decapsulated IC

9.2.2 Wafers

9.2.3 Feature Size

9.3 CMOS Technology

9.3.1 CMOS Inverter

9.3.2 WORKED EXAMPLE

Show how a 2input NAND gate it may be programmed
onto a single logic design cell.

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9.4 Layout

9.5 Active Layer Design Rules

The deposit/etch spreads as it

goes deeper
Design rules must take this
into account
Any connections have to be
made by allowing sufficient
overlap

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9.5.1 Design Rules for Mask 1-3 (P-well, Active and Poly Layers)

CMOS DESIGN RULES (PWELL PROCESS)

9.6 Design Rules for Contacts

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9.6.1 Design Rules for Mask 4-5

9.6.2 Design Rules for Mask 6-8

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9.6.3 Design Rules for Mask 9

Production process naturally generates current (charge) carrying mediums

separated by insulating layers
It forms a capacitance
Unwanted capacitors are termed parasitic
Typical MOS manufacture Area Capacitances (for various feature sizes)

9.6.4 PARASITIC CAPACITANCE

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9.6.4 PARASITIC CAPACITANCE

Note: FemtoFarad (fF) is equivalent to 10 -15 F

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The physical number of dies, Nd , that can be manufactured onto a silicon

wafer of radius R can simply be evaluated via the wafer/die area ratio as
follows:

9.6.5 Packing Density

Boundary losses occur when fitting square or rectangular dies into a circular
wafer
Following approximation can be used:

9.6.6 Worked Example

How many dies of area 500 by 800mm can be manufactured upon a 5cm
diameter wafer?

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9.7 VLSI FABRICATION METHODS

Fabrication of all monolithic integrated circuits (formed within a

semiconductor substrate), within a wafer requires the following
general production stages:

9.7.1 Wafer Preparation

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Base substrate material (Silicon) has as many impurities removed as possible

to improve resulting semiconductor performance

9.7.2 Doping

i)

Etch insulation stage using a photoresist material

Insulation stage by producing the thermal oxide SiO2 by heating the silicon
substrate to temperatures of between 850 and 1100C in the presence of
oxygen ( Si + O2 SiO2 )

Introduce doping impurities to create local regions of n and p semiconductor

material within the substrate material

ii)

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9.7.2 Doping
iii)
iv)

Photoresist Removal and Cleaning

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Photolithography where the above layers are removed using an acidic etch in
those areas exposed to uv light via a photographic negative
Ion implantation where the type of material is formed by accelerating the
appropriate type of impurities into the exposed substrate using a Cathode Ray
Oscilloscope type procedure. The doping levels are controlled by ion
concentration levels, energy imparted onto the ions and exposure time. It
should be noted that difraction patterns, due to random particle collisions,
ensure that the greater the depth, the greater the width of the ion implant.

9.7.3 Insulation
Again SiO2 is used to insulate between
layers
Greater thicknesses needed along with
the distance from the silicon wafers
surface
A deposition procedure is required

Actually polycrystalline silicon

By overdoping silicon onto the SiO2 surface, via deposition, forms silicon crystallines
within the structure
Forcing the silicon atoms apart which in turn destroys the usual pn junction properties
Causes the material to act as a high-resistance conductor within the semiconductor

9.7.4 Poly-Silicon

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Relatively low temperature operation which uses the photolithographic

approach as defined above to reveal the appropriate areas for metal
deposition via a vacuum techniques
Aluminium is generally used as it is easy to deposit, forms good low
resistance contacts with silicon, is easy to etch and connect to
Often a two layer metal procedure is employed

9.7.5 Metallisation

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