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Course Outline

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“ELX304 Electronic Systems Design”, Lecture Notes, University of Sunderland, UK

EE1022 – Electronic Engineering

Diode Principles and Applications Bipolar Junction Transistor Field Effect Transistors Operational Amplifiers Gates and Logic Design Combinational Logic Design Sequential Logic Design Programmable Logic Devices Semiconductor Device Fabrication

S9: Semiconductor Device Fabrication

By: Dr. S. Thayaparan

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9.2

9. Semiconductor Design Fabrication

Integrated Circuits (IC)

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9.2 9. Semiconductor Design Fabrication Integrated Circuits (IC) 4 3 9.1 VLSI Realization Process
9.2 9. Semiconductor Design Fabrication Integrated Circuits (IC) 4 3 9.1 VLSI Realization Process
9.1 VLSI Realization Process
9.1
VLSI Realization Process

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9.2.2 Wafers
9.2.2 Wafers
9.2.1 Decapsulated IC
9.2.1 Decapsulated IC

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9.3 CMOS Technology 8
9.3 CMOS Technology
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9.2.3 Feature Size
9.2.3
Feature Size

Show how a 2input NAND gate it may be programmed

9.3.2

WORKED EXAMPLE

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onto a single logic design cell.
onto a single logic design cell.
a 2input NAND gate it may be programmed 9.3.2 WORKED EXAMPLE 10 9 onto a single
9.3.1 CMOS Inverter
9.3.1
CMOS Inverter



The deposit/etch spreads as it goes deeper Design rules must take this into account

Any connections have to be made by allowing sufficient overlap

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account Any connections have to be made by allowing sufficient overlap 11 12 9.5 Active Layer
account Any connections have to be made by allowing sufficient overlap 11 12 9.5 Active Layer
9.5 Active Layer Design Rules
9.5
Active Layer Design Rules
account Any connections have to be made by allowing sufficient overlap 11 12 9.5 Active Layer
account Any connections have to be made by allowing sufficient overlap 11 12 9.5 Active Layer
9.4 Layout
9.4
Layout

9.5.1 Design Rules for Mask 1-3 (P-well, Active and Poly Layers)

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Rules for Mask 1-3 (P-well, Active and Poly Layers) 14 13 9.6 Design Rules for Contacts
Rules for Mask 1-3 (P-well, Active and Poly Layers) 14 13 9.6 Design Rules for Contacts
9.6 Design Rules for Contacts
9.6
Design Rules for Contacts
Rules for Mask 1-3 (P-well, Active and Poly Layers) 14 13 9.6 Design Rules for Contacts
CMOS DESIGN RULES (PWELL PROCESS)
CMOS DESIGN RULES (PWELL PROCESS)

9.6.1

9.6.2

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Design Rules for Mask 6-8
Design Rules for Mask 6-8
Design Rules for Mask 4-5
Design Rules for Mask 4-5

9.6.4

Production process naturally generates current (charge) carrying mediums separated by insulating layers It forms a capacitance Unwanted capacitors are termed parasitic Typical MOS manufacture Area Capacitances (for various feature sizes)

PARASITIC CAPACITANCE

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MOS manufacture Area Capacitances (for various feature sizes) PARASITIC CAPACITANCE 17 18 9.6.3 Design Rules for
9.6.3 Design Rules for Mask 9
9.6.3
Design Rules for Mask 9

9.6.6

9.6.5


How many dies of area 500 by 800mm can be manufactured upon a 5cm diameter wafer?

The physical number of dies, N d , that can be manufactured onto a silicon wafer of radius R can simply be evaluated via the wafer/die area ratio as follows:

Boundary losses occur when fitting square or rectangular dies into a circular wafer Following approximation can be used:

Worked Example

Packing Density

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can be used: Worked Example Packing Density 20 19 9.6.4 PARASITIC CAPACITANCE Note: FemtoFarad (fF) is
can be used: Worked Example Packing Density 20 19 9.6.4 PARASITIC CAPACITANCE Note: FemtoFarad (fF) is
can be used: Worked Example Packing Density 20 19 9.6.4 PARASITIC CAPACITANCE Note: FemtoFarad (fF) is
9.6.4 PARASITIC CAPACITANCE Note: FemtoFarad (fF) is equivalent to 10 -15 F
9.6.4
PARASITIC CAPACITANCE
Note:
FemtoFarad (fF) is equivalent to 10 -15 F

9.7

9.7.2

9.7.1

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Introduce doping impurities to create local regions of n and p semiconductor material within the substrate material

Base substrate material (Silicon) has as many impurities removed as possible to improve resulting semiconductor performance

semiconductor substrate), within a wafer requires the following general production stages:

Fabrication of all monolithic integrated circuits (formed within a

Insulation stage by producing the thermal oxide SiO 2 by heating the silicon substrate to temperatures of between 850 and 1100C in the presence of oxygen ( Si + O 2 → SiO 2 )

VLSI FABRICATION METHODS

Wafer Preparation

Doping

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Etch insulation stage using a photoresist material
Etch insulation stage using a photoresist material

9.7.3

9.7.2

iii)
iv)

9.7.4


Again SiO2 is used to insulate between layers Greater thicknesses needed along with the distance from the silicon wafers surface A deposition procedure is required

Actually polycrystalline silicon

By overdoping silicon onto the SiO2 surface, via deposition, forms silicon crystallines within the structure

Causes the material to act as a high-resistance conductor within the semiconductor
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Forcing the silicon atoms apart which in turn destroys the usual pn junction properties

Photolithography where the above layers are removed using an acidic etch in those areas exposed to uv light via a photographic ‘negative’ Ion implantation where the type of material is formed by accelerating the appropriate type of impurities into the exposed substrate using a Cathode Ray Oscilloscope type procedure. The doping levels are controlled by ion concentration levels, energy imparted onto the ions and exposure time. It should be noted that difraction patterns, due to random particle collisions, ensure that the greater the depth, the greater the width of the ion implant.

Insulation

Doping

Poly-Silicon

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the depth, the greater the width of the ion implant. Insulation Doping Poly-Silicon 2 3 Photoresist
Photoresist Removal and Cleaning
Photoresist Removal and Cleaning

9.7.5


Relatively low temperature operation which uses the photolithographic approach as defined above to reveal the appropriate areas for metal deposition via a vacuum techniques Aluminium is generally used as it is easy to deposit, forms good low resistance contacts with silicon, is easy to etch and connect to Often a two layer metal procedure is employed

Metallisation

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contacts with silicon, is easy to etch and connect to Often a two layer metal procedure