Integrating Design IP and Verification IP

To Ensure Quality and Predictability

Prakash Rashinkar
Director of Engineering

Rambus, Inc.

Outline

IP Challenges
PCIe Solution
Value Proposition
Verification IPs
Interoperability
Summary

2007 Rambus
For Presentation purposes only

Slide 2

IP Challenges
I had to
convince the
vendor the bug
was in their IP

I had to spend
time chasing down
IP bugs
Integration
Quality
Verification

My project was
delayed because I
had to verify the
vendors bug fix

Qualifying IP
Cost
Lack of Stds
Timing
Reuse
Vendor Relation
0%

5%

10%

15%

20%

Source: Gartner, DAC - 2006

2007 Rambus
For Presentation purposes only

Slide 3

25%

30%

Sources of IP Problems
#1: Lack of independent verification

Unfound bugs in vendors IP can delay or halt projects

Risk of VIP checking using same models as design IP

You can
trust me!
ii

2007 Rambus
For Presentation purposes only

Slide 4

IP Integration Challenge Case Study1

IP Designed for PC

IP Repackaged for
Multimedia Mobile

CPU

Memory

North
Bridge

Graphics

Graphics

South
Bridge

Per #1

Per #n

CPU

DSP

Memory Controller

DDR

Comm

Graphics

Flash

Slide 5

IP Interface Issues
Additional logic
Understand vendors RTL
Software changes
Affects time-to-market

Bridge

Per #1

2007 Rambus
For Presentation purposes only

Video

Per #n

IP Integration Challenge Case Study2

CPU

DSP

Comm

Memory Controller

DDR

Video

Graphics

Bridge

Flash
Per #1

Comm

Comm

Per #n

Master
Model

NON-SEQ

SEQ

SEQ

IDLE

SEQ

Slave Model
NON-SEQ

Video

DDR
2007 Rambus
For Presentation purposes only

System Crash

Flash
Slide 6

Sources of IP Problems
#2: Inadequate Integration of Design and Verification IP
Installation and bringup consumes your resources
Configure VIP for your specific needs
Ensure Design IP and VIP work together
Time and resources spent unnecessarily
Creating a verification plan
Writing tests
Running non applicable tests
Measuring that required coverage is achieved

2007 Rambus
For Presentation purposes only

Slide 7

Outline

IP Challenges
PCIe Solution
Value Proposition
Verification IPs
Interoperability
Summary

2007 Rambus
For Presentation purposes only

Slide 8

High Yield, Production Proven PCI Express IP

Compute: NB

Graphics

2007 Rambus
For Presentation purposes only

Storage

Compute: SB

Bridge

Graphics

Slide 9

Customized Digital Controllers

Configurability and Flexibility for Integration
Ethernet
PCI Express
Endpoint
Root Complex
Switch/ Switch Port
Hybrid

10/100/1000 MAC
10G MAC
SPI 4.2
Single channel
Multi channel

Bridges

RapidIO

AXI
AHB

2007 Rambus
For Presentation purposes only

Serial
Parallel

Slide 10

Combining Best of Breed Design and

Verification IP

Concept

Revenue

Cadence & Rambus value proposition

Highest quality
Fastest time to revenue
Lowest risk

2007 Rambus
For Presentation purposes only

Slide 11

Best of Breed PCI Express Solution

Design IP and VIP independently cross checked
Cadence and Rambus models built independently

Design IP and VIP most tightly integrated

Executable verification plan specific to your IP
Customized test suite specific to your IP
Automated protocol Compliance Management System

2007 Rambus
For Presentation purposes only

Slide 12

Outline

IP Challenges
PCIe Solution
Value Proposition
Verification IPs
Interoperability
Summary

2007 Rambus
For Presentation purposes only

Slide 13

Value Proposition
Rambus Value
Customized application layer interface
IP designed to interface directly to high speed SoC buses
Quick integration and short time-to-market
Design services for customized interfaces

Configurable endpoint, root complex, hybrid, switch

and switch port solutions
Design aware solutions for maximum performance
Configurable per specific customer applications
GUI tool for quick configuration and area optimization

Collaboration Value
Why is the VIP important?
Want to ensure highly customizable and configurable design is
connected correctly
Combine configurable, proven design IP with best of class VIP

2007 Rambus
For Presentation purposes only

Slide 14

Customized Application Layer Interface

CPU

DSP

Comm

Graphics

AXI Bus
AXI Bridge

Memory Controller

UL Bus
DDR

2007 Rambus
For Presentation purposes only

PCIe

Flash

Slide 15

Video

Configurable Design IP Solutions

Bridge and Switch
Applications

Latency Sensitive
Applications

Shallow Transaction Layer

Shallow Transaction Layer

Shallow Transaction Layer

Application Interface

GPEX

Data Link Layer

Data Link Layer

Shallow Transaction Layer

MAC Layer

TRX

TCTL

TTX

DRX

DCTL

DTX

Logic
Layers

Transaction Layer
MAC Layer

Data Link Layer

End Point
Application
Initiator

TTM Critical Applications

Shallow Transaction Layer

Feature-rich Transaction Layer

Shallow Transaction Layer

MRX

MCTL

MTX

RX

CTL

TX

MAC Layer

Shallow Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

MAC Layer

MAC Layer

DICE: Dynamic IP Configurator and Explorator

2007 Rambus
For Presentation purposes only

End Point
Application
Target

Slide 16

DICE

2007 Rambus
For Presentation purposes only

Slide 17

Outline

IP Challenges
PCIe Solution
Value Proposition
Verification IPs
Interoperability
Summary

2007 Rambus
For Presentation purposes only

Slide 18

PCIe IP Configuration Explosion

IP must support different customer requirements

Endpoint, Root Complex or Switch

Link Width: x1 to x32
Maximum packet size: 128B to 4KB
Number of functions: 1 to 8
Number of VCs: 1 to 8
Interrupt support: INTx/MSI/MSIx
Data Width: 32b, 64b or 128b

Total of about 300 different hardware

configuration parameters
Configuration explosion: more than 150,000
Every customer has a different RTL

A new verification problem for every customer

2007 Rambus
For Presentation purposes only

Slide 19

Configuration Explosion: Block-level

Verification
MSG
15

CFG
10

PM
20

TL

DLL

MAC

40

50

60

Rambus GPEX (PCIe Core)

Total configurations for system-level verification:

15 * 10 * 20 * 40 * 50 * 60 = 360,000,000
Block-level verification decomposes verification
problem, and decouples configuration explosion

Total test setups = 15 + 10 + 20 + 40 + 50 + 60 = 195

2007 Rambus
For Presentation purposes only

Slide 20

Verification IPs

Targets Design IP
Protocol Compliance
and Integration of
Design IP and
Customer Logic

Targets Design IP
Functionality

Rambus VIP
(CoverMore)

Cadence VIP
(CMS)

Shallow Transaction Layer

Transaction Layer

Data Link Layer

MAC Layer

2007 Rambus
For Presentation purposes only

Slide 21

CoverMore Verification IP
Customer ASIC

CoverMore: Highly modular approach

Reuse across block, IP and chip level
Self-checking Design IP

GPEX
CoverMore

GPEX
Block A

Block B

Block C

CoverMore

CoverMore

CoverMore

Block A

First CoverMore
implementation based on
Cadence Specman/e

CoverMore
2007 Rambus
For Presentation purposes only

Slide 22

CoverMore IP Verification
DLL
Coverage

Seq Dr

DLL-TL-VC

Seq Dr

DLL BFM

Monitor

TL BFM

MAC
Coverage
DLL-MAC-VC

TL
Coverage
PAB-TL-VC

AXI-PAB-VC

PAB
Coverage

GPEX
PCIe-AXI-Bus
Bridge (PAB)

PAB
Checker

Transaction
Layer (TL)

Data Link
Layer (DLL)

TL
Checker

DLL
Checker

MAC
Layer

MAC
Checker

CoverMore: Coverage and verification based on Modular and reusable IPs

2007 Rambus
For Presentation purposes only

Slide 23

Cadence
eVC
VIP

CoverMore Block Level Verification

TL
Coverage
Seq Dr

PAB-TL-VC

Seq Dr

Seq Dr

DLL-TL-VC

Seq Dr

TL BFM

Monitor

PAB BFM

DLL BFM

Monitor

TL BFM

PCIe-AXI Bus
Bridge (PAB)

Transaction
Layer (TL)

TL
Checker

2007 Rambus
For Presentation purposes only

Slide 24

Data Link
Layer (DLL)

Cadence VIP Strategy

Compliance Mgmt. System

Provide Plan-to-Closure VIP

spanning full verification
process

UVC
SystemVerilog Interface | e Interface

Advanced Testbench Core

Transaction-based Acceleration

Incisive Assertion-based VIP

Incisive SpeedBridgeTM

Support most complex,

demanded protocols
Unique Compliance
Management System
Enable customers & partners
to deploy CDNSs VIP
development process
Provide tailored Verification
IP for Cadence Vertical Kits

2007 Rambus
For Presentation purposes only

Slide 25

Compliance Management System (CMS)

Automates compliance verification and reporting

Leverage Cadence uVC Functional Coverage

Key differentiator
Optimized for Rambus IP with Rambus refinements

Rambus Specific Refinements

Executable
representation of
verification objectives

Compliance
Management System
Compliance
vPlan

Reports detailed
verification status
(Coverage model)

2007 Rambus
For Presentation purposes only

Compliance
Reporting

Compliance
Coverage and
Metrics
Compliance
Test Suite

Slide 26

Protocol compliance
coverage points and
checks

Constrained random
sequences
automatically reach
~70% coverage

Outline

IP Challenges
PCIe Solution
Value Proposition
Verification IPs
Interoperability
Summary

2007 Rambus
For Presentation purposes only

Slide 27

Interoperability Objectives
Validate Design IP using 3rd party VIP
Testcases
Functional Coverage - User/system point of view
Have you covered all

Typical scenarios
Error cases
Corner cases
Protocols
States
Interrupts
Data Integrity

Provide a high quality product to the customer

Productivity enhancement
2007 Rambus
For Presentation purposes only

Slide 28

Design IP & Verification IP

Interoperability Challenges
Challenges
resolved

VIP
VIP
Rambus
Rambus

Functionality verification &

Integration challenges

VIP

VIP
VIP
Vendor#A
#A
Vendor

DesignIP
IP
Design
(GPEX)
(GPEX)
VIP
VIP
Cadence
Cadence

2007 Rambus
For Presentation purposes only

VIP
VIP
Vendor#D
#D
Vendor
Protocol compliance
challenges
Slide 29

Interoperability Challenges
Ensuring the VIP and Design IP have the same
configuration
In depth design knowledge availability
Verification IP expertise

Achieving targeted coverage of Application

Interface
Run the testcases by programming random seed

Debugging
Time consuming Root-cause analysis

2007 Rambus
For Presentation purposes only

Slide 30

Methodology
Re-create Real Customer Environment And
Experience
Maintain Verification Independence
Tool aspects
Follow release QA for eVC and Design IP
Debugging
Run regressions at CDN and Rambus
Regressions include Cadence + Rambus
testcases
Root-cause analysis
Identify bugs due to subsequent tool versions
and fix
VIP/tool bug fixes by CDN
Design IP bug fixes by Rambus
2007 Rambus
For Presentation purposes only

Slide 31

Refinement
CDN PCIe compliance vPlan has all features of
PCIe
Example - DUT configuration specific features
DUT acts as End point
RC related coverage points are disabled
Unsupported PCIe compliance points in the
design
Refined vPlan and created required
perspective which will load on CDN
compliance vPlan
2007 Rambus
For Presentation purposes only

Slide 32

vManager Regression Session

2007 Rambus
For Presentation purposes only

Slide 33

vPlan Default Perspective

Default
Perspective

Coverage
Model for
RC/EP/Legacy
EP

Root Complex
vPlan Tree

End Point
vPlan Tree

2007 Rambus
For Presentation purposes only

Slide 34

vPlan Loading Rambus Perspective

Loading
Rambus
Perspective

2007 Rambus
For Presentation purposes only

Slide 35

vPlan Rambus Perspective Loaded

EndPoint vPlan
Tree with Rambus
Perspective

2007 Rambus
For Presentation purposes only

Slide 36

vPlan Window Selected Item

2007 Rambus
For Presentation purposes only

Slide 37

Failure Report - First Failure Description

2007 Rambus
For Presentation purposes only

Slide 38

Interoperability Efforts

Strategy Managers
TL Engineer
Team Lead

Rambus VIP
(CoverMore)

Cadence
VIP

GPEX
GPEX
Design
Design IPIP

Tool R&D
Engineer
Project
Manager

DLL Engineer

Verification
Engineer

Verification
Engineer

MAC Engineer

Tool R&D
Engineer

Huge efforts spent to help the customer integrate IP smoothly

2007 Rambus
For Presentation purposes only

Slide 39

Interoperability Efforts
Many ManYears worth of efforts
Design IP Development
VIP Development
Interoperability efforts

Validation
Tool Licenses
Methodologies
Customer approval

2007 Rambus
For Presentation purposes only

Slide 40

Rambus and Cadence Collaboration Deliverables

Design IP
PCI Express Digital controller, PHY

Verification IPs
CoverMore VIP
Cadence eVC VIP
PCI Express eVC
Supports e and/or SystemVerilog test benches
PCI Express Compliance Management System
Executable verification plan (vPlan)
Test suite to achieve 70% + coverage
Rambus specific package for Verification
Refinement file for PCI Express vPlan
Additional test sequences to maximize
coverage
2007 Rambus
For Presentation purposes only

Slide 41

Outline

IP Challenges
PCIe Solution
Value Proposition
Verification IPs
Interoperability
Summary

2007 Rambus
For Presentation purposes only

Slide 42

Summary
Rambus + Cadence collaboration solves IP Integration challenges

Independently verified
Independently created models
Independently crosschecked

Tightest integration of Design IP and VIP

Rambus application interface and services for
matching custom infrastructure

Most automated solution

Cadence CMS automates verification
Digital core customizable protocol support

2007 Rambus
For Presentation purposes only

Slide 43

2007 Rambus
For Presentation purposes only

Slide 44