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QUESTION PAPER SOLUTIONS


QUE 1.WHAT ARE INTERRUPTS? EXPLAIN HOW MULTIPLE
DEVICES ARE HANDLED IN INTERRUPTS.

 In program-controlled I/O, the program enters a wait


loop in which it repeatedly tests the device status.
During the period, the processor is not performing
any useful computation.

 However, in many situations other tasks can be


performed while waiting for an I/O device to become
ready.

 Let the device alert the processor.


EXAMPLE OF WORKING:

 Some computations + print

 Two subroutines: COMPUTE and PRINT

 The printer accepts only one line of text at a time.

 Try to overlap printing and computation.


 COMPUTE produces first n lines of text;

 PRINT sends the first line to the printer; then PRINT is


suspended; COMPUTE continues to perform other
computations;

 After the printer finishes printing the first line, it send


an interrupt-request signal to the processor;

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 In response, the processor interrupts execution of


COMPUTE and transfers control to PRINT to send the
next line;

 COMPUTE resumes;

EXAMPLE OF WORKING OF INTERRUPT

IMPORTANT POINTS:
 The routine executed in response to an interrupt
request is called the interrupt service routine – PRINT

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 Assume - interrupt request arrives during execution


of instruction i

◦ Processor completes execution of instruction i.

◦ Loads the program counter with the address of


the first instruction of the interrupt service
routine, address of i+1 must be put in temporary
storage

◦ After execution of interrupt service routine, the


processor has to come back to i+1(reloads PC
from the temporary storage)

◦ Many processors – return address is saved on


the processor stack.
 Interrupt-acknowledge signal – the processor must
inform the device that its request has been
recognized so that it may remove its interrupt
request signal.

 Before starting execution of the interrupt service


routine

 Any information that may be altered during


the execution of that routine must be saved.

 This information must be restored before


execution of the interrupted program is
resumed.

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 So original program can continue execution


without being affected in any way by the
interruption, except for the time delay.

 Interrupt latency

 Task of saving and restoring done by


processor auto.

 Most processors save only minimum amount


of information because saving and restoring
in registers will take much time.

 Saving registers also increases the


delay between the time an interrupt request
is received and the start of the execution of
the interrupt service routine.

 This delay is called interrupt latency.

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INTERRUPT HARDWARE

ENABLING & DISABLING INTERRUPT:

 Since the interrupt request can come at any time, it


may alter the sequence of events from that
envisaged by the programmer.

 Interrupts must be controlled – ability to enable and


disable interruptions.

 Ignoring an interrupt happens in the previous


example (Compute and Print)

 An interrupt request from the printer should


be accepted only if there are output lines to
be printed.

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 After printing the last line of a set on n lines,


interrupts should be disabled until another
set becomes available printing.

 Another case – a particular sequence of


instructions is executed to the end with out
interruption because the interrupt-service
routine may change some of the data used
by the instructions.
 Solution –> Interrupt-enable and Interrupt-disable

 The interrupt request signal will be active until it


learns that the processor has responded to its
request. This must be handled to avoid successive
interruptions (infinite loop).

 Three possibilities of mechanisms are available to


solve this problem:

 Let the interrupt be disabled/enabled in the interrupt-


service routine.

 Processor hardware ignores the interrupt-


request line until the execution of the first
instruction of the interrupt-service routine
has been completed.

 Then, by using an Interrupt-disable


instruction as the first instruction in the
interrupt service routine (programmer can
ensure that no further interruptions will

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occur until an Interrupt-enable instruction is


executed)

 Interrupt-enable instruction is the last


instruction in interrupt-service routine

 Let the processor automatically disable interrupts


before starting the execution of the interrupt-service
routine.

 After saving the contents of the PC and the


processor status register (PS) on the stack,
the processor performs the equivalent of
executing an Interrupt-disable instruction.

 1 bit in PS register indicates Interrupt-


enable or not. If it is 1 interrupt request will
accept and after setting PC and PS,
processor clears this bit (disable further
interrupts)

 After Return-from-interrupt instruction is


executed, the contents of the PS are
restored from the stack, setting the
Interrupt-enable bit back to 1. (enable
interrupt)

 Edge-triggered – processor has a special interrupt-


request line for which interrupt-handling circuits
responds only to the leading edge of the signal. Such
a line is said to be edge-triggered.

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 Processor will receive only one request,


regardless of how long the line is activated.

 There is no danger of multiple interruptions.


HANDLING MULTIPLE DEVICES:

 How can the processor recognize the device


requesting an interrupt?

 Given that different devices are likely to require


different interrupt-service routines, how can the
processor obtain the starting address of the
appropriate routine in each case?

 (Vectored interrupts)

 Should a device be allowed to interrupt the processor


while another interrupt is being serviced?

 (Interrupt nesting)

 How should two or more simultaneous interrupt


requests be handled?

 (Daisy-chain)
VECTOR INTERRUPTS:

 To reduce time involved in the polling process


(polling- processor repeatedly checks the status
flags).

 Vectored Interrupts – refers to all interrupt-handling


schemes based on this approach.

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 A device requesting an interrupt can identify itself by


sending a special code to the processor over the bus.

 This enables the processor to identify individual


devices even if they share a single interrupt-request
line.

 Then, the processor can immediately start executing


the corresponding interrupt-service routine.
 Code supplied – starting address of the interrupt-
service routine. (Address – interrupt vector)

 Processor reads this address and loads it into the PC.

 Avoid bus collision – when a device sends an


interrupt request, the processor may not be ready to
receive. The device must wait to put data on the bus
when the processor is ready to receive.

 When the processor is ready, it activates the


interrupt-acknowledge line, INTA.

 The I/O device responds by sending its interrupt-


vector code and
Turning off the INTR signal.

INTERRUPT NESTING:

 Simple solution: only accept one interrupt at a time,


then disable all others.

 Problem: some interrupts cannot be held too long.


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 Priority structure

INTR 1 I NTR p
Processor

Device 1 Device 2 Device p

INTA1 INTAp

Priority arbitration
circuit

Figure 4.7.   Implementation of interrupt priority using individual
interrupt­request and acknowledge lines.

 Simultaneous Requests

 The processor must have some means of


deciding which request to service first

 Processor simply accepts the request having


the highest priority

 Widely used scheme – daisy chain

 INTA signal propagates serially


through the devices.

 When several devices raise an


interrupt request and the INTR line
is activated, the processor
responds by setting the INTA line to
1.
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 This signal is received by device 1.

 Device 1 passes the signal on to


device 2 only if it does not require
any service.

 If device 1 has a pending request


for interrupt, it blocks the INTA
signal and proceeds to put its
identifying code on the data lines.

 So, the device that is electrically


closest to the processor has the
highest priority., second device has
second priority
SIMULTANEOUS REQUEST:

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CONTROLLING DEVICE REQUEST:

 Some I/O devices may not be allowed to issue


interrupt requests to the processor.
Two independent mechanisms for controlling interrupt
requsts:

 At device end, an interrupt-enable bit in a control


register determines whether the device is allowed to
generate an interrupt request.

 At processor end, either an interrupt enable bit in the


PS register or a priority structure determines whether
a given interrupt request will be accepted.
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Example
Consider a processor that uses the vectored interrupt
scheme, where the starting address of the interrupt-
service routine is stored at memory location INTVEC.
Assume,
 Interrupt - enable bit is 9th bit.

 Some point in Main program, we wish to read an


input line from the keyboard and store the chars. In
successive byte locations in memory starting at
location LINE.

 Steps:

 Load the starting address of the interrupt-


service routine in location INTVEC.

 Load the address LINE in memory location


PNTR.

 Enable keyboard interrupts by setting bit 2


in register control to 1.

 Enable interrupts in the processor by setting


to 1 the IE bit in the processor status
register, PS.
Main program:
Move #LINE,PNTR Initialize buffer pointer
Clear EOL Clear End of line indicator.
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BitSet #2,CONTROLEnable keyboard interrupts.


BitSet #9,PS Set interrupt-enable bit in the
PS.

QUE 2. EXPLAIN CACHE MAPPING FUNCTIONS.


CACHE:

 Why we need it?

 The speed of the main memory is very low


in comparison with the speed of modern
processors.

 Locality of reference

 Cache mechanism is based on a program


called locality of reference

 Analysis – most of a execution time is spent


on routines which many are executed
repeatedly – may constitute a loop, or few
procedures call repeatedly.

 Many instructions in localized areas of the


program executed repeatedly.

 Manifest in two ways:


- temporal (recently executed instructions is likely to
be executed again very soon)

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- spatial (instructions in close proximity to a recently


executed instr.)

 What is cache?

 If the active segments of a program can be


placed in a fast cache memory, then the
total execution time can be reduced
significantly.
 Cache block – cache line

◦ A set of contiguous address locations of some


size

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QUE 3. EXPLAIN VIRTUAL MEMORY ADDRESS


TRANSLATION.

 Physical main memory is not as large as the address


space spanned by an address issued by the
processor.
232 = 4 GB, 264 = …

 When a program does not completely fit into the


main memory, the parts of it not currently being
executed are stored on secondary storage devices.
 Techniques that automatically move program and
data blocks into the physical main memory when

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they are required for execution are called virtual-


memory techniques.
 The binary addresses that the processor issues for
either instructions or data are called virtual or logical
addresses.

 These Virtual addresses will be translated into


physical addresses by a combination of hardware
and software components.

 If a virtual address refers is available in main


memory then the contents are accessed
immediately.

 Otherwise, contents must be brought in to a suitable


location in the memory before they can be used.

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ADDRESS TRANSLATION:

 Assume,

 All programs and data are composed of fixed-length


units called pages, each of which consists of a block
of words that occupy contiguous locations in the
main memory.

 Page cannot be too small or too large.

 The virtual memory mechanism bridges the size and


speed gaps between the main memory and
secondary storage – similar to cache (only speed
gap).

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 The page table information is used by the MMU for


every access, so it is supposed to be with the MMU.

 However, since MMU is on the processor chip and the


page table is rather large, only small portion of it,
which consists of the page table entries that
correspond to the most recently accessed pages, can
be accommodated within the MMU.
 A small cache, called Translation Lookaside Buffer
(TLB) is incorporated into the MMU.

 TLB operation is same as the operation cache.

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 In addition to the information that constitutes page


table entry, the TLB must also include the virtual
address of the entry.
QUE 4. EXPLAIN BUS ARBITRATION.
BUS ARBITRATION:
 The device that is allowed to initiate data transfers
on the bus at any given time is called the bus
master.

 Bus arbitration is the process by which the next


device to become the bus master is selected and bus
mastership is transferred to it.

 Need to establish a priority system.


 Two approaches: centralized and distributed

 Centralized – a single bus arbiter performs the


required arbitration.

 Distributed – all devices participate in the selection of


the next bus master.

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 The bus arbiter may be the processor or a separate


unit connected to the bus.

 If processor contains bus arbitration circuitry –


processor is normally the bus master unless it grants
bus mastership to one of the DMA controllers.

 DMA controller needs become bus master – activate


Bus-Request line BR.

 The signal one the Bus-Request line is logical OR of


the bus requests from all the devices.

 When Bus-Request is activated, the processor


activates Bus-Grant signal, BG1

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 This signal is connected to all DMA controllers using


daisy-chain

 The current Bus master indicates to all devices using


Bus Busy signal BBSY.

 Hence, after receiving Bus-Grant signal, a DMA


controller waits for Bus-Busy to become inactive,
then assumes mastership of the bus.

 At this time, it activates Bus-Busy to prevent other


devices using the bus at the same time.

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(A)DMA-DIRECT MEMORY ACCESS


INTRODUCTION-A special control unit may be provided to
allow transfer of a block of data directly between an
external device and the main memory without cotineous
intervension by the processor.
- DMA transfer are performed by a control circuit that is a
part of I/O device interface .this circuit is called DMA
CONTROLLER.

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DMA CONTROLLER performs the function that would


normally be carried out by the processor.when accessing
the main memory for each word transferred.it provides
the memory address and all the bus signal needed for
data transfer ,increment the memory of transfer.
DMA-PROCEDURE
-Although dma controller can transfer data without
intervention of processor it must be under the control of a
programe executed by the processor.
-processor sends the starting address,the number of data
and the direction of transfer to dma controller.
-DMA suspends the application programe requesting DMA
transfer and starts another programe.
-After the DMA transfer is done ,DMA controller sends an
interrupt signal to the processor.
DMA CONTROLLER REGISTER:

ACCCESSED THE PROCESSOR TO INITATE TRANSFER


OPERATIONS

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31 30 1 0

Status and control

IRQ Done
IE R/ W

Starting address

Word count

Figure 4.18. Registers in a DMA interf ace.

- Two address are used for storing the starting address


and word count
- Third register contains ststus and control flags.
- The R/W bit determines direction of the
transfer.When this bit is set to 1 by a programe
instruction.The controller performs a read
operation.otherwise it performs a write operation.
- When the controller has completed transfer of data
and is ready to receive another commmand,it set
done flag to 1.

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- 30 is the interrupt enable flag when this flag is set to


1,it causes the cotroller to raise an interrupt
- -IRQ bit to 1 when it has requested an interrupt.

Main
Processor
memory

System bus

Disk/DMA DMA
controller controller Printer Keyboard

Disk Disk Network


Interface

Figure 4.19. Use of DMA controllers in a computer system.

• A DMA controller connects a high speed network to


computer bus.
• The disk contoller which control two disks also has
DMA capability and provides two DMA channels.
• IT can perform two independent DMA operations.
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• MREMORY ACCESS
• Memory access by the processor and the DMA
controller are interwoven.
• DMA device has higher priority for using bus than
processor
• Among all DMA requests to priority is given to high
speed peripherals.
• Cycling stealing-since processor originates most
memory access cycles the dma controller can be said
to steal memory cycle from the processor.
• block(brust) modern DMA controller may be given
execlusive access to the main memory to transfer a
bloack data without interruption.

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(B)Assembler Directives
 Allow programmer to specify other information
needed to translate the source program into object
program – assembler directives/commands.
 For eg., SUM is used to represent the value 200. This
fact is conveyed to the assembler program through a
statement such as SUM EQU 200 - informs the
assembler the name SUM should be replaced by the
value 200 wherever it appears in the program.

 Label Operation Operand(s) Comment


Sample Program

- How to interpret the names


- Where to place the instructions
- Where to place the data operands
In the memory

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Assembly and execution of programme

 Assembler’s task (source → object)

 Replace all symbols denoting operations and


addressing modes with the binary codes used in
machine instructions

 Replace all names and labels with their actual values


 Assign addresses to instructions and data blocks
(ORIGIN, DATAWORD, RESERVE)

 Determine the values that replace the names (EQU,


label)

 Branch address (Relative addressing, branch offset-


which is the distance to the target)
 Scan through the source program, keep track of all
names and the numerical values that correspond
them in a symbol table. – when a name appears
second time, it is replaced with its value from the
table.

 What if a name appears as an operand before it is


given a value (forward branch)? - scans source
program twice (solution)
 Two-pass assembler – during first pass, assembler
will create a complete symbol table. At the end of
this pass, all names will have been assigned

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numerical values. Second time, subs. Values for all


names.

©READ ONLY MEMORY

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The data stored in a ROM are of perm anent in


nature.when the power of ROM is switch of the data is not
deeted.When the power is on ROM remains the data
stored in a memory.ROM is based on the fact that there is
a mesh of diode or fuses plased in a matrix form.The
selected fuses are burnt as per the data to be stored in
the rom.Similarly the prense or absence of diode or fuses
denotes whether bit 0 or 1 is stored.

(D)MICRO PROGRAMME CONTROL


MICROPROGRAMMED CONTROL is an alternative scheme
of step counter and a decoder and encoder in which
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control signals are generated by a programme similar to


machine language programe.First we introduce some
common terms. A control word is a word whose individual
bits represents various control signals.Each of the control
steps in the control sequence of instruction defines a
unique combition of 1’s and 0’s in the control word.

BASIC ORAGINATION OF A MICROPROGRAMMED


CONTROL UNIT

Starting address
generator
IR

Cloc µPC
k

Control
store

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Q.2 WHAT IS AN INTERRUPT?EXPLAIN HOW MULTIPLE


DEVICES ARE HANDLED IN INTERRUPTS.
ANSWER-Nomal execution of a programme may be
preempted if some device requires urgent servicing
-The normal execution of a current program must be
interrupt the device raises an interrupt signsl.
- Interrupt service routine.
- current system information backup and
restore(pc,general register,control information,specific
information.
EXAMPLE:

 Some computations + print

 Two subroutines: COMPUTE and PRINT

 The printer accepts only one line of text at a time.

 Try to overlap printing and computation.


 COMPUTE produces first n lines of text;

 PRINT sends the first line to the printer; then PRINT is


suspended; COMPUTE continues to perform other
computations;

 After the printer finishes printing the first line, it send


an interrupt-request signal to the processor;
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 In response, the processor interrupts execution of


COMPUTE and transfers control to PRINT to send the
next line:

 COMPUTE resumes;

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sequence of data

Explain single bus structure.


Sol:-
A group of lines that serves as a connecting path for
several devices is called a bus. In additition to the
lines that carry the data the bus must have lines for
address and control purposes.

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Input Output Memory Processor

Figure 1.3.    Single­bus structure.

According to this figure:-

• All Functional units are interconnected to a bus,


here bus are used for only one transfer at a
time. Only two units can
Actively use the bus at any given time.

• Bus control lines are used to arbitrate multiple


requests for use of the bus. The main virtue of a
single bus-structure is its low cost and its
flexibility for attaching peripheral devices. Some
time systems that contain multiple buses
achieve transfers to be carried out at the same
time.

• The devices connected to a bus vary widely in


their speed of operation. Some
electromechanical devices, such as Keyboards
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and printers, are relatively slow. Others like


magnetic or optical disks are considerably
faster .Memory and processor units operate at
electronic speeds making them the fastest parts
of a computer. Because all these devices must
communicate with each other over a bus.

• A common approach is to include buffer


registers with the devices to hold the
information during transfers.
The buffer registers out timing difference among
processors,memories,and I/0 divices.They prevent a high
speed of processor from being locked to a slow I/0 device
during a sequence of data transfer.

 Explain the following (a) little endian


assignment.
(b) Big endian
assignment.

Solution:-
Big-Endian: lower byte addresses are used
for the most significant bytes of the word.

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Little-Endian: opposite ordering. Lower byte


addresses are used for the less significant bytes of
the word.

 Both little – endian and big – endian assignments are


used in commercial machines.

 Both cases, byte addresses 0, 4, 8…. Are taken as


addresses of successive words in the memory.

 Addresses are used when specifying memory read


and write operations for words.

 It is also necessary to specify the labeling of bits


within a byte or a word.

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Question: Explain Booth’s algorithm to multiply two


signed numbers with an example
Answer
A powerful algorithm for singed-number multiplication is
booth’s algorithm ,which is generates 2n-bit product and
treats both the positive and negative number uniformly.
this algorithm suggest that we can reduce the number of
operation required for multiplication by representing
multiplier as a difference between two numbers. It takes
into consideration the fact that 0’s in the multiplier
require just shifting, and 1’s in the multiplier from bit
position n to bit position m can be treated as 2 n+1- 2m

 For a negative multiplier, a straightforward solution is


to form the 2’s-complement of both the multiplier

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and the multiplicand and proceed as in the case of a


positive multiplier.

 This is possible because complementation of both


operands does not change the value or the sign of
the product.

 A technique that works equally well for both negative


and positive multipliers – Booth algorithm.

for example. 0011110.to derive the product, we could


add four appropriately shifted versions of the
multiplicand ,as in the standard procedure. how ever we
can reduce the number of required operation by
regarding this multiplier

1 0 0 1 1 (-1 3 )
0 1 0 1 1 (+11)
11111 1 0 0 1 1
1111 10 0 1 1
sign extension is shown in bold
000 0 0 000
111 001 1
00 0 000
1 1 0 1 1 1 1 0 0 0 1 (-143)

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Fig: sign extension of negative multiplicand


In general, in the Booth scheme, -1 times the shifted
multiplicand is selected when moving from 0 to 1, and +1
times the shifted multiplicand is selected when moving
from 1 to 0, as the multiplier is scanned from right to left
0 0 1 0 1 1 0 0 1 1 1
0 1 0 1 1 0 0

0 +1 -1 +1 0 -1 0 +1 0 0
-1 +1 -1 +1 0 +1 0 0
Figure Booth recoding of a multiplier
The booth technique for recording multiplier is
summarized in below table.
The transformation 011….110 +100…0-10 is called
skipping over 1s
Multiplier version
of multiplication
Bit i bit i-1 selected by bit i.
0 0 0 ×M
0 1 1 ×M
1 0 -1 ×M
1 1 0× M
Figure Booth multiplier recoding table

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Q:explain restoring binary division with neat diagram


Answer
An n bit positive divisor is loaded into register M and n-
bit positive dividend is loaded into register Q at the start
of operation,register A is set to 0 .after the division is
complete ,the n-bit quotient is the register Q and
remainder is an register A,the required subtraction are
facilitated by using 2’s complement arithmetic.the extra

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bit position at the left end of both A and M


accommodates the sing bit during subtractions.
Division Steps
Shift A and Q left one binary position
Subtract M from A, and place the answer back in A
If the sign of A is 1, set q0 to 0 and add M back to A
(restore A); otherwise, set q0 to 1
Repeat these steps n times

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Question: write about IEEE Floating point Standard


Answer:
A general form and size for floating-point numbers is
decimal system,and then relate this form to a comparable
binary representation a use ful form is
±X1.X2X3X4X5X6X7×10±Y1Y2
It is possible to approximate this mantissa precision and
scale factor range in a binary representation that
occupies 32 bits: 24-bit mantissa (1 sign bit for signed
number), 8-bit exponent.
Instead of the signed exponent, E, the value actually
stored in the exponent field is an unsigned integer
E’=E+127, so called excess-127 format

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 For excess-127 format, 0 ≤ E’ ≤ 255. However, 0 and


255 are used to represent special value. So actually
1 ≤ E’ ≤ 254. That means -126 ≤ E ≤ 127.
 Single precision uses 32-bit. The value range is from
2-126 to 2+127.
BDouble precision used 64-bit. The value range is
from 2-1022 to 2+1023.

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 What is an addressing mode? Explain the


different addressing modes with example
Solution:-

Addressing modes are referred to as


facility provider during translating a high level
language program into assembly language
program, the compiler must be able to

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implement these constructs using the facilities


provided in the instruction set of the computer in
which the program will be run. The different
ways in which the location of an operand is
specified in an instruction are referred to as
addressing modes.

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