IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 59, NO.

6, JUNE 2012

331

Area-Efficient Low-Noise Low-Spur Architecture

for an Analog PLL Working From
a Low Frequency Reference
Xiao Pu, Ajay Kumar, and Krishnaswamy Nagaraj

AbstractThis brief presents an area-efficient low-noise architecture for an analog phase-locked loop (PLL) working off a low
frequency reference. The architecture has been demonstrated in
a 100400-MHz PLL implemented for wireless connectivity and
broadcast applications. It can easily be extended to gigahertz
(GHz) operations. A low reference frequency forces a low loop
bandwidth, which requires large loop filter components. The challenge is to keep the area small while meeting the jitter specs.
By using a charge-pumpless architecture with a novel windowing
function, we were able to stabilize the loop with a large resistor
and a moderate capacitor without degrading phase noise due to
the large thermal noise from the resistor. This provides substantial
advantage for area reduction. The windowing function also improves leakage-induced spurs by 16 dB. The PLL was designed in
a 45-nm CMOS all-digital process. It occupies an area of 0.09 mm2
and draws a total current of 800 A.
Index TermsClock generation, low-reference PLL, phaselocked loop (PLL).

I. I NTRODUCTION

NALOG PHASE-LOCKED LOOPS (PLLs) are widely

used for clock generation and timing recovery in modern
systems-on-chip (SOCs). The focus of this brief is on the PLLs
used for clock generation in the digital baseband portion of
wireless transceivers. In a typical wireless receiver, the incoming radio-frequency signal is first amplified and mixed down to
an intermediate frequency (IF). The IF signal is further amplified and digitized by an analog-to-digital (A/D) converter and
then subjected to complex digital signal processing to recover
the desired signal. The clock signal for the A/D converter is
generally required to have very low phase noise in order to
meet tight signal-to-noise requirements. As the on-chip local
oscillator will have a variable frequency, it generally cannot be
used to run the base band blocks. A separate fixed-frequency
PLL is required for this function. In many instances, the input
reference clock (FREF ) source available for this PLL is a lowfrequency (32-kHz) crystal [1][5]. One example of this is
the frequency-modulation (FM) transceiver, which is now an

Manuscript received July 14, 2011; revised September 12, 2011, October 31,
2011 and February 14, 2012; accepted April 7, 2012. Date of publication
May 22, 2012; date of current version June 12, 2012. This brief was recommended by Associate Editor P.-I. Mak.
The authors are with Texas Instruments Incorporated, Dallas, TX 75266 USA
(e-mail: pu@ti.com, akumar@ti.com, nagaraj@ti.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2012.2195064

Fig. 1. Conventional second-order PLL.

integral part of virtually every smart phone. Although a highfrequency crystal oscillator is available on these phones, the FM
receiver, which can have long play times, is required to work off
of a 32-kHz reference in order to minimize power consumption.
The low input frequency limits the loop bandwidth that the PLL
can have, which, in turn, makes it very difficult to implement
the PLL without external components. This brief describes a
fully integrated low-FREF PLL architecture that has been used
in an FM receiver, which is part of a multiradio SOC for
mobile phone applications. Results from a 45-nm prototype are
presented and analyzed.
Fig. 1 shows the block schematic of a commonly used
second-order PLL [6],[7]. It consists of a voltage-controlled
oscillator (VCO), whose output is divided down to the reference
frequency to generate a feedback clock (FBCLK). A phasefrequency detector (PFD) operates on the input reference (REFCLK) and FBCLK to produce an error signal in the form of
UP or DN pulses, depending on whether FBCLK is lagging or
leading REFCLK. These pulses drive a charge pump that puts
out proportional amounts of current into a passive loop filter
whose output controls the VCO frequency. In close loop, the
system has a second-order phase-domain transfer function. R1
and C1 constitute the main loop filter, whereas C2 is a relatively
small capacitor that provides an additional pole for filtering out
high-frequency ripple from the charge pump operation. The
3-dB bandwidth (3dB ) and the damping factor () of this
response are given by [6]
3dB

Kv
ICP R1
M

where ICP is the charge pump current, and Kv is the VCO gain
(in hertz per volts).
The very low input reference frequency impacts the design
of the PLL in several ways: 1) Any leakage current in the filter

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Fig. 2. Proposed architecture in its basic form.

capacitors would cause a significant droop in the filter output,

which, in turn, modulates the VCO frequency, causing serious
reference spurs. For this reason, these capacitors cannot be
realized using the high-efficiency metaloxidesemiconductor
(MOS) capacitors, which are very leaky. Instead, we would
have to use metalinsulatormetal (MIM) capacitors, which
have very low leakage but are very highly area intensive. 2)
The 3-dB bandwidth of a PLL system generally has to be
less than 1/10 of the reference frequency in order for the loop
to be stable. This would put the loop bandwidth here to be
about 3 kHz. 3) Another requirement from the loop stability
is that damping factor has to be close to 1 or higher. From
this point of view, the frequency of the zero formed by
R1 and C1 will have to be less than one half of the 3-dB
bandwidth of the PLL. Let us consider the case where the output
frequency is 200 MHz and Kv is 500 MHz/V. If we apply the
aforementioned constraints and limit C1 to tens of picofarad,
we would require R1 to be a few M and ICP on the order of
100 nA. While these are, in theory, achievable in short-channel
technologies, there are several practical issues: First, it is very
difficult to operate the loop at such low charge pump current
levels. The dynamic currents due to charge injection from the
switches would, in practice, be much larger in magnitude and
would cause significant reference spurs. Second, although the
large-value resistor is achievable in a reasonable area, it would
produce a large amount of thermal noise that translates into
excessive phase noise. A previously reported charge-pumpless
architecture [8] mitigates some of the problems with charge
pump but still has the problem of high noise due to the large
resistor. One solution to the noise problem would be to use a
large-value external capacitor for C1 [3]. This would allow us
to use a smaller resistance and lower its noise. However, such
a solution requires an external component, board space, and an
additional pin.
II. P ROPOSED A RCHITECTURE
The aforementioned problems are overcome in the proposed
implementation by using a novel charge-pumpless active loop
filter. Fig. 2 shows the proposed architecture in its basic form.
The charge pump is eliminated. Instead, the UP and DN voltage
pulses from the PFD are passed through resistive potential
dividers, providing an attenuation factor , and then directly
applied to the inputs of an operational-amplifier-based differential low-pass filter. A key distinguishing feature of this loop

Fig. 3.

Loop filter with the windowing function.

filter architecture is a single large resistor R1 playing the dual

role of emulating a small charge pump current and providing
a low frequency zero in conjunction with C2 . Resistor R2 in
conjunction with C2 provides the high-frequency pole and is
much smaller than R1 . It can be shown that, with this loop
filter, the 3-dB frequency and damping factor for the PLL are
given by

1 ICP Kv C1
R1 .
=
2
M
The attenuators on the UP and DN pulses help emulate the
effect of a small charge-pump current (100 nA) without the
disadvantages of operating a charge pump with a small current.
An attenuation factor of around 5 is easily achievable with very
little area and power dissipation. The capacitors C1 in Fig. 2
have to be MIM capacitors to avoid leakage current. However,
capacitors C2 , which are connected to the summing node of the
amplifier, sustain a very small voltage and therefore have no
leakage. They can be high-density poly-n-well capacitors. The
architecture of Fig. 2 still has two problems: First, thermal noise
from R1 will affect phase noise. Second, the offset and finite
gain component at the amplifier summing node causes current
flow through R1 . This results in a droop in the filter output
from one reference edge to the next. This, in turn, gives rise
to reference spurs. Both these problems are addressed by the
addition of a novel windowing function (enhanced version of
[9]), as shown in Fig. 3. Here, two switches are introduced in
series with resistors R1 . During initial locking, these switches
are kept permanently on, and the PLL acquires lock in the
conventional manner. Once lock is achieved, the switch control
signal WIN becomes a pulse that starts a little before the
beginning of the UP/DN pulses in every reference cycle and
ends a little after the end of the UP/DN pulses, as shown at the
bottom of Fig. 3. Under the locked condition, minimum-width
pulses are created on UP/DN at the beginning of each reference
cycle to correct for noise and occasional drift. For the rest of the
cycle, the loop is largely idling. By introducing a windowing
function to disconnect the large R1 while the loop is idling, we
limit its noise contribution to a fraction of the reference cycle.

PU et al.: AREA-EFFICIENT ARCHITECTURE FOR ANALOG PLL WORKING FROM LOW FREQUENCY REFERENCE

Fig. 4.

333

Excessive current injection due to narrow window.

Fig. 6. Simplified schematic of the window generator.

Fig. 5.

Loop ringing due to narrow window.

The effect of leakage current from the amplifier summing node

voltage is virtually eliminated as well.
The exact pulsewidth of WIN is not very critical, but it has
to stay high long enough for the current flow from the UP/DN
inputs to be complete. In fact, an excessively narrow window
would lead to excessive loop gain and loop instability. This
occurs because of the parasitic capacitance associated with
n-well resistors. During the UP/DOWN pulses, the parasitic
capacitances of part of R1 that is physically closer to the WIN
switches present a short circuit to ground and absorb much
charge. If the window is terminated prematurely, all the charge
trapped in the parasitics will discharge slowly (governed by
the RC time constant) into the opamp summing node. This is
illustrated in Fig. 4, which shows transient currents exiting R1
and flowing into the opamp summing node. As we can see,
with a shorter window, much current continues to flow, even
after the window is terminated. This results in the effective
value of R1 being smaller than intended. On the other hand,
a longer window allows the excess charge from the parasitics
to flow back in to the UP/DOWN terminals. Fig. 5 shows the
simulated step response of the VCO control voltage with a
5-s window and 5-ns window. A distinctive ringing is seen
on the latter. This is mitigated by using a longer window,
which allows for the excess charge trapped in the parasitic
capacitance to flow back to the PFD side. However, a longer
window results in an increase in the noise contribution from
R1 , but it is possible to keep the window narrow enough to
realize a significant reduction in the noise when compared to a
conventional implementation. Two important attributes of this

architecture is that the UP and DN pulses do not operate any

switches but are directly fed to the loop filter and that polarities
of the UP and DN currents are the same. These help minimize
mismatches between the UP and DN paths.
WIN is generated using very simple digital circuitry. In equilibrium, input common-mode voltage at the amplifier inputs
assumes a value such that average current flowing in from the
UP/DN pulses is balanced by the average current flowing out
during the interval between the end of the UP/DN pulse and
the end of the WIN pulse. In our implementation, the value
of this voltage is on the order of 100 mV. This low commonmode voltage combined with the fact that the attenuated UP and
DN pulses have a small amplitude enable the use of n-channel
MOS (NMOS)-only switches for the windowing function. Most
of the charge injected by these switches when they are turned
off will go toward the UP/DN outputs because of the relatively
lower impedance compared to R1 . The residual charge injected
toward the loop filter will be largely canceled by the differential
architecture and further filtered heavily by the loop filter.
Switches cannot be used in series with R2 because the time
constant associated with the branch R2 C2 is larger than a
REFCLK period. Fortunately, the value of R2 being relatively
small does not contribute a significant amount of noise.
III. C IRCUIT B LOCKS
A simplified schematic of the window control generator is
shown in Fig. 6. The PFD outputs are designated as UP and
DN. The earlier of these triggers a ONE-SHOT, which starts
WIN. UP and DN are slightly delayed to generate the UP
and DN pulses for the loop filter. This effectively starts WIN
a little early. This is necessary in order to avoid introducing a
signal-dependent error. If WIN coincides with either UP or DN,
then the phase information for the time it takes to turn on the
switch would be lost. In our implementation, the one-shot has
been realized by using a counter that sets the pulsewidth to a
programmable number of VCO clock periods. An OR gate is
used to force WIN high whenever the PLL is out of lock.
Fig. 7 shows the block schematic of the operational amplifier.
The p-channel MOS differential pair MP1 and MP2 forms the
main input pair. A small NMOS differential pair MN1 and

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 59, NO. 6, JUNE 2012

Fig. 9. Measured phase noise X-axis: 100 Hz to 10 MHz; Y -axis: 20 to

150 dB.
Fig. 7. Circuit schematic of the operational amplifier.

Fig. 10. Measured phase noise with different window sizes X-axis: 100 Hz
to 100 kHz;Y -axis: 40 to 100 dB.

Fig. 8. Chip micrograph.

MN2 is included in parallel to provide amplification just in

case the amplifier input common mode gets stuck at a high
value during startup. The amplifier uses a class-AB output
stage for power efficiency. The oscillator core consists of a
ring oscillator made up of three CMOS inverters. The ring
oscillator supply is connected to the loop filter output. A levelshifting buffer translates the oscillator output to the digital
supply voltage domain. The sizes of the transistors forming the
ring, which have a strong bearing on the phase noise and power
consumption of the VCO, have been optimized carefully.
The feedback divider uses a dual-modulus prescaler, followed by a pulse-swallowing counter. The output of the divider
is resynchronized to the VCO output to eliminate phase noise
from the divider stages. The reset state of the divider is arranged
such that the very first VCO clock edge that occurs after
the reset is deasserted results in a FBCLK edge. This feature
facilitates a zero phase start, which is important in certain applications. The PFD uses a standard two-flip-flop architecture.
IV. E XPERIMENTAL R ESULTS
This PLL has been designed and fabricated in a 45-nm sixlayer metal digital CMOS technology. A micrograph of the
chip is shown in Fig. 8. It measures 320 270m2 . The PLL

uses two supply voltage domains. The digital circuits work

from the main digital supply of the SOC, whereas the analog
circuits work from a separate supply generated by an on-chip
low-dropout regulator. The prototype has been tested at up to
400 MHz as this is determined by the applications for which
the PLL was intended. The architecture can be easily extended
to gigahertz PLLs by redesigning the ring oscillator for a higher
center frequency. Fig. 9 shows the measured phase noise of the
test clock, which is the divide-by-four of the output at 184 MHz.
The two contrasting curves show the cases with windowing
function enabled and disabled, respectively. It can be seen that
the windowing function provides 15-dB reduction of in-band
phase noise, most of which is due to the large R1 . An expanded
view of the phase noise with various window lengths is shown
in Fig. 10. The top curve is the phase noise when window is
disabled, and the rest are for window sizes ranging from 0.5 to
2.5 s in seven steps. A smaller window size reduces the inband phase noise arising from R1 but increases loop peaking
(due to the parasitic capacitance effect discussed in Section II).
The high-frequency spurs seen on the phase noise plot are not
from the PLL but from the test setup. The output spectra for the
max and min windows are captured in Figs. 11 and 12. It is seen
that the windowing function gives a 16-dB improvement in the
32-kHz reference sidebands. The entire PLL consumes 800 A
of current. The rms jitter for audio band ranging from 300 Hz
to 10 kHz is calculated by integrating the
SSB phase noise for
this band and normalized with a factor of ( 2T /2) to convert

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335

as well as spurs from droop in the VCO control voltage due

to leakage. The windowing function also allows for significant
area reduction by using a large n-well resistor and a moderate
MIM capacitor to implement the loop filter. For comparison
with conventional loop architecture without the windowing
function, to achieve the same phase noise performance, the
resistance would have to be reduced five times (15-dB-lower
phase noise), and the capacitance would have to be increased
five times. Since the loop filter occupies 55% of the total
silicon area (of which 35% is the n-well resistor), this would
nearly double the total chip area. This PLL has been used in
an FM transceiver [5], which is part of a multiradio wireless
connectivity SOC. An audio SNR of better than 64 dB has been
achieved.
Fig. 11. Measured output spectrum with windowing.

ACKNOWLEDGMENT
The authors would like to thank Stanley Goldman for his
contributions.
R EFERENCES

Fig. 12. Measured output spectrum without windowing.

from radian to second, and the result is 650 ps. The rms jitter
integrated from 10 MHz to fvco /2 is 3.5 ps.
V. C ONCLUSION
An analog PLL intended for wireless connectivity and broadcast application has been presented in this brief. The main
challenge in these applications is that the PLL has to work
from very low frequency reference clock (32 kHz), in order to
save power in the SOC. The design presented here uses a novel
architecture that includes a windowing concept that mitigates
the problems of excessive thermal noise from the loop filter,

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