(C2)

80x86 Internal Architecture

Computer Operation Model

FETCH Instruction - EXECUTE Instruction
FETCH

EXECUTE FETCH

EXECUTE FETCH

EXECUTE

time

FETCH

EXECUTE

1) Read Instruction from Memory

2) Decode/Interpret Instruction
3) Increment Instruction Address Register
1) Control Unit - Input is Decoded Instruction
2) Control Signals Set
3) Data is Processed

8086 Architecture Specifics

BIU and EU - Pipelined Arrangement

BIU - Bus Interface Unit

Instruction Pipeline
EU - Execution Unit
Pipeline - Hardware Designed for Parallel Operation

BIU

FETCH

FETCH

EU

WAIT

EXECUTE

FETCH

FETCH

EXECUTE

time

FETCH GET DATA

EXECUTE

8086 Internal Architecture

Execution Model

8086 Overall Architecture

BIU and EU - Pipelined Arrangement

Instruction
Pipeline
EXECUTION
UNIT
EU

BUS
INTERFACE
UNIT BIU

System Bus (PC Bus)

Address Bus

Data Bus

Instr. Decode;
Bus Controller

EU

AH

AL

BH

BL

CH

CL

DH

DL

BP
DI
SI
SP

ADD

CS
ES
SS
DS
IP

SYSTEM BUS (Internal)

ALU/EXECUT
FLAGS

BIU

3
4
5
6

Instruction
Queue

Content of the EU: Content of the BIU: .

BIU Bus Interface Unit

(Resp: signals and data/instruction
control)

To bring the instructions into the

internal QUEUE
To control the content of the queue
To computes the address
To generates the control signals

BIU - contents
Bloc for controlling the signals
FIFO memory to implement the 6 byte
s queue
Instruction pointer (next instruction to
be executed)
ALU to calculate the address
Internal communication registers
Registers for memory segmentation

EU Execution Unit

Decoding of instructions
ALU
General registers (accessible by user)
Internal registers (internal operations)
Register to store the status and contr
ol of the program

AL
BL
CL
DL

AH
BH
CH
DH

Accumulator
Base
Counter
Data
15

Code Segment
Data Segment
Stack Segment
Extra Segment

Destination Index

AX
BX
CX
DX
0

CS
DS
SS
ES
15

Instruction Pointer
Stack Pointer
Base Pointer
Source Index

IP
SP
BP
SI
DI

}
}

For 32 bit processors: AX register (16b) EAX (32b)

8086/8088 Register File (cont)

Instruction Pointer Register
15

IP Contains Address of NEXT Instruction to be Fetched

Automatically Incremented
Programmer can Control with jump and branch

AX, BX, CX, DX

General Purpose Registers
7

Accumulator
Base
Counter
Data

AH
BH
CH
DH

AL
BL
CL
DL

Can Be Used Separately as 1-byte Registers

AX AH:AL
Temporary Storage to Avoid Memory Access
Faster Execution
Avoids Memory Access

Some Special uses for Certain Instructions

AX, BX, CX, DX

General Purpose Registers - Some Specialized Uses
7

Accumulator
Base
Counter
Data

AH
BH
CH
DH

AL
BL
CL
DL

AX, Accumulator
Main Register for Performing Arithmetic
mult/div must use AH, AL
accumulator Means Register with Simple ALU
BX, Base
Point to Translation Table in Memory
Holds Memory Offsets; Function Calls
CX, Counter
Index Counter for Loop Control
DX, Data
After Integer Division Execution - Holds Remainder

CS, DS, ES, SS - Segment

Registers
Contains Base Value for Memory Address
CS, Code Segment
Used to point to Instructions
Determines a Memory Address (along with IP)
Segmented Address written as CS:IP

DS, Data Segment

Used to point to Data
Determines Memory Address (along with other registers)
ES, Extra Segment allows 2 Data Address Registers

SS, Stack Segment

Used to point to Data in Stack Structure (LIFO)
Used with SP or BP
SS:SP or SP:BP are valid Segment Addresses

IP, SP, BP, SI, DI - Offset Registers

Contains Index Value for Memory Address
IP, Instruction Pointer
Used to point to Instructions
Determines a Memory Address (along with CS)
Segmented Address written as CS:IP

SI, Source Index;

DI, Destination Index

Used to point to Data

Determines Memory Address (along with other registers)
DS, ES commonly used

SP, Stack Pointer;

BP, Base Pointer

Used to point to Data in Stack Structure (LIFO)

Used with SP or BP
SS:SP or SP:BP are valid Segment Addresses

These can also be used as General Registers !!!!!!

8086/8088 Register File (cont)

Flags Register
15

x OF DF IF TF SF ZF x AF x PF x CF

Status and Control Bits Maintained in Flags Register

Generally Set and Tested Individually

9 1-bit flags in 8086; 7 are unused

Status Flags
Indicate Current Processor Status
CF
OF
ZF

Carry Flag
Overflow Flag
Zero Flag

SF

Sign Flag

PF

Parity Flag

Arithmetic Carry
Arithmetic Overflow
Zero Result; Equal
Compare
Negative Result; NonEqual Compare
Even Number of 1 bits

AF

Auxiliary Carry

Used with BCD

Arithmetic

Control Flags
Influence the 8086 During Execution Phase
DF:

Direction Flag

Increment/Decrement

used for string operations

IF: Interrupt Flag

Enables Interrupts

allows fetch-execute to be interrupted

TF Trap Flag

Allows Single-Step

for debugging; causes interrupt after each op

MOV AH,[SI]

8086 Segmented Memory

x86 Memory Partitioned into Segments
8086: maximum size is 64K (16-bit index reg.)
8086: can have 4 active segments (CS, SS, DS, ES)
8086: 2-data; 1-code; 1-stack
x386: maximum size is 4GB (32-bit index reg.)
x386: can have 6 active segments (4-data; FS, GS)
Why have segmented memory ????????
Other microprocessors could only address 64K since they
only had a single 16-bit MemAddrReg (or smaller).
Segments allowed computers to be built that could use more
than 64K memory (but not all at the same time).

8086/8088 Memory Access Registers

15

Code Segment
Data Segment
Stack Segment
Extra Segment

CS
DS
SS
ES
15

Instruction Pointer
Stack Pointer
Base Pointer
Source Index
Destination Index

IP
SP
BP
SI
DI

}
}

8086 Generating Physical Addresses

CS

Memory System
Address Lines

ES
SS
DS

19

0
Physical Address

Dedicated Segment Registers

ADD
15

0
Index Reg.

15
Segment Reg.

BP

0
0000

DI
SI
SP

Portion of BIU Circuitry

IP

Dedicated Index Registers

Segmented Addressing

Each Segment must begin at Paragraph Boundary

physical address

memory

CS
ES
SS

00000h

paragraph 1

DS

00010h

paragraph 2
00020h

paragraph 3

BP
DI
SI

Each paragraph has phys. address that is multiple of 10h

BIU is responsible for appending 0000 to Segment
only need 16-bit segment registers

SP
IP

Segmented Memory (x86 Style)

FFFFFh

Segment Registers:
Point to Base Address
Index Registers:
Contain Offset Value
fragmentation
Notation (Segmented Address):

Code
Segment

Segment
Registers
CS

Extra
Segment

ES
SS

DS

Stack
Segment

Data
Segment

00000h

System
Memory

CS:IP
DS:SI
ES:DI
SS:BP
SS:SP

Memory Storage Organization

Organized as SEGMENTS
Maximum segment size = 64KB
(Since 16 bit offsets: 216 = 65,535 = 64KB)

Maximum Memory Size:

220 = 1,048,576 = 1MB
Newer Processors (Pentium) Can Utilize More Memory
Wider Address Registers 32 bits
232 = 4,294,967,296 = 4GB

Segmented Memory Example

FFFFFh

Logical, Segmented Address:

0FE6:012Bh
Offset, Index Address:
012Bh
Physical Address:
0FE60h 65120
+ 012Bh
299
0FF8Bh 65149

Code
Segment

Segment
Registers
CS

Extra
Segment

ES
SS

DS

Stack
Segment

Data
Segment

00000h

System
Memory

Segmented Memory Aliasing

Logical, Segmented Address 1:
DS:SI = 1234:4321
Physical Address:
12340h 74560
+ 4321h 17185
16661h 91745
Logical, Segmented Address 2:
ES:DI = 1665:0011
Physical Address:
16650h 91728
+ 0011h 00017
16661h 91745

Segment Locations in Physical Memory

 1 Word = 16 bits
Byte Addressable
Little Endian Arrangement
MSB (Most Significant Byte) at Higher Address
072CH

18H

AD5FCH

072BH

A3H

AD5FBH

072AH

7EH

AD5FAH

0729H

69H

AD5F9H

0728H

AAH

AD5F8H

0727H

2EH

AD5F7H

0726H

00H

AD5F6H

0725H

55H

AD5F5H

0724H

02H

AD5F4H

0723H

72H

AD5F3H

0722H

11H

AD5F2H

0724H
0H
0000

Base Address = ACEDH

Logical Address = 0724H
Physical Address
= ACED0H + 0724H
= AD5F4H
M[ACED:0724]
= M[AD5F4]
= 5502H
0725H

2H
0010

5H
0101

5H
0101

hex
binary

072CH

18H

AD5FCH

072BH

A3H

AD5FBH

072AH

7EH

AD5FAH

0729H

69H

AD5F9H

0728H

AAH

AD5F8H

0727H

2EH

AD5F7H

0726H

00H

AD5F6H

0725H

02H

AD5F5H

0724H

55H

AD5F4H

0723H

11H

AD5F3H

0722H

20H

AD5F2H

0721H

72H

AD5F1H

0720H

DEH

AD5F0H

071FH

ADH

AD5EFH

071EH

FAH

AD5EEH

071DH

CEH

AD5EDH

071CH

CAH

AD5ECH

FEH

Assume:
M[DS:DI] Contains a Pointer Value
DS = AD5Fh; DI = 0005h
(All Segments Start on Paragraph Boundary)
SI M[DS:DI]
Then:
Pointer is

M[DS:DI] = M[AD5F:0005]
= M[AD5F5] = 0002h
M[DS:SI] = M[DS:(DS:DI)] = M[DS:0002h]
= M[AD5F:0002] = M[AD5F2] = 1120h

Default Segment/Index Pairs

Type of Memory Reference

Instruction Fetch
Stack Operation
Variable (except following)
- String Source
- String Destination
- BP used as Base Register
- BX Used as Base Register

Default Segment Base

CS
SS
DS
DS
ES
SS
DS

Alternate Segment Base

Offset
None
IP
None
SP
CS, ES. SS
Effective Address
CS, ES, SS
SI
None
DI
CS, DS, ES
Effective Address
CS, ES, SS
Effective Address

Homework:
Give several exercises

Keypoints