Software Radio

High-speed ADC combines with FPGA to

enable single-slot SDR solutions
The software-dened radio (SDR) concept has enabled designers to reinvigorate classical
designs in a compact form. One of the areas where SDR-based designs have immense
advantage is in the development of multichannel receivers. This article describes an example
implementation that can handle an FM bandwidth of 300 kHz having a 40 kHz message
bandwidth and 105 kHz FM deviation. The implementation presented easily handles a wide
range of applications including sonobuoy and tactical communication applications.
By Angsuman Rudra and Alexis Bose

Classic designs are being migrated to SDR-based implementation, and requirements for recongurability, space and size reduction
are becoming crucial. SDR offers the most benet in multichannel
scenarios where high-speed signal-processing modules can process
multiple channels without duplication of expensive processing modules. FPGAs are also playing a signicant role for baseband processing and offer recongurability and space saving that is crucial for a
variety of applications. This multichannel receiver can be used as, for
example, a sonobuoy receiver, a tactical communication receiver or a
next-generation wireless communication receiver. The FPGA-based
implementation allows the user to recongure the same hardware into

System description

The entire multichannel receiver can be delivered in a single-slot

implementation with capacity to spare as shown in Figure 1. The singleslot receiver comprises two PMC modules: a high-speed ADC module
with 16 digital downconverters (DDC) [ICS-554] and a FPGA-based
PMC module [ICS-1580]. The ICS-554 allows the user to digitize up
to four IF signals and digitally tune up to 16 frequency-division multiplexed (FDM) channels. The DDCs in the ICS-554 are programmed
for a decimation factor of 64, which produces a complex output data
rate of 1.5625 Msamples/s at a 100 MHz ADC sampling rate. Note
that the data rate is four times higher than the Nyquist data rate of
390 ksamples/s (complex) for a 300 kHz RF bandwidth. These FDM
channels (FM-modulated complex baseband signal) are then sent to
the ICS-1580 module for FM demodulation (Figure 2). For ease of
implementation, the 16-channel FM demodulator is implemented as
two eight-channel demodulators.
The FM demodulation process can be characterized as:
m(t) = d()/dt, where phi is the phase of the received signal.
With a complex baseband representation (I, Q), = atan(Q/I).
Substituting this in the equation above and expanding out d(atan(Q/I)),
the baseband message signal may be recovered as:
(I*dQ QdI)/(I^2 + Q^2).
This is the heart of the FM demodulation function implemented in
FPGA as shown in Figure 3. The automatic scaling function ensures
that the output of the divider is a full-scale 16-bit number. This produces near full-scale baseband output for a wide range of RF signal
power, in effect implementing a digital automatic gain control (AGC)
functionality. The various settings are summarized in Table 1.

ADC 1

ADC 4

DDC 1

DDC 16

PMC: ICS-554

FPGA
8-ch FM
demod
8-ch FM
demod

PCI interface

Market needs

multiple proles, resulting in signicant space savings for multimode

applications. Moreover, logistics support and spare parts inventory
are greatly reduced.

Data format

igh-speed analog to digital converters (ADC) and large eldprogrammable gate arrays (FPGA) have allowed designers to
design compact solutions that were unthinkable a few years ago.
This article discusses how a 16-channel frequency modulation (FM)
demodulator operating in the intermediate frequency (IF) region may
be implemented in a single slot, and builds on two articles previously
published in RF Design[1,2]. The system implemented here is capable
of digitally tuning to 16 separate FM bands, downconverting the signal
to produce complex baseband outputs and performing a multichannel
FM demodulation in a FPGA core.
This article describes an example implementation that can handle an
FM bandwidth of 300 kHz. This supports an FM with 40 kHz message
bandwidth and 105 kHz FM deviation. The implementation presented
here easily handles a wide range of applications including sonobuoy
and tactical communication applications. The 16-channel demodulator
is implemented in a modular fashion as two eight-channel demodulator
blocks. The eight-channel FM demodulator uses less than than 4700
slices, seven 18 x 18 multipliers and 16 18 kbit random access memory
(RAM) blocks found in a Xilinx FPGA[3].

Data format

PMC: ICS-1580
To host

Figure 1. Multichannel IF receiver in a single slot.

46

Figure 2. A 16-channel FM demodulator describes the system block

diagram.

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April 2006

I*dQ - Q*dI
I

16

16

I +Q
2

2 n (I*dQ - Q*dI)

32

32

Automatic scaling

Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8

32

32
2 (-m) * (I 2 + Q 2 )

16

Decimate by 16,
361-tap MAC
FIR (8-ch)

1.5625
Msps/ch
97.65 ksps/ch
x 8 channels

16

To PCI interface
Figure 3. An eight-channel FM demodulator module implemented in FPGA.

Output Data Rate

ADC Sampling Rate

100 MHz

DDC Decimation Factor

64

DDC Programmable Filter

17%

DDC RF Bandwidth

265 kHz

1.5625 Msamples/s
(complex)

Digital Phase Discriminator

1.5625 Msamples/s per

channel (real)

Decimating MAC FIR Filter

(Decimation = 16)

97.65 ksamples/s
(real) per channel

Table 1. Summary of the settings.

A detailed description of the hardware used and the various

functional blocks programmed in the FPGA follows.

Hardware modules

The ICS-554 and the ICS-1580 PMC modules that enable the build
up of the system are described here.
ICS-554. A four-input high-speed ADC card capable of
sampling at rates up to 105 MHz. Up to 16 onboard narrowband
digital tuners enable users to implement a compact multichannel
receiver solution. The maximum bandwidth per channel is 2.5 MHz
for the 16 narrowband channels. Multiple channels may be combined
to provide up to four channels at 10 MHz each. The onboard DDCs
allow the user to digitally downconvert the signal and reduce the
effective data rate for each channel. Digital tuning is achieved by
writing a tuning word for the numerically controlled oscillator
(NCO). Digital retuning is thus an extremely fast process and enables
the receiver to serve as a very fast frequency-hopped system. More
information regarding the ICS-554 is available from[4].
ICS-1580. A PMC module with a Virtex-II Pro device
(XC2VP70). The FPGA is directly connected to 64 Mbytes of
synchronous dynamic random access memory (SDRAM) arranged
as four independent banks and 16 Mbytes of QDR-II SRAM arranged
as four independent banks. Four multi-Gigabit Tx/Rx links from
the FPGA are available on the front panel and enable high-speed
data movement in a multiboard scenario. This would allow multiple
ICS-1580s to be interconnected to increase effective FPGA resources.
The 64 user I/O lines of the PMC module are also connected to
the FPGA and are used to transfer data from the ICS-554 to this module.
More information regarding the ICS-554 is available from[5].

Digital phase discriminator

This block is the heart of the FM demodulation process and is

implementing the differentiation of the phase of the received signal.
The DDCs produce a complex baseband (I,Q) representation of the
received signal. The implementation of the (I*dQ QdI)/(I^2 + Q^2)
is carried out in two steps. In the rst step, the numerator (I*dQ QdI)
and the denominator (I^2 + Q^2) are rst computed. The differentiation

48

function is approximated by the difference operator. Thus:

dI = I(n) I(n-1) & dQ = Q(n) Q(n-1). After algebraic manipulation the numerator becomes:
I(n-1) * Q(n) I(n) * Q (n-1).
The denominator is calculated in a straightforward fashion. The
multipliers are implemented using the 18 x 18 hardware multipliers available in the Xilinx FPGA. The division is performed using
a Xilinx LogiCORE divider block. The availability of dividers that
can be easily and economically implemented in a FPGA has made
possible implementation of a much wider variety of DSP algorithms
in FPGA. A xed point divider is implemented in this example.
The design targets a system with approximately 300 kHz RF
bandwidth with about 40 kHz baseband signal bandwidth. Thus,
an FM system with 105 kHz frequency deviation and 40 kHz message
bandwidth will be easily accommodated as the bandwidth of such
a system is about 290 kHz (= 2*(105+40)). The Nyquist data rate
for carrying this bandwidth is about 390 ksamples/s (complex), which
translates to a DDC decimation of 256 at a 100 MHz sampling rate.
However, at this reduced sampling rate, the approximation of the
differentiation reduces the distortion performance. To alleviate the
problem, a 4x oversampling ratio has been selected as compared with
the Nyquist rate.

Baseband lter

The output of the phase discriminator is the baseband message

signal (40 kHz bandwidth in this example). However, the output
data rate is about 1.56 MHz, which is much more than required.
Having a very high data rate causes an undue burden on the host
system, which has to transfer and process the data. To reduce the
data rate, a decimating multiply-accumulate (MAC) low-pass nite
impulse response (FIR) lter is used. The decimation factor for the
FIR is chosen to be 16, which produces a baseband data rate of
97.65 kHz, sufcient to handle the message bandwidth of 40 kHz.
The low-pass FIR has a passband of 42 kHz and a stopband of
48 kHz. As the input data rate (1.56 Msamples/s per channel) is
signicantly lower than the 100 MHz clock used in the FPGA
fabric, multichannel operation is possible without consuming
additional FPGA resources.

FPGA implementation and occupancy

FM systems are typically narrowband applications. This allows

multichannel implementation in relatively small FPGAs. FPGAs
typically run at very high speed. In the example shown here, the
FPGA was a Xilinx Virtex II Pro device (XCV2P70) running at
100 MHz. The relative occupancy is shown in Table 2.
The compact design is achieved by running the FPGA at a much
higher frequency than the input data rate. Thus, the same resources
(multipliers, slices, etc.) may be used to process multiple channels.
This allows the developer to implement additional functionality in the
design. Other FPGAs are now available that run at faster clock rates
enabling more functionality to be packed in the same device.

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April 2006

Used in 8-ch
FM demod

Percent Used

33,088

4700

14.2%

18 x 18 Multiplier

328

2.1%

18 kbit Block RAM

328

16

4.9%

Table. 2 Relative occupancy.

Multichannel IF receiver
Signal generator

-10
-20
-30
-40
-50
-60

PCI

FM at 21.4 MHz
105 kHz deviation
8 kHz message

FFT (Flattop Window) of Demod Signal

Amplitude (dB)

Slices

Total Available

-70
-80
0

Demod data
analysis (off-line)

10

15

20 25 30 35
Frequency (kHz)

40

45

50

Figure 5. Spectrum of the demodulated signal with IF input at 10 dB full

scale (dBFS) at the ADC.

Figure 4. Test setup for characterizing the system.

Distortion reduction

Performance characterization

The test setup used to characterize the multichannel receiver

is shown in Figure 4. The FM demod data is collected and a FFT
(using a at-top window) is used to analyze the performance.
Figure 5 and Figure 6 show the performance at two input levels:
-10 dB and -20 dB below the full scale of the ADC input. The ADC
full-scale value is about 5 dBm. It can be seen from the plots that
the demodulated output signal level is preserved. The estimated
SINAD for the -10 dBFS input case (Figure 5) is 28.0 dB, while that
for the -20 dBFS input case is 23.2 dB.

-10
-20
Amplitude (dB)

The approximation dQ = Q(n) Q(n-1) causes non-linear distortion.

A simple way has been used to reduce the distortion by oversampling
as described earlier. The higher complex baseband output data rate
from the DDCs allows greater granularity in the differentiation,
reducing the distortion. Software-based oating-point implementation
has shown that 4x oversampling (as compared with the Nyquist rate)
reduces the harmonic distortions by about 30 dB (compared to the
case when the outputs are at the Nyquist rate). Additional improvements
may be obtained with a higher oversampling factor.

FFT (Flattop Window) of Demod Signal

-30
-40
-50
-60
-70
-80
0

10

15

20 25 30 35
Frequency (kHz)

40

45

50

Figure 6. Spectrum of the demodulated signal with IF input at 20 dB full

scale (dBFS) at the ADC.

Conclusion

This article describes a single-slot multichannel receiver that is

ideal for multimode SDR-based recongurable solutions. As an
example, a multichannel FM demodulator core has been implemented
with extremely low FPGA resource utilization demonstrating the
power of todays high-speed FPGA devices in communications
systems. RFD

References

1. RF Design, May 2004, FPGA-based Application for Software

Radio, Angsuman Rudra.
2. RF Design, July 2003, Multichannel Multiband VHF Software
Radio-based Receiver Eliminates RF Downconversion, Angsuman
Rudra.
3. Xilinx Virtex-II Pro Data Sheet (www.xilinx.com).
4. Tech Note No. 45: ICS-554 4-Channel, 105 MHz ADC PMC
Module with DDCs, Xilinx FPGA and PCI 64/66 Interface (http://
www.ics-ltd.com/TechNotes.cfm).
5. Tech Note No. 54: The ICS-1580 FPGA DSP Board with
High-Speed Inputs in PMC Format, (http://www.ics-ltd.com/TechNotes.cfm).

50

ABOUT THE AUTHORS

Angsuman Rudra obtained a B. Tech degree from IIT
Kharagpur in India in 1992, a Masters degree in Electronics
and Electrical Communications Engineering from Carleton
University in 1996, and an MBA from the University of
Ottawa in 2001. Previously with Nortel, he joined ICS
Sensor Processing in 2001, where he is currently director,
systems. He is a Professional Engineer in the state of Ontario
and a member of IEEE.
Alexis Bose holds a BASc in Systems Design Engineering
from the University of Waterloo. He has five years of
experience in software and hardware systems related to
communications, biomedical and defense. He joined ICS
Sensor Processing in 2003 as an FPGA systems engineer,
and has worked on numerous software-dened radio and
radar projects.

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April 2006