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Functional verification
Marcin Kazmierczak
SwitchCore AB

SwitchCore today
Fab-less semiconductor company
Develops integrated switching devices with advanced
QoS functionality for the gigabit Ethernet market.
In-house back-end and full-custom design
85 employees
Offices in Lund, Stockholm, San Jose, Boston and
Singapore

Design flow
Specification

RTL-Design

Block-level

Top-level

Simulations

Regression

Synthesis

Floorplanning

Regression
Layout

Tests netlist

Static Timing
Analysis

DRC

Tape Out

Verification Flow
Specification

Verification Plan

Beh
TB

Ext sim

RTL coding
TC

RTL debug

Why verify?

Check that the design meets the specification

Standards
Bugs cause re-spin
Cost
Time

Cost of bug
Block design
Chip simulation
More debug
May require change in algorithm

Silicon in lab
Most often requires new tape-out
Expensive

At customer environment
Very expensive
Reputation
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Functional simulation

Simulate
Stimulate a device from its inputs
Monitor outputs for expected behaviour
Show that the DUT works correctly for all valid
combinations of inputs

DUT

Testbench environment
Software based simulation environment
Resembles hardware lab
Pattern generators
Logic analyzers

Bus-functional models
Harness

Testbench environment
Testcases

Engine (Scoreboard, Parser)

Harness
BFM

BFM

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DUT

BFM

Bus-functional models

Interfaces with DUT

Raises level of abstraction
Easier debug
Encapsulation
Protocol checking
Error-injection
Reuse

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sendFrame (N, Size)

setParam (N, VAL)
setCOL (VAL)

PHY

Testcases

Direct testcases
Test isolated function
Automated result
Language
Calls high-level routines in
testbench

Stimuli

Expected
output

PASS
FAIL

TB ENGINE

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Verification plan

General specification
Features
Definition of testcases
Conformance test plan
Specification of environment
Allocation of resources
Goals
Difficult to plan all activities
Block-level verification plan
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Behavioural model
External functionality
High-level software
constructs
Keep it simple
Shorter development time
Faster simulations
Debug testcases
Archictectural issues
Differences from RTL
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BEH
BFM

BFM
RTL

Regression

Test suite
Automation
Run on regular basis
Verify added functionality
Check that nothing already verified is broken
Repeatable

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Observability
Propagation
Detection

DUT

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Controllability
Triggering an error condition
Coverage

DUT

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Code coverage

Statement
Branch
Path
Quality measure of test suite
Deficiencies?
Hardware concurrency

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Functional coverage
State machine
States
Transitions

Transactions
CPU interfaces

Sequences
Frames
Cpu accesses

Combinations

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Extended verification
Testplan
Basic sanity
Functions
Stress

Fill coverage holes

Random simulation
When are we done?

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Random simulation

Stress the device (realistic environment)

Internal interactions
Hit corner-case
Requires more advanced environment
Parameters
Error-injection
Repeatable
Run-time

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Random simulation
Requirements on verification environment
constraints
seed

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Random
parameters

BFM

Expected
result

BFM

DUT

BFM

PASS ?
FAIL ?

Generation
Bus-functional models
Higher-level of abstraction
Identification
Sequence numbers

Coverage
Frame types
Sequences

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Checking
Protocol checkers
Bus-functional models
Standards

Protocol violation

BFM

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DUT

BFM

Checking
Scoreboard

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Transfer function
Expected data
Comparison function
Identification
On-the-fly checking
Difficulties?

Scoreboard

BFM

Match/Comparison

DUT

BFM

Parsing
Testcases written in proprietary format (SwitchCore)
Easy to change and re-run
Pre-processing of testcases (Perl)

Testcase

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Pre-processor

Testfile

HDL Testbenches
HDLs (Verilog/VHDL) can be powerful with advanced
coding style
Known languages
But not efficient in testbench coding
Deficiencies
Non re-rentrant tasks in Verilog
No powerful primitives

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Specman/E

Powerful primitives
Functional Coverage Points
Randomization
Methodology
No upfront definition of testcases
Verisity (www.verisity.com)

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Functional Coverage Points

Generated stimuli
Frame types

State machines
Signals
Values

Transactions
Cpu access

Sequence / Combination of events

Crossing coverage points
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Vera

Verilog based
Object-oriented
Randomization functions
Checking
Synopsis (www.synopsis.com)

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TestBuilder

C++
Class-library
Generation / checking
Open-source
Integration with NC-Verilog
Cadence (www.cadence.com)

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Formal Verification

Mathematical
Proof properties
Exhaustive
Size
Properties

Equivalence checking
netlist - netlist
RTL - netlist

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White-Box Verification

Assertions
Increase observability
Better coverage measure
Easier debug
Corner-cases
Used during RTL simulations
Error!

DUT

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Semi-Formal Verification

Increase controllability
Formally check if assertions can be violated
Used with assertions during RTL simulations
Not exhaustive
Zero-in (www.0-in.com)

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System simulation

Board level (several ASICs)

Interfaces
Interactions
Boundaries?
Simulation models
uP

PHY

NP

RAM
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IF

Emulation

System of FPGAs
Faster simulation
Software/Hardware co-verification
Difficulties
Generation
Checking

Longer iteration time

Size of design?
Very expensive
www.quickturn.com
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When are we done?

How do we know that we have checked everything?

Functions tested
Bug rate
Coverage
Very difficult question...

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Bugs
Bug tracking important
Categories
Minor
Respin
DOA (Dead-On-Arrival)

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SwitchCore

ModelSim
Simulation on RTL and netlist (with timing)
Netlist simulation are very slow
Static timing analysis more efficient in finding timing
issues

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SwitchCore

Block-level testbenches
Multi-block testbenches
Top-level testbench
Regression suite
Random tests

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Experience

Multi-block testbenches
Designer should not verify own block
Random tests important
ASIC general specification
Planning / Goals
Clean interfaces between blocks
Bug tracking important
Release management
Difficult to plan debugging time
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Future

Random simulation
Testcase generation
Closed-loop random generation
Formal methods
Hybrid methods (e.g. Semi-formal)
Less RTL coding
Verification more and more important

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