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VLSI DESIGN
OBJECTIVE QUESTION BANK
ACADEMIC YEAR -2014-2015
Prepared By:
Mr. M. RAMAKRISHNA, Assoc. Professor, ECE
Mr. D.RAVIKRAN BABU, Assoc. Professor, ECE
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VLSI DESIGN: Prepared by M.Ramakrishna
VLSI DESIGN
OBJECTIVE QUESTION BANK
UNIT I: INTRODUCTION
1. The approximate number of transistors per VLSI chip in commercial products
a. 100-1000
b.1000-20,000
c.20,000 -1,000,000
d. 1,000,000-10,000,000
b. Polymerization
d. self aligning
6. The buried n+ sub collector is added to the n-well CMOS transistor to provide
a. Emitter region
b. Reduce the output drive current
c. Reduce the n-well collector resistance
d. Base region
d. Aluminum layer
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VLSI DESIGN: Prepared by M.Ramakrishna
b. MW-sec
c. PJ
d. Joules
b. -0.2VDD
c. 0.8VDD
d. -0.8VDD
b. BICMOS
c. GaAs
d. ECL
b) doping control
d) decreasing substrate doping level
b) copper
c) silver
d)tungsten
b) Ge
c) SiO2
d) AlO2
b) Amorphous
c) Poly crystalline
d) None
b) Metal-Silicon
c) Metal-Ge
d) Metal-SiO2
b) Oxidation
c) Photolithography
d) Encapsulation
c) Latch up immunity
a) Poly silicon
b) Si
d) Al
d) None
22.
c) Cu
b) Saturation
c) cut-off
d) linear
The drain current flow in ideally independent of drain-source voltage when channel is
a) Strongly depleted b) Weakly depleted c) strongly inverted d) Weakly inverted
23. -------------- Process is used to transfer the layout pattern from masks to wafer.
a) Diffusion
b) Isolation
c) Photolithographic
d) Metallization
24. According to Moores law, the number of transistors that could be manufactured on a chip
a) Linearly decreases
c) Grows linearly
b) Grows exponentially
d) Decreases exponentially
d) 1 m
30. The Fermi potential value for typical p-type silicon substrate is
a) 0.6V
b) 0.35V
c) -0.35V
31. Accumulation mode of MOS transistor is
a) Vgs=Vt
b) Vgs>Vt
c)Vgs<Vt
32. The effective gate voltage is Vg=Vgs-Vt(Vgs<Vt)
a) high current flows b) no current flows c) low current flows
33. In enhancement mode devices Vt, Vdd values are respectively
a) 5V, 1V
b) -5V, -1V
c) 1V, 5V
d ) CGS
d)-0.6V
d) none
d) none
d) -1V, 5V
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VLSI DESIGN: Prepared by M.Ramakrishna
34. In NMOS fabrication, on the hole chip metal (aluminum) has deposited over its surface to a
thickness is
a) 2um
b) 1m
c) 0.5um
35. In well process, to achieve low threshold voltages(0.6V and 0.1V)
a) high doping
b) low doping
c) deep well diffusion
36. The process technology presently used in chip design is
a) NMOS
b) PMOS
c) BiCMOS
37. In present CMOS technology the type of gate used is
a) Poly Silicon
b) Aluminum
c) copper
38. Common dielectric is used for isolation of devices is
a) Silica
b) silicon dioxide
c) wood
39. The second most abundant element available on the earth is
a) Silicon
b) Aluminum
c) graphite
d) 5um
d) none
d) CMOS
d) Gold
d) graphite
d) ferrous
40. The plasma orientation of the wafer which produces electrically cleaner oxide interface is
a) <100>
b) <110>
c) <111>
d) <000>
d) none
42. _____ Law describes the epitaxial growth of integrated circuit complexity
a) Lenzs law
b) nyquists
c) faradays
d) Moores
43. VLSI is meant by the term as a Device has containing between_______________ transistors.
a) 103 and 105
b) 105 and 107
c) 107 and 109
d) 109 and 1011
44. Thermal oxidation process is carried out at ____ 0C temperature range.
a) 100-200
b) 400-600
c) 900-1200
d) 1300-1600
45. _____ is the best method for controlling the selective dopants in to the silicon crystal wafer.
a) epitaxial
b) diffusion
c) ion implantation d) all
46. ICs made by sputting materials on ceramic substrate are called
a) Thin film IC
b) Hybrid IC
c) Monolithic IC
d) Thick Film IC
47. MOS ICs
a) consume more power
b) occupy less space than BJT
c) low input capacitance
d) having high speed
48. Epitaxial layer growth in IC
a) May be on n-type
b) may be on p-type
c) Involves growth from gas phase d) involves growth from liquid phase
49. The most important reason for use of ICs is
a) High reliability
b) low power consumption
c) simple circuit design
d) low cost
50. According to Moores law, the number of components doubles in every _____ months
a) 10
b) 20
c) 22
d) 18
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VLSI DESIGN: Prepared by M.Ramakrishna
(T / F )
(T / F )
(T/ F )
73. In Bi-CMOS, the logical approach is to use MOS switches to perform the logic function
(T / F )
74. In BiCMOS technology, the n-well resistance is reduced by using _________
75. Through-hole mounting is used in ________________ package
76. Metallization is done for fabricating
77. Dry etching is also known as____________
78. the mask is often known as________
79. Bipolar device has__________
80. Working of MOSFET depends on___________
81. Dual inline package is sometimes called as _________ package.
82. Photolithography is done in________________.
83. The type of silicon required to fabricate IC is____________
84. Etching is done to remove ________areas to the semiconductor surface
85. Photo resist is used in lithographic process to transfer patterns from _____to the________
86. Advantages on silicon on insulator _______ process is absence of latch up problem
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VLSI DESIGN: Prepared by M.Ramakrishna
ANSWERS-UNIT-I
1. c
2. b
3. b
4. d
5. b
6. c
7. d
8. c
9. c
10. b
11. d
12. b
13. a
14. c
15. c
16. a
17. c
18. c
19. a
20. a
21. b
22. c
23. c
24. c
25. a
26. b
27. d
28. d
29. d
30. b
31. c
32. b
33. c
34. b
35. c
36. d
6/62
37. a
38. b
39. a
40. a
41. b
42. d
43. c
44. c
45. c
46. a
47. b
48. c
49. a
50. d
51. Chemical Vapour Deposition
52. Electron
53. Deal and groover model
54. Zero
55. Vss , Vdd
56. Bipolar
57. Limited load driving capacity
58. ON
59. Faster
60. High
61. 0.1m
62. 0.2Vdd
63. Positive
64. Cg = C0 WL
65. Threshold voltage
66. 1m
67. Channel
68. True
69. True
70. False
71. True
72. False
73. False
74. Doping
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VLSI DESIGN: Prepared by M.Ramakrishna
c) Vds>vgs-vt
d) Vds<vt
2. For faster NMOS circuits, one would choose the following type of substrate
a) 110 Oriented n - type substrate
b) 100 oriented p - type substrate
c) 111Oriented p - type substrate
d)111 oriented n- type substrate
3. Pull-up to pull-down ratio for NMOS inverter driven by another NMOS inverter is
a) 4:4
b) 4:1
c)1:4
d) 8:1
4. The following device is less likely to suffer latch-up
a) NMOS
b) CMOS
c) Bi-CMOS
d) PMOS
5. In CMOS inverter if n=p &if Vtn=Vtp, then the logic levels are disposed about at a
point
where
a)VIN=Vout=0.1VIN
b)VIN=0.5 VDD
c) VIN=Vout=0.5VDD
d) VIN=Vout=VDD
6. The figure of merit of MOS transistor can be expressed as
a) gmCg
b) Cg/gm
c) gm /Cg
d) gm + Cg
7. Typical mobility of holes(Bulk) is
a) 650cm2/V.sec
b) 240 cm2/V.sec
c) 1250 cm2/V.sec
d)
480
cm2/V.sec
8. Pick up the true statement with respect to Bi-CMOS Inverter
a) Low input impedance
b) High output impedance
c) High noise margin
d) Low driving capability
9. To achieve best performance NMOS inverter transfer characteristics, Zpu/Zpd ratio
should be
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VLSI DESIGN: Prepared by M.Ramakrishna
a) Zero
possible
b) One
c) As low as possible
d) As high as
10. Number of transistors to implement three-input AND gate using pass transistor logic is
a) 6
b) 3
c) 5
d) 9
11. In the MOSFET, as width of channel increases Id
a) Increases
b) decreases
c) Constant
d) none
d) Parasitic C
b) Parasitic BJTs
d) all
c) Domino
d) all
4) none
d) none
19. The expression for drain to source current in non-saturated region for enhancement
MOS device is
20. The charge per unit area in the depletion layer beneath the oxide QB is
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VLSI DESIGN: Prepared by M.Ramakrishna
21. . The transit time of electrons will flow from source to drain is
d)
Low
and
c)Vgs=Vt
d) Vgs*Vt
27. For depletion mode devices the channel is established because of the implant even
when
a) Vgs=0
b) Vgs=Vdd
c) Vgs=Vdd/2
d) Vgs=Vt
28. An inverter driven through one or more pass transistors should have a Zp.d/Zp.u ratio
a a) 2:1
b) 4:1
c) 8:1
d) 16:1
29. An inverter driven directly from the output of another should have a Zp.u/Zp.d
a) 2:1
b) 4:1
c) 8:1
d) 16:1
30. In place of resistors ___are used
a) buffers
b) inverters
c) pass transistor
d) NAND gate
31. The inverter has _____input impedance and ________ output impedance
a) High, Low
b) Low, High
c) Low, Low
d) High, High
32. The ____ of electron mobility with electric field gives velocity
a) addition
b) product
c) subtraction
d) division
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VLSI DESIGN: Prepared by M.Ramakrishna
33. _____ is the input voltage of a CMOS inverter in which both PMOS and NMOS in
saturated region
a) Vdd
b) Vdd/2
c) Vdd/3
d) 2Vdd
34. In BiCMOS logic____ are used near output to drive currents
a) PMOS
b) NMOS
c) BJT
d) Resistor
35. Sub threshold operation of MOSFET is very much useful in _____
a) biomedical applications
b) memory
c) charge coupled devices
d) none
36. The main advantages of short channel devices is_____
a) its low power consumption
b) it has good output characteristics
c) it has good speed
d) it is easy to fabricate
37. The phenomenon in MOSFET like early effect in BJT is
a) body effect
b) hot carrier effect
c) channel length modulation
d) subthreshold conduction
38. Sub threshold operation occurs in_________
a) strong inversion region
b) weak inversion region
c) saturation region
d) cut-off region
39. The ON resistance of a MOSFET_______
a) linearly increases with Vgs
b) linearly decreases with Vgs
c) exponentially increases with Vgs
d) non-linearly decreases with Vgs
40. The threshold value of an enhancement NMOS transistor is
a) >0
b) <0
c) =0
d) none
41. Main advantage of depletion load NMOS inverter circuit over enhancement type
NMOS load is
a) fabrication process is easier b) sharp VTC transitions and better noise margins
c) less power dissipation
d) none of these
42. Which one is not second order effect?
a) body effect
48. Trans
conductance
of
MOS
transistor
(gm)
is
expressed
as
78. The charge induced is ________ on the gate to source voltage Vgs, then Ids is ___
on the both Vgs and Vds
79. In non-saturated region electric field Eds _________
80. The threshold voltage for the NMOS depletion mode device is________
81. The effective gate to channel voltage at the drain ,the current is fairly_______
82. In the aspects of MOS, increasing __________ cause the channel depleted of
charge carriers and thus_______ raised
83. The source of NMOS and PMOS in CMOS inverter always connected to____
84. A MOS transistor which has no conducting channel region at zero gate bias is
called__
85. Saturated load in the ___ inverter makes high output logic less by 1Vt
86. In the NMOS inverter configuration, the depletion mode device is called_____
87. In the NMOS depletion mode transistor dissipation is___________ when
Vin=logical 1
88. In pull-up (CMOS)_________________flows either for logical 0 or for logical 1
inputs.
89. In CMOS inverter(region 3) is the region in which the inverter exhibits gain and
both the transistors are in______
90. Advantages on silicon on insulator _______ process is absence of latch up problem
91. In linear region channel is formed and drain current_____ linearly when potential
is _______ between source and drain
92. The speed of CMOS is less when compared to other technologies due to
93. The state of NMOS and PMOS transistor in region 4 of Vin Vs Vout characteristics is
94. In CMOS _____&_____ are used
95. The transconductance ratio is ______
96. If n=p then the value of Wp is ______
97. Figure of Merit of MOS transistor is__________
98. CMOS has__________ dissipation than compared to bipolar and mos devices
99. ______load in the NMOS inverter makes HIGH OUTPUT logic less by 1Vt.
100.
If packaging density area and performance are the constraints, power
dissipation is
not a constraint, the technology preferred is_____________.
101.
The parameter which affects the propagation delay is ______.
102.
Advantages of Silicon on Insulator CMOS process is____________
103.
Working of MOSFET depends on_______.
104.
The width of the channel dependent on_____________.
105.
The ratio of gm/Cg gives __________
REFERENCES:
13/62
VLSI DESIGN: Prepared by M.Ramakrishna
ANSWERS-UNIT-II
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
c
b
b
c
c
c
d
c
c
b
b
b
a
b
a
b
a
c
4
3
3
c
4
d
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
b
a
a
c
b
b
a
b
b
c
a
c
c
b
d
a
b
a
a
8:1
Body effect
Less
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
(Vgs Vt)
faster
high, low
low
CMOS
Low
-0.6v negative
Drain current
Large
Threshold
voltage
Pass transistor
Increase
Latch up
Gate voltage
0.2v positive
4:1
1250
cm2/V.sec
Minimum
650cm2/V.sec
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VLSI DESIGN: Prepared by M.Ramakrishna
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
101.
102.
103.
104.
105.
Cg = C0 WL
Decreases
Drain current
Drain current
Vds/2
2 to 3 times
Vgs, Vt
Gate voltage
source
gm
gate voltage
dependent
,dependent
Eds=Vds/L
negative
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
constant
Vsb,Vt
GND,Vdd
enhancement
mode
BICMOS
Pull up
high
no
current
92.
High
93.
capacitance
Linear,
94.
Saturation
NMOS&PMO
95.
96.
flows
saturation
CMOS
Increases,
97.
Increases
100.
98.
99.
input
S
Ids/Vgs
2.5 Wn/Ln
gm/ Cg
low
static
power
saturation
NMOS
15/62
VLSI DESIGN: Prepared by M.Ramakrishna
(c) Blue
(d)
(c)3
(d)
(d) 1
d) Red
c) Red
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VLSI DESIGN: Prepared by M.Ramakrishna
c) Demarcation
d) 10
d)
13. The minimum separation between two metal-2 contacts in based design rules
is
a. 1
b. 2
c.3
d. 4
14. The gate delay is scaled by
a. 1/
b. /2
c. 1/
d.
b.
d.
Metal1
to
Connect
d.
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VLSI DESIGN: Prepared by M.Ramakrishna
d.
d)
d) None
b) NOR
c) NOT
d) None
a) NOT Gate
d) NOR
b) Transmission gate
c) NAND
29. The metal 2 to metal2 spacing in CMOS lambda based design rules is
a) 2
b) 3
c) 4
d)
30. Power speed product is scaled by
a) 1/2
b) 1/2
c) /2
d)
31. All of the following are used for making contacts b/w poly silicon and diffusion
in NMOS circuit, except
a) Buried contact
b) butting contact
c) Polysilicon to metal then metal to diffusion
d) none of these
32. The switching energy per gate is Eg______
a) 1/2
b) 1/2
c) /2
d)
c) /2
d)
d)1/
d) metal-1
38. In CMOS design style, the n-transistor are then placed____ the demarcation
line and thus close to____
a) below, Vdd
b) Above, Vss
c) Above, Vdd
d)
below, Vss
39. The minimum feature size on chip is 2um, then the value of is
a) 4
b) 2
c) 3
40.
41.
42.
d) 1
color.
43. The power and ground lines often called
44. The minimum width of metal 1 layer is
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VLSI DESIGN: Prepared by M.Ramakrishna
45.
46.
47.
48.
49.
50.
51.
notation
The minimum poly silicon width is___________
As fabrication technology improves, the heat sink size_
In CMOS design style, Demarcation line is shown by
The Scaling factor for gate oxide thickness is _______________
The feature size will scale down without changing design rules
52.
53.
False
Layers cannot join together where contacts are formed
True / False
To provide an interconnection pattern _____________ layer is used
True /
P+ mask
[
]
a. Black
p- well
[
]
b. Blue
p- diffusion
[
]
c. Yellow
Metal 2
[
]
d. Brown
VDD contact
[
]
e. Green
Carrier density in channel Qon is scaled by_____
The max operating frequency is scaled by ______
The parasitic capacitance is scaled by ______
In CMOs design style, diffusion paths must ____ the demarcation line
In CMOS design style, the Vss and Vdd contact crosses,one on the Vss line
for every_____n-transistor
64. In CMOS design style, the p-transistor are placed____ the demarcation line
and ___ Vdd
65. For nMOs design green is used for _____
66. The color of polysilicon ate is _______
67. For nMOS design, black is used for ______
68. In double metal MOS process rules, connected to the other layers using
69.
74.
REFERENCES:
1. Essentials of VLSI circuits and systems Kamran Eshraghian,
EshraghianDougles and A. Pucknell, PHI, 2005 Edition- CHAPTER 3 (pp: 5577).
2. CMOS VLSI Design- A circuits and systems perspective, Neil H.E Weste,
David Harris, Ayan Banerjee, pearson, 2009- CHAPTER 3 (pp: 83-90).
ANSWERS -UNIT-III
1. a
2. b
3. c
4. b
5. a
6. b
7. c
8. a
9. d
10. a
11. b
12. c
13. d
14. b
15. a
16. b
17. b
18. c
19. b
20. b
21. b
22. a
23. c
24. b
25. a
26. a
27. a
28. a
29. b
30. c
31. b
32. c
33. b
34. a
35. c
36. b
37. c
38. b
39. b
40. d
41. Metal
42. Stick diagram
43. Brown
44. Power range
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45. 3
46. MOS transistor
47. Local distribution, global
distribution
48. 2
49. Reduces
50. Dotted line
51. 1 /
52. True
53. False
54. Metal
55. c
56. d
57. e
58. b
59. a
60. 1
61. 2/
62. 1/
63. Not cross
64. Four
65. Above, Below
66. n-diffusion
67. Red
68. contact areas
69. Vias
70. Green, Yellow
71. Above
72. Below
73. Vdd and GND
74. Green or red
75. =1
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VLSI DESIGN: Prepared by M.Ramakrishna
a) 1/2
b)
d) 2/2
c)
b) 1.0X10 2pF/m2=
c) 0.1x10 4pF/m2
d) 0.1x10
2pF/m2
3. The rise time of CMOS inverters is
a)
(b)
(c)
d)
d) 15 to100
d) Fan-out
c) 0.128 ns
d) 0.064s
13. The sheet resistance of silicides layer compared to poly silicon layer is
a. Twice
b. High
c. Low
d. Same
14. The layer used to speed up the rise time of propagated signal edges is
a. Diffusion layer
b. Metal layer
c. Poly-silicon layer d. Silicide layer
15. The channel resistance of a simple n-type pass transistor has a channel length 2 and width 2
is
a. 104 ohm
b. 4 ohm
c.1 ohm
d.4 ohm
16. One of the following is used to drive large capacitive loads
a. N cascaded inverters
b. Small size inverter
c. High Zp.d and Zp.u
d. Small L:W
17. For a given area, the metal to poly-silicon capacitance is compared to metal to substrate
a. Lower
b. Higher
c. Same
d. Half
18. One of the following is used to drive large capacitive loads
a. super buffers
b. Buffers
c. Inverters
d. Super inverters
19. The sheet resistance of diffusion layer compared to poly silicon layer is
a. Twice
b. High
c. Low
d. Same
20. Standard value of
a) 0.0032nf
Cg =
b) 0.01 pf
c) 0.128 pf
d) 0.0023 nf
33. Pass transistor logic uses transistors as______to carry logic signals from one node to
another.
34. The two phases in dynamic CMOS are _______and__________
35. The unit of sheet resistance is___________________
36. The resistance of MOS layers depend on the_____________________________and
_o f the layer.
37. The delay unit T =_______________
38. The rise time and fall time are dependent on______________
39. For equal n and p geometries the rise time is equal to_____ times that of the fall
time
40. R s is independent of the area of the square
[true / false]
41. _____________is the time taken for a waveform to rise from 10% to 90% of its steady-state
value.
42. ___________is the time taken for a waveform to fall from 90% to 10% of its steady-state
value.
43. __________is the time difference between input transition (50%) and the 50% output level.
44. _________is the advantage of Domino logic
45. __________is disadvantages of Domino logic
46. Correct operation of a design must not be dependent on__________________
47. ______________ is used to reduce the number of transistors required to implement a given
logic information.
48. The problem of driving comparatively large capacitive loads arises when signals must be
propagated from the -----49. The inverter pair delay for inverter having 4:1 ratio is ____________
50. For __________ the value of fringing field capacitance can be of the same order as that of
the area capacitance
51. The inverter pair delay for CMOS is_______________.
52. The optimum value of width factor to drive large load in N-cascaded inverters is____.
REFERENCES:
1.Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A.
Pucknell, PHI, 2005 Edition- CHAPTER 4 (pp: 85-110).
ANSWERS -UNIT-IV
1. d
2. a
3. c
4. b
5. a
6. d
7. b
8. a
9. a
10. c
11. c
12. a
13. c
14. b
15. a
16. a
17. b
18. a
19. c
20. b
21. n2rc( )
22. silicide
23. 2.5
24. 0.4
25. High output driving capability
26. Frequency
27. Metal 1
b.
c.
d.
16
SNR
b.
Ratio of amplitudes
c.
regularity
d.
quality
logical operations
b.
test ability
c.
topological properties
d.
nature of architecture
4. Any bit shifted out at one end of data word will be shifted in at the other end of the word
is called
a.
end-around
b.
end-off
c.
end-less
d.
end-on
5. In the VLSI design the data and control signals of a shift register flow in
a.
b.
c.
both horizontally
d.
both vertically
a.
first level
b.
top level
c.
bottom level
d.
leaf-cell level
7. The larger system design must be partition into a sub systems design such that
a.
b.
complexity of interconnection
c.
maximum interdependence
d.
arbitarily chosen
interdependence
b.
complex interconnections
c.
regular structures
d.
standard cells
down-top
b.
top-down
c.
d.
hierarchy
b.
down-top design
c.
d.
11. Any general purpose n-bit shifter should be able to shift incoming data by up to number
of places are
a.
b.
2n
c.
n-1
d.
2n-1
b.
c.
d.
line switch
b.
c.
crossbar switch
d.
gate switch
cross-bar swith
b.
transmission gate
c.
bus interconncection
d.
pass transistors
b.
c.
d.
16. The number of basic cells required for an n-bit X n-bit multiplier is
a.
(3n+1)
b.
(3n+1)2n
c.
n2
d.
n(n-1)
Register
b.
adder
c.
control bus
d.
I/O port
18. Carry line in adder must be buffered after or before each adder element because
a.
b.
c.
d.
19. The ALU logical functions can be obtained by a suitable switching of the
a.
b.
c.
d.
20. To fast an arithmetic operations, the multipliers and dividers is to use architecture of
a.
parallel
b.
serial
c.
pipelined
d.
switched
height increases
b.
c.
d.
height reduces
b.
c.
d.
23. The parity information is passed from one cell to the next and is modified or not by a cell
depending on the state of the
a.
previous information
b.
output line
c.
input lines
d.
next information
24. The parity information (pi) passed from one cell to the next is modified when the input
line (Ai) is at the state of
a.
zero
b.
overline{A}i
c.
one
d.
25. When cells of parity generator are butted together (indicate false statement)
a.
b.
c.
d.
26. The two output signals of comparator remain at zero as long as the two bits being
compared are
a.
same
b.
zero
c.
one
d.
different
27. In the comparator the two inputs if A>B then the outputs are
a.
b.
c.
d.
28. In the comparator the two inputs if A<B then the outputs are
a.
b.
c.
d.
29. The width of n-bit comparator is_____ where w is the width of leaf cell
a.
nw
b. w
c. (n-1) w
d. n
b.
c.
d.
31. ONE/ZERO detection circuits for word width of less than 32 bits is the
a.
pseduo-nMOS OR gate
b.
c.
d.
nMOS OR gate
32. The delay from the last changing output to the ripple zero/one detector is a
a.
b.
variable delay
c.
d.
33. The speed that synchronous up/down counter can operate is determined by the
a.
b.
c.
delay of registers
d.
b.
c.
d.
b.
N2
c.
-log N
d.
delay
to
the
output
is
porportional
log N
b.
c.
d.
Decimal numbers
b.
binary numbers
c.
d.
octal numbers
b.
c.
d.
39. The clocking of each stage of ripple counter is carried out by the
a.
common clock
b.
c.
d.
master-slave flip-flop
to
(n+1)T
b. (2n+1)T
c. (2n-1)T
d. (n-1)T
Maximum
b. minimum
c. same
d. no
44.
Odd
b. even
c. both
d. zero
____is a logic circuit used to compare the magnitudes of two binary numbers.
3. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003- CHAPTER
12 (pp: 443-471).
ANSWERS-UNIT-V
1. d
2. c
3. c
4. a
5. a
6. d
7. a
8. d
9. b
10. a
11. c
12. b
13. c
14. d
15. b
16. d
17. b
18. a
19. a
20. c
21. b
22. b
23. c
24. c
25. d
26. a
27. b
28. c
29. a
30. c
31. c
32. a
33. a
34. b
35. d
36. a
37. b
38. a
39. b
40. b
41. a
42. c
43. c
44. Xor gate
45. Barrel shifter
46. Adder
47. Barrel shifter
48. a
49. c
50. d
51. Arithmetic, logic
a.
b.
c.
d.
SRAM
DRAM
ROM
d.
EPROM
(d) 10x32
(b) 16 words of 5 bits each
(d) 5 words of 16 bits each
24. When the power supply of a ROM is switched off, its contents
(a) Become all zeros (b) become all ones (c) remain intact (d) are unpredictable
25. A ROM of size M x N bits can store
(a) N words of M bits each
(c) M bits
(d)
N bits
1024 x 8 bits is
(a) 8 bits
(b) 10 bits
(c) 12 bits
(d) 16 bits
27. A ROM has a 16-bit address bus. The number of locations in this memory is
(a) 16 (b) 32 (c)
1024
(d) 65536
28. It is desired to have a 64 x 8 ROM. The ROMs available are of 16 x 4 size. The number of
ROMs required will be
(a) 8
(b) 6
(c) 4
(d) 2
29. Four ROM chips of 16 x 4 size have their address buses connected together. This system will
be of size
(a) 64x4
(b) 16x16
(c) 32 x 8
(d) 256x 1
32. To have a ROM of size of 16KB,the number of 1024*4 ROMs required is ______
33.
34.
A low power SRAM cell may be designed by using _______ inverter
35. In SRAM and Anti-fuse types of FPGA, switched connections are made between ______
36.
31.
lines.
Expand DRAM _________________________________.
_____memory examines data word and compares this data with internally stored data.
32.
33.
34.
35.
36.
____variables.
The various types of ROMs arc ___________,____________and___________
A 16 x 5 ROM contains____________________________ a decoder.
37.
38.
39.
of
ANSWERS-UNIT-VI
1. a
2. c
3. b
4. c
5. c
6. b
7. a
8. b
9. c
10. a
11. a
12. b
13. c
14. d
15. c
16. a
17. b
18. c
19. c
20. a
21. b
22. a
23. b
24. a
25. b
26. b
27. d
28. c
29. a
30. b
31. Non-Volatile
32. 32
33. Non volatile
34. Cmos
35. Address lines and word
lines
36. Dynamic Random Access
Memory
37. CAM
38. EPROM
39. UV Rays
40. 7
41. PROM, EPROM,
E2PROM
42. 4x16
43. Non Volatile memory
44. EPROM, E2PROM
45. PROM
2.
3.
4.
5.
6.
The PLA provides a systematic and regular way of implementing multiple output
functions of n variables in
a.
POS form
b.
SOP form
c.
complex form
d.
simple form
AND gate have n inputs and output OR gate must have P inputs
b.
AND gate have P inputs and output OR gate must have n inputs
c.
d.
AND
b.
OR
c.
AND-OR
d.
NOR
b.
c.
d.
FPGA
b.
CPCD
c.
standard cells
d.
PLA
AND/OR structure
b.
OR/AND structure
c.
NAND/NOR structure
d.
EX-OR/OR structure
7.
8.
9.
10.
11.
12.
13.
V X P X Z PLA represents as
a.
b.
c.
d.
To realize any finite state machine requirements, the PLA along with
a.
b.
c.
d.
b.
multi-output basis
c.
d.
The regularity of the PLA sturcture shows that both the AND and OR planes are
constructed from
a.
b.
c.
d.
b.
software language
c.
tabulation method
d.
behaviour of system
b.
c.
syntax
d.
b.
14.
15.
16.
17.
18.
c.
larger in size
d.
FPGA
b.
PLA
c.
standard cell
d.
PAL
fuse-based FPGA
b.
SRAM-FPGA
c.
EPROM-FPGA
d.
b.
c.
micro cells
d.
AND/OR array
b.
c.
d.
The following is a chip whose final logic sturcture is directly configured by the end user
a.
b.
19.
c.
d.
positive logic
b.
negative logic
c.
users logic
d.
fixed logic
20.
21.
22.
23.
24.
25.
26.
b.
c.
d.
b.
c.
d.
b.
memory cell
c.
multiplexer
d.
b.
c.
d.
Which part of the CPLD is programmed to pass the latched or unlatched, true or
complement output to the external output
a.
b.
OR gates of array
c.
I/O cell
d.
standard cell
A slew rate control in the I/O block of CPLD is used to make the rising and falling of the
output pulse
a.
zero
b.
one
c.
faster
d.
slow
J-K flip-Flop
27.
28.
29.
30.
31.
32.
b.
R-S Flip-Flop
c.
T-Flip-Flop
d.
D-Flip-Flop
CPLD devices are used for design modification because these are
a.
reprogrammable
b.
non programmable
c.
d.
non programmable
b.
programmable
c.
d.
the pins
b.
the logic
c.
d.
the function
b.
c.
d.
it is AND/OR array
< 10times
b.
c.
< 1000times
d.
> 1000times
logic O
b.
logic 1
c.
high impedance
d.
open
33.
34.
35.
36.
37.
38.
39.
b.
c.
d.
b.
c.
d.
internal wires
b.
c.
intra wires
d.
b.
c.
d.
Standard cell designs are less area efficient than a full custom design due to
a.
b.
c.
d.
Where the design is of a reduced cost and include size memories the preferable approach
is
a.
FPGA
b.
c.
standard cell
d.
full custom
equal height
b.
equal width
40.
41.
42.
43.
44.
45.
c.
variable height
d.
constant width
Logic gate are placed in rows of standard cells are interconnected using
a.
internal wires
b.
intra wire
c.
routing channel
d.
switch box
b.
c.
d.
b.
c.
d.
b.
c.
d.
number of inputs
b.
number of outputs
c.
active high
d.
presence of flip-flop
active high
b.
active low
c.
number of inputs
d.
number of outputs
46.
47.
48.
49.
50.
51.
52.
OR gate is used
b.
c.
d.
One approach that is becoming more popular and feasible is to model chips as collections
of
a.
standard cells
b.
no.of gates
c.
d.
b.
c.
d.
b.
c.
d.
b.
number of OR gates
c.
d.
D flip-flop
b.
T flip-flop
c.
J-K flip-flop
d.
R-S flip-flop
AND-OR logic
b.
AND-NOR logic
53.
54.
c.
AND-NAND logic
d.
NAND-OR logic
In order to realize a Boolean function with a combinational PAL device, the function
must be expressed in
a.
POS form
b.
SOP form
c.
Standard form
d.
complex form
When the PAL sequential device has a tristate buffer at the output stage then the type of
circuit implemented is
a.
sequential circuit
b.
product terms
c.
pos form
d.
55.
56.
combinational circuit
Different versions of PLDs are
a. PLA
b.PAL
c.PROM
d.All
c. Both
d.None
61.
61.
b. 16 and 32
c. 8 and 16
d. 12 and 24
62.
63.
65.
66.
FPGA based design has turn-around time ______ than ASIC based design
a. Less b. more
c. equal
d. more or less
Logic gate that used to measure the gate equalent/count in an IC is______
a. NOT gate
b. 2-input NAND Gate
c. 2-input NOR gate
d. 2-input XOR gate
PLA has
a. fixed OR plane followed by a programmable AND plane
b. programmable AND plane followed by fixed OR plane
c. fixed AND plane followed by programmable OR plane
d. programmable AND plane followed by Programmable OR plane
PAL has
a. fixed OR plane followed by a programmable AND plane
b. programmable AND plane followed by fixed OR plane
c. fixed AND plane followed by programmable OR plane
d. programmable AND plane followed by Programmable OR plane
In FPGA-based design, designers
a. design the layout and fabricate the IC
b. download the bit stream to program the device
c. both (a) and (b)
d. None
Different FPGA programming technologies are
a. antifuse b. SRAM
c. EPROM
d.all
LUT is used in
a.CPLD
b. FPGA
c. ASIC
d. SPLD
67.
69.
70.
71.
72.
73.
74.
76.
77.
78.
75.
d. CLB
[true / false]
[true/false]
[true/false]
79.
REFERENCES:
1.CMOS VLSI Design- A circuits and systems perspective, Neil H.E Weste, David Harris, Ayan
Banerjee, pearson, 2009- CHAPTER 10(pp: 407-443).
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003- CHAPTER
14 (pp: 558-564).
ANSWERS-UNIT-VII
1.
2.
3.
4.
5.
b
a
d
a
d
6. a
7. c
8. b
9. b
10. c
11. a
12. b
13. d
14. a
15. a
16. b
17. d
18. b
19. c
20. c
21. b
22. d
23. b
24. c
25. d
26. d
27. a
28. b
29. b
30. a
31. d
32. b
33. c
34. b
35. b
36. a
37. c
38. c
39. a
40. c
41. a
42. b
43. b
44. b
45. b
46. b
47. c
48. c
49. b
50. a
51. a
52. b
53. b
54. d
55. d
56. a
57. Application
Specific
Integrated
Circuit
7. A 20 bit counter is split into four five bit section, them the required steps for testing are
a.
25
b. four sets of 25
c. five sets of 24
d. five sets of 25
16. The two key concepts underlying all considerations for testability are
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VLSI DESIGN: Prepared by M.Ramakrishna
d. LFSR method
22. Self-test circuitry approach is based on
a. linear feedback shift registers only
b. linear feedback shift registers, exclusive-OR and clock system or gate
c. clock system only
d. inclusive OR gates only
23. The combination of LSSD scan path and linear feedback shift register is called
a. self test circuitry
b. signature analysis technique
c. structured testability
d. built-in logic block observation
24. In the following which one is correct with respect to BILBO testing for control inputs C 0=1,
C1=1
a. linear shift mode
b. signature analysis mode
c. data latch
d. reset mode
25. The control inputs in BILBO testing the corresponding mode is
a. linear shift mode
b. signature analysis mode
c. data latch
d. reset mode
26. In the BILBO arrangements, when C0=0, C1=1 then the corresponding mode is
a. linear shift mode
b. signature analysis mode
c. data latch
d. reset mode
27. The following the mode when C0=1, and C1=0 in the BILBO arrangement
a. linear shift mode
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VLSI DESIGN: Prepared by M.Ramakrishna
33. In order to reconfigure flip - flops appropriately, it is necessary to be able to include a double
throw switch in the
a. simple scan path
b. address path
c. control signal path
d. data path
34. The test access port or TAP controller in a boundary - scan system level testing is a
a. 16 - state FSM
b. 8 - state register
c. 8 - state interface pins
d. 16 - state NAND gates
35. The following path is used to reduce testing time in the LSSD
a. simple scan path
b. parallel path
c. single path
d. complex path
36. The test access port or TAP controller in a boundary - scan system - level testing has
connections of
a. one single bit
b. one multiple bits www.studentmoments.com
c. four or five single bit
d. one or two multiple bits
37. The instruction register (IR) in boundary-scan system level testing has to be at least
a. one bit long
b. two bit long www.studentmoments.com
c. there bit long
d. four bit long
38. Subsystems can be checked out individually by providing the appropriate
a. additional inlet/outlet pads
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VLSI DESIGN: Prepared by M.Ramakrishna
44. To find the bridging faults, the following popular testing method is used
a. scan testing
b. I L A
c. I D D Q
d. self testing
45. The layout is tested by using
a. Design rule checker www.studentmoments.com
b. simulator
c. PROBE
d. BILBO
46. The layout modifications improves the performance
a. typically 10 % - 20 %
b. greater than 50 %
c. typically 100 %
d. typically 30 % to 50 %
47. NET is used to
a. verify its compliance with the design rules
b. extract the circuit from the mask layout
c. test for the number of contacts
d. simulate the leaf cell
48. PROBE is used to
a. verify the design rules
b. extract the circuit from the mask layout
c. layout testing
d. simulate the cell
49. To reduce parasitics, the changes are made in
a. circuit
b. transistor size
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VLSI DESIGN: Prepared by M.Ramakrishna
c. layout
d. logic
50. The steady state response to any allowed input state change is independent of the circuit and
wire delays within the system then this logic system is called
a. level-sensitive
b. finite state machine
c. stable - state
d. combinational logic circuit
51. Long counters are tested by
a. scan - based approaches
b. self test
c. built - in testing
d. ad-hoc testing
52. The following type of a fault should not disturb the functionality of the circuit
a. Delay fault
b. bridge fault
c. open circuit
d. stuck at faults
REFERENCES:
1.Essentials of VLSI circuits and systems Kamran Eshraghian, EshraghianDougles and A.
Pucknell, PHI, 2005 Edition- CHAPTER 10 (pp: 306-330).
2.CMOS VLSI Design- A circuits and systems perspective, Neil H.E Weste, David Harris, Ayan
Banerjee, pearson, 2009- CHAPTER 12 (pp: 539-551).
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VLSI DESIGN: Prepared by M.Ramakrishna
ANSWERS-UNIT-VIII
1. a
2. a
3. a
4. a
5. c
6. b
7. b
8. b
9. a
10. a
11. c
12. a
13. a
14. d
15. c
16. b
17. a
18. c
19. d
20. a
21. b
22. b
23. d
24. c
25. a
26. d
27. b
28. a
29. a
30. a
31. c
32. a
33. d
34. a
35. b
36. c
37. b
38. a
39. c
40. d
41. b
42. c
43. b
44. c
45. a
46. a
47. b
48. d
49. c
50. a
51. d
52. c
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VLSI DESIGN: Prepared by M.Ramakrishna