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Anil Wamanrao
Email-awpatil01@gmail.com
Abstract
Voltage or current converters generate discrete output
waveforms, which require large inductances connected in
series with the respective load to generate the desired current
waveform. Mostly, neither the voltage nor the current
waveforms are as expected and also have distorted voltages
and currents waveforms produces harmonic contamination,
additional power losses, and high frequency noise. In this
paper a method of minimization of THD with near to reference
current generation is proposed based on multilevel inverter. A
sinusoidal pulse width modulation scheme is developed for the
multilevel inverter.
Vc +
Vc
Vc
Va
(a)
I. Introduction
Vc
Vc
Va
(b)
Vc
Va
(c)
Fig 1: One phase leg of an inverter with (a) two levels, (b)
three levels, (c) n levels
1
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hn =
(a)
(b)
Fig 3 (a) Vertically shifted carriers
(b) Horizontally shifted carriers
Vo
Vm
V2
V1
1 2 m
3
2
4 m
[Vk cos(nk )]
n k = 1
2
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2mf
vc
vm
Natural Sampling
Asymmetrical
Sampling
Fig. 4 (a) PH
(b) PO
(c) APO
and
is introduce in symmetrical and
mf
2 mf
asymmetrical sampling method respectively , where mf is
frequency modulation ratio
3. This delay in response is significant when the ratio of
switch frequency to reference frequency (the pulse
number) is small. It leads to a frequency response roll-off
which obeys a Bessel function, similar to the familiar sine
function roll-off for Pulse Amplitude Modulation (PAM).
4. Another unwanted effect of digital SPWM is odd
harmonic distortion of the synthesized waveform. The
severity of these effects is a function of the ratio of the
modulating and carrier frequencies, f1/fc. This ratio may
approach and pass unity in high power active filters (high
f1, low fc), by which point these effects have become
significant and limiting.
For five level inverter, four carriers (C1 C4) divides whole
modulating voltage into four region r1 to r4 as shown in Fig 3
(a). Lower order harmonics can be shifted to higher order by
increasing carrier frequency. However, it is not possible to
improve the total harmonic distortion without using output
filter circuit. Switching frequency in SPWM is equal to carrier
frequency therefore switching losses are high.
VI. Implementation of SPWM Technique
Digital implementation SPWM technique is based on classical
SPWM technique with carriers and reference sine waveform.
Only difference between them is, in digital SPWM a sine table
consisting of values of sine waveform sampled at certain
frequency is used. As result reference wave form in digital
SPWM represents a sample and hold waveform of sine wave
forms.
This sampling of sine waveform comes in two variants; a)
Symmetrical sampling, b) Asymmetrical sampling.
Reference
fc
mf =
fm
Ts
tk
tk+ tk
fc = Carrier frequency .
fm = Reference Sine wave frequency.
vc
Mathematically Modulated
Reference
Carrier
tk+1
(tk+1)+ (tk+1)
vm
Symmetrical
Sampling
3
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Vr (t ) = maVm sin(m t )
Where
ma = modulation index .
Vm = Peak value of Reference signal .
m = 2 f m .
fm = fundamental frequency of reference signal .
tk = Time instant at which sine wave form is sampled.
Carrier signal equation for positive slope and negative slope,
Vc
2
Vc
Vc ( N _ S ) = 2Vc fc t +
2
Vc ( P _ S ) = 2Vc fc t
Ca
rri
er
an
d
sig
nal
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0.005
0.01
Time(sec)
0.015
0.02
(a)
200
150
Output Voltage (SPWM)
r=1
r=0
r = -1
100
50
0
-50
-100
-150
r = -2
-200
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
Time (sec)
(b)
4
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2
1.5
1
Carrier
0.5
0
-0.5
-1
-1.5
-2
0.02
0.025
0.03
0.035
0.04
Time (sec)
(a)
(c)
Fig. 9 (a) carrier arrangement, (b) output voltage and (c) FFT
for PH disposition (All carriers are in phase)
200
150
100
Output Voltage
50
0
-50
-100
-150
-200
0.02
0.025
0.03
0.035
0.04
0.045
0.05
0.055
0.06
Time (sec)
(b)
1.5
1
C
a
rrie
r
0.5
0
-0.5
-1
-1.5
-2
0.02
0.025
0.03
0.035
0.04
Time (sec)
(a)
200
150
Output Voltage
100
50
(c)
0
-50
Fig. 11 (a) carrier arrangement, (b) output voltage and (c) FFT
for APO disposition (All carriers are alternatively in
opposition)
-100
-150
-200
0.02
0.025
0.03
0.035
0.04
0.045
0.05
0.055
0.06
(b)
C
arriers
0.5
0
-0.5
-1
(c)
-1.5
-2
0.02
Fig. 10 (a) carrier arrangement, (b) output voltage and (c) FFT
for PO disposition (All carries above the zero reference are in
phase, but in opposition with those below )
0.025
0.03
0.035
0.04
Time (sec)
(a)
200
150
Output Voltage
100
50
0
-50
-100
-150
-200
0.02
0.025
0.03
0.035
0.04
0.045
0.05
0.055
0.06
Time (sec)
(b)
5
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(c)
Fig. 12 (a) carrier arrangement, (b) output voltage and (c) FFT
for SPWM method for 5-level inverter where carriers are
shifted by 90
Table.1 Comparison different SPWM methods for Multilevel
Inverter.
Comparison of SPWM method for Multilevel inverter
Method
THD (%)
1
PH
21.96
2
PO
21.85
3
APO
21.89
4
Carrier shift (90)
21.28
VIII. CONCLUSION
For controlling multilevel inverter different modulation
scheme are used. Of these different modulation schemes
SPWM method has gained more interest in industrial
application. The same can be implemented using hardware.
Mainly DSP or microcontroller based controller are preferred
over analog controller for implementing SPWM scheme for
multilevel inverter. But DSP based
scheme such as
symmetrical sampling, asymmetrical sampling or regular
sampling method either produce phase delay in generated
output waveform or required dedicated processor for
continuous sampling. In this work a mathematical model based
SPWM scheme is proposed which calculate exact instant of
crossing of reference sine waveform with carrier signal and
modify sampled value of reference signal based on this
information to achieve performance same as that with natural
SPWM. Results obtain from MATLAB simulations validate
the proposed scheme which give better performance of
proposed scheme over the other scheme on the basis of output
phase delay and output THD.
1993.
IX. REFERENCES
[1] J. S. Lai and F. Z. Peng, Multilevel Converter- A New
Breed Power Converter, IEEE IAS Annual Meeting
Conf. Record, pp. 2348-2356, 1995
[2] Rodrguez, J., Lai J-S., Zheng Peng, F., Multilevel
Inverters: A Survey of Topologies, Controls,and
Applications, IEEE Transactions on Power Electronics,
Vol. 49, No.4, August 2002, pp.724-737.
[3] M. Manjrekar and G. Venkataramanan, Advanced
topologies and modulation strategies for multilevel
inverters, Conference Record of the IEEE-PESC, 1996,
pp. 1013-1018.
6
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