Digital Design 4H

Principles Of
Digital Design
Flip-Flops
Clocks
Latches
Flip-flops
State diagrams
Copyright 2010-2011 by Daniel D. Gajski
EECS31/CSE31, University of California, Irvine
Topic preview
Boolean
algebra
Finite-state
machine
Logic gates and

flip-flops
Logic design
techniques
Sequential design
techniques
RTL Combinatorial
components
RTL storage
components
Binary system
and data
representation
Generalized
finite-state
machines
Register-transfer
design
Processor
components
Sequential components
Sequential components contain memory elements
The output values of sequential components depend on the

input values and the values stored in the memory elements
The values in the memory elements define the state of

sequential components
Example : Ring counter that starts the answering machine after

4 rings
Sequential components can be

(1) asynchronous or (2) synchronous
Asynchronous sequential components change their state and

output values as a response to change in input values
Synchronous sequential components change their state and

output values at fixed points of time defined by the clock signal
Clock signal
Clock period
Clock
width
Rising edge
Falling edge
Clock period ( measured in micro, nano seconds ) is the time between

successive transitions in the same direction
Clock frequency ( measured in MHz, GHz ) is the reciprocal of clock period
Clock width is the time interval during which clock is equal to 1
Duty cycle is the ratio of the clock width and clock period
Clock signal is active high if the changes occur at the rising edge or during
the clock width
Clock signal is active low otherwise
SR-latch ( NOR implementation )

SR-latch has two states: (1) set state (Q=1) and (2) reset state (Q=0)
S
1.4
1.4
(hold)
(hold)
(reset)
(set)
(?)
Logic schematic
Q (next)
Q (next)
Truth table
R
1.4
Undefined
1.4
1.4
2.8
2.8
1.4
t0
1.4
2.8
1.4
t1
t2
t3
t4
t5
t6
Undefined
1.4
2.8
t7
t8 t9
t10
Timing diagram
Gated SR-latch
Control signal C activates the latch
C S
0 X
0 X
1 0
1 0
1 0
1 1
1 1
R
S
2.0
Q
C
C
R
2.0
Q
S
Graphic symbol
Logic schematic
R
X
X
0
0
1
0
1
Q Q(next)
0
0
(inactive)
1
1
(inactive)
0
0
(hold)
1
1
(hold)
X
0
(reset)
X
1
(set)
X
NA
(?)
Truth table
reset state
set state
reset state
S
R
Q
2.0
4.0
t0
t1
t2 t3
t4
t5
Timing diagram
4.0
t6
t7
t8 t9
2.0
t10 t11 t12
t13
tsetup thold
Gated D-latch
C D
0 X
0 X
1 0
1 1
D
D
2.0
2.0
Q
C
Graphic symbol
Truth table
Logic schematic
reset state
Q Q(next)
0
0
1
1
X
0
X
1
set state
reset state
C
D
2.0
4.0
t0
t1
t2
tsetup
t3
4.0
t4
thold
t5
tsetup
t6
thold
t7
3.0
t8
t9
tsetup
thold
Timing diagram
Setup time is minimum time inputs must be stable before C

Hold time is minimum time inputs must be stable after C
Q follows D while C is asserted as long as D satisfies setup and hold time restrictions
Flip Flops
Latches are level-sensitive since they respond to input changes

during clock width.
Latches are difficult to work with for this reason.
Flip-Flops respond to input changes only during the change in

clock signal.
They are easy to work with though more expensive than latches.
Several styles of flip-flops are available.

(1) master-slave (MS)
(2) edge-triggered (ET)
(3)
Erroneous shifting with D-latches

Erroneous operation is possible with level-sensitive latches
X
D Q1
D Q2
D Q3
4.0/3.0
4.0/3.0
4.0/3.0
Clk
Logic schematic
Clk
X
Q1
4.0
Q2
3.0
3.0
4.0
Q3
4.0
t0
t1
3.0
t2
t3
t5
t4
t6
t7
Timing diagram
Note: Low-to-high delay is 4.0ns. High-to-low delay is 3.0ns.

10
Master-slave flip-flop
In a MS flip-flop D is sampled and stored at the rising edge (low-to-high) of the Clk signal
Master
latch
D
Slave
latch
D Qm
4.0/3.0
C
Qs
4.0/3.0
C
Clk
Logic schematic
Clk
Qm
4.0
Qs
4.0
t0
t1
4.0
5.0
3.0
4.0
3.0
t2
t3
t5
t4
t6
t7
t8
t9
Timing diagram
11
Shifting with master-slave flip-flops

Master-slave flip-flops
X
D Q1n
4.0/3.0
C
Q1s
D Q2n
4.0/3.0
C
4.0/3.0
C
Q2s
4.0/3.0
C
D Q3n
4.0/3.0
C
Q3s
4.0/3.0
C
Clk
Logic schematic
Clk
X
Q1m
3.0
4.0
Q1s
4.0
3.0
Q2m
5.0
4.0
Q2s
4.0
Q3m
3.0
5.0
4.0
Q3s
4.0
t0
t1
t2
t3
t4
t5
t6
t7
Timing diagram
12
Flip-flop types
Flip-flop
name
Flip-flop
symbol
SR
Clk
R
Characteristic
table
S
0
0
1
1
R
0
1
0
1
Characteristic
equation
Q(next)
Q
0
1
NA
Q(next)=S+RQ
SR=0
Excitation
table
Q
0
0
1
1
Q(next)
0
1
0
1
S
0
1
0
X
R
X
0
1
0
S,R=1,0
S=0
R=0
State diagram
Q=1
Q=0
S,R=0,1
Q(next)
0
1
0
1
Clk
Q(next)=D
Q
0
0
1
1
Q(next)
0
1
0
1
D
0
1
0
1
D=1
D=0
State diagram
D=1
Q=1
Q=0
D=0
Note: For master-slave flip-flops data inputs must satisfy set-up and hold time constraints.
13
A latch / flip-flop with asynchronous inputs

CLR
D
Q
C
PRS
D
Q
CLR
PRS
Graphic symbol
D latch
14
Summary
We introduced memory elements

Latches (asynchronous)
Flip-flops (synchronous)
We presented several ways to describe memory

elements
Characteristic tables
Characteristic equations
State diagrams
Timing diagrams
We introduced the concept of a state diagram >> FSM
15

Digital Design 4H

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Digital Design 4H

Caricato da

Copyright:

Formati disponibili

Principles Of

Copyright 2010-2011 by Daniel D. Gajski

EECS31/CSE31, University of California, Irvine

Logic gates and

EECS31/CSE31, University of California, Irvine

Sequential components contain memory elements

The output values of sequential components depend on the

The values in the memory elements define the state of

Example : Ring counter that starts the answering machine after

Sequential components can be

Asynchronous sequential components change their state and

Synchronous sequential components change their state and

Copyright 2010-2011 by Daniel D. Gajski

EECS31/CSE31, University of California, Irvine

Clock period ( measured in micro, nano seconds ) is the time between

Clock frequency ( measured in MHz, GHz ) is the reciprocal of clock period

Clock width is the time interval during which clock is equal to 1

Clock signal is active low otherwise

Copyright 2010-2011 by Daniel D. Gajski

EECS31/CSE31, University of California, Irvine

SR-latch ( NOR implementation )

EECS31/CSE31, University of California, Irvine

Copyright 2010-2011 by Daniel D. Gajski

t10 t11 t12

Setup time is minimum time inputs must be stable before C

EECS31/CSE31, University of California, Irvine

Latches are level-sensitive since they respond to input changes

Latches are difficult to work with for this reason.

Flip-Flops respond to input changes only during the change in

Several styles of flip-flops are available.

Copyright 2010-2011 by Daniel D. Gajski

EECS31/CSE31, University of California, Irvine

Erroneous shifting with D-latches

Note: Low-to-high delay is 4.0ns. High-to-low delay is 3.0ns.

EECS31/CSE31, University of California, Irvine

EECS31/CSE31, University of California, Irvine

Shifting with master-slave flip-flops

EECS31/CSE31, University of California, Irvine

EECS31/CSE31, University of California, Irvine

A latch / flip-flop with asynchronous inputs

Copyright 2010-2011 by Daniel D. Gajski

EECS31/CSE31, University of California, Irvine

We introduced memory elements

We presented several ways to describe memory

We introduced the concept of a state diagram >> FSM

Copyright 2010-2011 by Daniel D. Gajski

EECS31/CSE31, University of California, Irvine

Potrebbero piacerti anche