Pipelining Outline

Introduction

ECE473 Computer Architecture and

Organization

Defining Pipelining
Pipelining Instructions

Hazards

Structural hazards
Data Hazards
Control Hazards

Pipeline: Control

Exceptions
Performance
P f
Controller implementation

Lecturer: Prof. Yifeng Zhu

Fall, 2012

ECE473

Portions of these slides are derived from:

Dave Patterson UCB

Lec 17.1

Lec 17.2

ECE473

Pipelined Datapath with Control

Signals

Pipelining in MIPS
MIPS architecture was designed to be pipelined
Simple instruction format (makes IF, ID easy)
Single-word instructions
Small number of instruction formats
Common fields in same place (e.g., rs, rt) in different
formats
Memory operations only in lw, sw instructions
(simplifies EX)
Memory operands aligned in memory (simplifies MEM)
Single value for writeback (limits forwarding)

PCSrc
1

PCSrc

ID/EX

IF/ID

EX/MEM

MEM/WB

ADD
ADD
4
RegWrite

PC
ADDR

RD

Instruction
Memory

Pipelining is harder in CISC architectures

rs
32

rt

RN1

RN2

WN
WD

MemWrite
RD1

Register
File RD2

ALUSrc

Zero

ALU

ADDR

Data
Memory

0
1

immed 16
rt
rd

Branch

<<2

E
X
T
N
D

RD

MemtoReg
0

WD

ALU
Control

32
6

ALUOp

MemRead

RegDst

ECE473

Lec 17.3

ECE473

Lec 17.4

Next Step: Adding Control

Control for Pipelined Datapath

Basic approach: build on single-cycle control

WB

Place control unit in ID stage

Pass control signals to following stages

Control

Later: extra features to deal with:

WB

EX

Data forwarding
Stalls
Exceptions

RegDst
ALUOp[1:0]
ALUSrc

IF / ID

Lec 17.5

ECE473

ID / EX

WB

MemRead
MemWrite
Branch

RegWrite
MemtoReg

EX / MEM

MEM / WB

Lec 17.6

ECE473

Control for Pipelined Datapath

Datapath and Control Unit

PCSrc

Instruction
R-format
lw
sw
beq

Execution/Address Calculation
Memory access stage
stage control lines
control lines
ALU
ALU
Mem
Mem
Reg Dst Op1
Op0 ALU Src Branch Read
Write
1
1
0
0
0
0
0
0
0
0
1
0
1
0
X
0
0
1
0
0
1
X
0
1
0
1
0
0

RegWrite

Write-back stage
control lines
Reg
Mem to
write
Reg
1
0
1
1
0
X
0
X

Control

ADD
4
RegWrite

WB
Control

M
EX

PC
ADDR

RD

Instruction
Memory

WB
M

rs
32

WB

rt

RN1

RN2

WN
WD

RD1

EX / MEM

MEM / WB

rd

Lec 17.7

ECE473

Zero

ALU

ADDR

Data
Memory

E
X
T
N
D

RD
0

WD
32
6

RegDst
0

ALU
Control

ALUOp

MemRead

IF/ID
ECE473

ALUSrc

rt

ID / EX

Branch

<<2

Register
File RD2

immed 16

IF / ID

ADD

ID/EX

EX/MEM

MEM/WB
Lec 17.8

Tracking Control Signals - Cycle 1

PCSrc

Tracking Control Signals - Cycle 2

PCSrc

RegWrite

1
0

RegWrite

Control

Control

ADD

ADD

ADD

4
RegWrite

PC
ADDR

RD

Instruction
Memory

rs
32

rt

Branch

<<2

RegWrite

PC
5

RN1

RN2

WN
WD

RD1

ALU

Data
Memory

E
X
T
N
D

RegDst

RN1

RN2

WN
WD

MemRead

RD1

EX/MEM

E
X
T
N
D

rt

SW

MEM/WB
Lec 17.9

ECE473

Zero

ALUSrc

ALU

Data
Memory

ALU
Control

32
6

RegDst

MemRead

ALUOp

5
LW

IF/ID

RD

WD

ID/EX

EX/MEM

MEM/WB
Lec 17.10

ECE473

Tracking Control Signals - Cycle 3

Tracking Control Signals - Cycle 4

PCSrc

PCSrc
0

Control

RegWrite

RegWrite

Control

ADD

ADD
4

4
RegWrite

Branch

<<2

RegWrite

PC

PC
ADDR

RD

Instruction
Memory

rs
32

rt

RN1

RN2
WN

WD

RD1

IF/ID

ADDR

Zero

ALU

Data
Memory

E
X
T
N
D

RegDst

SW

ID/EX

rs
32

RN2

WN
WD

rd

SUB

MEM/WB
Lec 17.11

ECE473

IF/ID

Branch

<<2

RD1

Zero

ALUSrc

Register
File RD2

ALU

ADDR

Data
Memory

0
1

rt

MemRead

01

EX/MEM

RN1

immed 16

ALUOp

ALU
Control

LW

rt

RD

WD
32

RD

Instruction
Memory

ADDR

rt
rd

ALUSrc

Register
File RD2

immed 16

ADD

ADD

ADD

ECE473

ADDR

0
1

rd

ID/EX

Branch

<<2

Register
File RD2

immed 16

ALUOp

IF/ID

rt

ALU
Control

rs
32

RD

WD
32

RD

Instruction
Memory

ADDR

rt
rd

ADDR

Zero

ALUSrc

Register
File RD2

immed 16

LW

ADD

E
X
T
N
D

32
6

RegDst

ADD

RD
0

WD

ID/EX

ALU
Control

ALUOp

SW

EX/MEM

1
LW

MemRead

MEM/WB
Lec 17.12

Tracking Control Signals - Cycle 5

PCSrc

Class Exercise
Consider the following code segment
1.
LW R1, 0(R4)
2.
LW R2, 0(R5)
3.
ADD R3, R1, R2
4.
BNZ R3, L
5.
LW R4, 100(R1)
6.
LW R5, 100(R2)
7.
SUB R3, R4, R5
8. L: SW R3, 50(R1)

RegWrite

1
0

Control

ADD
ADD
4
RegWrite

ADDR

RD

Instruction
Memory

rs
32

rt

RN1

RN2

WN
WD

RD1

rt
rd

ALU

ADDR

Data
Memory

0
1

E
X
T
N
D

ADD

MemRead

ALUOp

ID/EX

1
0

ALU
Control

RegDst

5
5
SUB

RD

WD
32

Assuming that
there is no forwarding,
zero testing
t ti is
i being
b i resolved
l d d
during
i ID
ID, and
d
registers can be written in the first of the WB
cycle and also be read in the send half of the same
WB cycle,

Zero

ALUSrc

Register
File RD2

immed 16

IF/ID

Branch

<<2

PC

EX/MEM

SW

MEM/WB

Lec 17.13

ECE473

Question: identify the resources of various hazards

in the above code sequence.

LW

Lec 17.14

ECE473

Class Exercise

Class Exercise

Consider the following code segment

1.
LW R1, 0(R4)
2.
LW R2, 0(R5)
3.
ADD R3, R1, R2
4.
BNZ R3, L
5.
LW R4, 100(R1)
6.
LW R5, 100(R2)
7.
SUB R3, R4, R5
8. L: SW R3, 50(R1)

Consider the following code segment

1.
LW R1, 0(R4)
2.
LW R2, 0(R5)
3.
ADD R3, R1, R2
4.
BNZ R3, L
5.
LW R4, 100(R1)
6.
LW R5, 100(R2)
7.
SUB R3, R4, R5
8. L: SW R3, 50(R1)

Assuming that
there is no forwarding,
zero testing
t ti is
i being
b i resolved
l d d
during
i ID
ID, and
d
registers can be written in the first of the WB
cycle and also be read in the send half of the same
WB cycle,

Use compiler techniques to reshuffle/rewrite the

code (without changing the meaning of the program)
as to minimize data hazards as far as possible.
Assume that no other general purpose registers
other than those used in the code, are available.

Question: identify the resources of various hazards

in the above code sequence.
ECE473

Lec 17.15

ECE473

Lec 17.16

Class Exercise
Consider the following code segment
1.
LW R1, 0(R4)
2.
LW R2, 0(R5)
3.
ADD R3, R1, R2
4.
BNZ R3, L
5.
LW R4, 100(R1)
6.
LW R5, 100(R2)
7.
SUB R3, R4, R5
8. L: SW R3, 50(R1)

1.
2.
3.
4.
5.
6.
7.
8.

LW R1, 0(R4)
LW R2, 0(R5)
( )
LW R4,, 100(R1)
LW R5, 100(R2)
ADD R3, R1, R2
BNZ R3, L
SUB R3, R4, R5
L: SW R3, 50(R1)

Use compiler techniques to reshuffle/rewrite the

code (without changing the meaning of the program)
as to minimize data hazards as far as possible.
Assume that no other general purpose registers
other than those used in the code, are available.

ECE473

Lec 17.17