Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
MATERIAL
UNIT-III
PIN DIAGRAM OF 8086
The 8086 is internally a 16-bit MPU and externally it has a 16-bit data bus. It has the ability to address up to 1
MB of memory via its 20-bit address bus. In addition, it can address up to 64K of byte-wide input/output
ports.
It is manufactured using high-performance metal-oxide semiconductor (HMOS) technology, and the
circuitry on its chip is equivalent to approximately 29,000 transistors.
The 8086 is housed in a 40-pin dual in-line package. The signals pinned out to each lead are shown in figure.
The address bus lines A0 through A15 and data bus lines D0 through D15 are multiplexed.
For this reason, these leads are labeled AD0 through AD15. By multiplexed we mean that the
same physical pin carries an address bit at one time and the data bits at another time.
P SREEKANTH
2
P SREEKANTH
BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer of data over the
higher order (D15-D8) data bus. It goes low for the data transfers over D15-D8 and is used to derive chip selects
of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge
cycles, when- ever a byte is to be transferred on the higher byte of the data bus.
3
P SREEKANTH
TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution will continue, else,
the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading
edge of clock.
RESET: This input causes the processor to terminate the current activity and start execution from FFFF0H. The
signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET
returns low. RESET is also internally synchronized.
VCC: +5V power supply for the operation of the internal circuit. GND ground for the internal circuit.
Control Signals:
When Address latch enable (ALE) is logic 1 it signals that a valid address is on the bus. This address can be
latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
M/IO (memory/IO) tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic
1 signals a memory operation and logic 0 signals an I/O operation.
DT/R (data transmit/receive) signals the direction of data transfer over the bus. Logic 1 indicates that the bus
is in the transmit mode (i.e., data are either written into memory or to an I/O device). Logic 0 signals that the
bus is in the receive mode (i.e., reading data from memory or from an input port).
The bank high enable (BHE) signal is used as a memory enable signal for the most significant byte half of
the data bus, D8 through D15.
WR (write) is switched to logic 0 to signal external devices that valid output data are on the bus.
RD (read) indicates that the MPU is performing a read of data off the bus. During read operations, one other
control signal, DEN (data enable), is also supplied. It enables external devices to supply data to the
microprocessor.
The READY signal can be used to insert wait states into the bus cycle so that it is extended by a number of
clock periods. This signal is supplied by a slow memory or I/O subsystem to signal the MPU when it is ready to
permit the data transfer to be completed.
Interrupt Signals:
4
P SREEKANTH
SYSTEM CLOCK:
To synchronize the internal and external operations of the microprocessor a clock (CLK) input signal is used.
The CLK can be generated by the 8284 clock generator IC.
The 8086 is manufactured in three speeds: 5 MHz, 8 MHz and 10 MHz.
LOCK:
P SREEKANTH
After decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or
double opcode byte. If it is single opcode byte, the next bytes are treated as data byte depending upon the
decoded instruction length; otherwise, the next byte in the queue is treated as the second byte of the instruction
opcode. The second byte is then decoded in continuation with the first byte to decide the instruction length and
the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read
from the queue but the fetch cycle is initiated by BIU only if at least, two bytes of the queue are empty and the
EU may be concurrently executing the fetched instructions.
6
P SREEKANTH
7
P SREEKANTH
AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN
output depends upon the status of the IOB pin.
If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data
enable used in the multiple bus configurations.
INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.
IORC, IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the address port.
The MRDC, MWTC are memory read command and memory write command signals respectively and may be
used as memory read or write signals.
All these command signals instructs the memory to accept or send data from or to the bus.
For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.
Here the only difference between in timing diagram between minimum mode and maximum mode is the status
signals used and the available control and advanced command signals.
R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply
a required signal to its DT / R pin during T1.
P SREEKANTH
One cycle of clock is called a state or t-state. The bus cycle of the 8086 microprocessor consists of at least four
clock periods. These four time states are called T1, T2, T3 and T4. This group of states is called a MACHINE
CYCLE.
The total time required to fetch and execute an instruction is called an instruction cycle. An instruction cycle
consists of one or more machine cycle.
The memory must provide valid data during T3 and maintain it until after the processor terminates the
read operation. The data read by the 8086 microprocessor can be carried over all 16 data bus lines.
During T4,
o The 8086 switches RD to the inactive 1 logic level to terminate the read operation. DEN returns to its
inactive logic level late during T4 to disable the external circuitry.
12
P SREEKANTH
13
14
P SREEKANTH
A0
I/00
Memory Capacity
1K=1024(0400H)
Address lines
10
.
.
2K=2048(0800H)
11
4K=4096(1000H)
12
.
.
8K=8192(2000H)
13
16K=16384(4000H)
14
AN
I/ON
32K=32768(8000H)
15
64K=65536(10000H) 16
Available memory for 8086 is 1MB. EPROM can be used as program memory and RAM as a data
memory.
EPROM and RAM can be placed anywhere in 1MB memory but EPROM can be placed at last memory
page so that starting address of program memory at FFFF0H.
For interfacing memory to 8086, provide odd and even banks of memory. Even bank is selected when
A0=0 and odd bank is selected when BHE=0.
C
In order to communicate with memory or I/O devices, microprocessor has to decode the address.
Absolute Decoding:
In absolute decoding technique, the memory chip is selected only for the specified
logic level on the address lines. Here in order to select an 8K memory chip, we are using 13 address lines for each
memory location and remaining address lines (A19 A14) are used to generate unique chip select signal. However
this has a disadvantage that implementing this requires more hardware. It is used in large systems.
15
P SREEKANTH
Absolute Decoding
Linear Decoding:
This technique eliminates the hardware for decoding logic i.e. it uses less number of
lines for selecting the chip but it has a drawback that multiple same addresses can be provided for different chips.
This can be used in small systems.
Linear Decoding
Block decoding: In this technique, decoder can be used to select the chip logic. This can be used in systems
which uses array of memories.
16
P SREEKANTH
2. 64KB EPROM
3.
64KB
RAM.
Draw
the
complete
17
P SREEKANTH
18
P SREEKANTH
Memory Map:
Ex 3: Generate chip select signals with the help of 74LS138 to six memory chips of size 16KB, with the
address map from 00000H to 17FFFH.
Sol: The capacity of the memory is 128KB
Size of the single memory chip is 16KB i.e. 0 16383 (0 3FFFH)
In order to represent 128KB, 8 chips are required but number of chips should be used is six.
P SREEKANTH
19
20
21
P SREEKANTH
Direct Memory Access (DMA) is a method of allowing data to be moved from one location to
another in a computer without intervention from the central processor (CPU). It is also a fast way
of transferring data within (and sometimes between) computer.
The DMA I/O technique provides direct access to the memory while the microprocessor is
temporarily disabled. The DMA controller temporarily borrows the address bus, data bus and
22
P SREEKANTH
DMA OPERATION
The HOLD signal as an input (to the processor) is used to request a DMA action.
The HLDA signal as an output that acknowledges the DMA action. When the processor recognizes the
hold, it stops its execution and enters hold cycles. HLDA becomes active to indicate that the processor
has placed its buses at high- impedance state.
A DMA read transfers data from the memory to the I/O device. A DMA write transfers data from an I/O
device to memory. The system contains separate memory and I/O control signals. Hence the Memory &
the I/O are controlled simultaneously.
The DMA controller provides memory with its address, and the controller signal selects the I/O device
during the transfer.
Data transfer speed is determined by speed of the memory device or a DMA controller.
In bus master mode, the DMA controller acquires the system bus from the CPU to perform the DMA
transfers. Because the CPU releases the system bus for the duration of the data transfer, the process is
sometimes referred to as cycle stealing.
In bus slave mode, the DMA controller is accessed by the CPU, which programs the DMA controllers
internal registers to set up DMA transfers. The internal register consist of source and destination address
registers and transfer count registers for each DMA channel, as well as control and status registers for
initiating, monitoring and sustaining the operation of the DMA controller.
23
P SREEKANTH
25
P SREEKANTH
2. Read/Control logic
4. Priority resolver
5. DMA channels.
DATA BUS BUFFER: It contains tristate, 8 bit bi-directional buffer. Slave mode, it transfer data between
microprocessor and internal data bus. Master mode, the outputs A8-A15 bits of memory address on data lines
(Unidirectional).
READ/CONTROL LOGIC: It controls all internal Read/Write operation. Slave mode, it accepts address bits and
control signal from microprocessor. Master mode, it generate address bits and control signal.
Control logic block: It contains, Control logic, Mode set register and Status Register.
CONTROL LOGIC: Master mode, It control the sequence of DMA operation during all DMA cycles. It generates
address and control signals. It increments 16 bit address and decrement 14 bit counter registers. It activates a
HRQ signal on DMA channel Request. Slave, mode it is disabled.
Register organization of 8257: The 8257 performs the DMA operation over four independent DMA channels.
Each DMA channel has a pair of two 16-bit registers i.e. address register and terminal count register. Also there
are two common registers for all the channels are Mode set register and Status register. The CPU selects one of
these registers using address lines A0 to A3.
DMA address register: The function of this register is to store the address of the starting memory location, which
will be accessed by the DMA channel.
Terminal Count register: The function of this register is to indicate the end of the data transfer after required
number of DMA cycles.
The low order 14-bits of the terminal count register are initialized with the number
of DMA cycles minus one. After each DMA cycle this register content can be decremented by 1and becomes zero
after all DMA cycles are over. The bits 14 and 15 indicate the type of the DMA operation.
26
P SREEKANTH
Status Register
P SREEKANTH
27
Pin Description:
DREQ0 DREQ3 (DMA request): Used to request a DMA transfer for a particular DMA channel.
DACK0 DACK3 (DMA channel acknowledge): Acknowledges a channel DMA request from a device.
HRQ (Hold request): Requests a DMA transfer.
HLDA (Hold acknowledge) signals the 8237 that the microprocessor has relinquished control of the address,
data and control buses.
A0 A3 In idle cycle these can act as inputs and are used by 8237 to address the control registers to be read or
written. In an active cycle, they provide the lowest 4 bits of the output addresses generated by 8237.
A4 A7 These lines are activated only during DMA services to generate address bits.
DB0 DB7 These lines are used to transfer data to / from I/O device or memory.
AEN (Address enable): Enables the DMA address latch connected to the 8237 and disable any buffers in the
system connected to the microprocessor. (Use to take the control of the address bus from the microprocessor)
ADSTB (Address strobe): Functions as ALE to latch address during the DMA transfer.
EOP (End of process): Signals the end of the DMA process.
IOR (I/O read): Used as an input strobe to read data from the 8237 during programming and used as an output
strobe to read data from the port during a DMA write cycle.
IOW (I/O write): Used as an input strobe to write data to the 8237 during programming and used as an output
strobe to write data to the port during a DMA read cycle.
MEMW (Memory write): Used as an output to cause memory to write data during a DMA write cycle.
MEMR (Memory read): Used as an output to cause memory to read data during a DMA read cycle.
28
P SREEKANTH
29
P SREEKANTH
COMMAND REGISTER
MODE REGISTER
MSR REGISTER
MRSR REGISTER
STATUS REGISTER
SINGLE MODE
DEMAND MODE
BLOCK MODE
31
P SREEKANTH
First sendmaster clear software to 8237, which mask/disable all DMA channels, clear first-last flip-flop
and clear all internal registers, except mask register.
Send a command register to inform priority of DMA channels, normal/compressed timings, polarity of
DREQ and polarity of DACQ signals.
Write a mode word to mode register of each channel to inform DMA mode and type of DMA transfer.
32
P SREEKANTH
33
P SREEKANTH