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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-1
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-2
Objectives
After completing this chapter, you will be able to:
Understand the features of decoders
Understand the features of encoders
Understand the features of priority encoders
Understand the features of multiplexers
Understand the features of demultiplexers
Describe how to design comparators and
magnitude comparators
Describe how to design a parameterized module
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-3
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-4
Decoder
Encoder
Multiplexer
Demultiplexer
Comparator
Adder (CLA)
Subtracter (subtractor)
Multiplier
PLA
Parity Generator
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-5
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-6
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-7
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-8
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-9
[1:0]
[0]
[1]
un1_y28
enable
1111
[3:0] [3:0]
y[3:0]
[1]
[0]
y[3:0]
un1_y27
[0]
[1]
y26
un1_y26
y25
un1_y25
[0]
[1]
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-10
[0]
[1]
[1]
[0]
0000
0
1
[3:0] [3:0]
y[3:0]
y[3:0]
[0]
[1]
y26
[0]
[1]
y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-11
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-12
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-13
8-14
[3:0]
[0]
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y[1:0]
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[2]
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y24
[3]
[0]
[1]
[2]
y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-15
[3:0]
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[1]
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y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-16
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-17
y[1:0]
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valid_in
valid_in
[2]
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y_1[0]
in[3:0]
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un1_in_1
un1_in_3
y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-18
[0]
[1]
[2]
[3]
valid_in
valid_in
in[3:0]
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10
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00
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[1:0]
[1:0]
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y[1:0]
[0]
[1]
[2]
[3]
y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-19
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-20
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-21
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-22
[1:0]
in3[3:0]
[3:0]
[0]
[1]
[1]
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in2[3:0]
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[3:0]
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[1]
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d
[3:0]
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d
[3:0]
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d
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e
d
[3:0] [3:0]
y[3:0]
y[3:0]
un1_select_4
[0]
[1]
un1_select_5
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-23
8-24
[1:0]
in3[7:0]
[7:0]
[0]
[1]
[1]
[0]
in1[7:0]
in2[7:0]
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[7:0]
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[7:0]
e
d
[7:0] [7:0]
y[7:0]
y[7:0]
[0]
[1]
un1_select_5
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-25
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-26
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-27
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-28
[1:0]
[0]
[1]
y37
0000
[3:0]
[3:0] [3:0]
y3[3:0]
[3:0] [3:0]
y2[3:0]
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0000
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y1[3:0]
[0]
[1]
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0000
[3:0]
0
1
y0[3:0]
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-29
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-30
Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-31
Comparators
A 4-bit comparator
8-32
Types of Comparators
Comparator
Cascadable comparator
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-33
Comparators
An 8-bit comparator
8-34
a[3:0]
[3:0]
[3:0]
b[3:0]
[3:0]
[3:0]
ceq
ceq
[3:0]
[3:0]
<
cgt
cgt
[3:0]
[3:0]
<
clt
clt
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
8-35
<
un1_Oagtb
a[3:0]
[3:0]
[3:0]
b[3:0]
[3:0]
[3:0]
parameter N = 4;
// I/O port declarations
input Iagtb, Iaeqb, Ialtb;
input [N-1:0] a, b;
output Oagtb, Oaeqb, Oaltb;
Oaeqb
Oaeqb
=
un1_Oaeqb
Oagtb
un2_Oagtb
Oagtb
Iagtb
[3:0]
[3:0]
<
un1_Oaltb
Oaltb
Oaltb
Ialtb
un2_Oaltb
8-36