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Outline
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loop: lw
lw
add
sw
addi
addi
bgtz
$t3,
$t4,
$t2,
$t2,
$t0,
$t1,
$t1,
0($t0)
4($t0)
$t3, $t4
8($t0)
$t0, 4
$t1, -1
loop
Assembler
0x8d0b0000
0x8d0c0004
0x016c5020
0xad0a0008
0x21080004
0x2129ffff
0x1d20fff9
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Advantages of RISC
easier to understand and teach :-)
regular structure make it easier to pipeline
no machine code to microcode translation step
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loop: lw
lw
add
sw
addi
addi
bgtz
$t3,
$t4,
$t2,
$t2,
$t0,
$t1,
$t1,
0($t0)
4($t0)
$t3, $t4
8($t0)
$t0, 4
$t1, -1
loop
Assembler
0x8d0b0000
0x8d0c0004
0x016c5020
0xad0a0008
0x21080004
0x2129ffff
0x1d20fff9
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6 bits
5 bits
5 bits
5 bits
5 bits
6 bits = 32 bits
000000
rs
rt
rd
shamt
funct
op
rs
rt
op
Register-type
address/immediate
target address
Immediate-type
Jump-type
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Immediate-type instructions
# move from/to
mfhi $t1
mflo $t1
# jump register
jr
$ra
# load/store
lw
$t1, 345($t2)
sw
$t2, 345($t1)
lb
$t1, 345($t2)
sb
$t2, 345($t1)
Jump-type instructions
# unconditional jump
j
label
Outline
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Components of an instruction
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
000000
rs
rt
rd
shamt
funct
op
rs
rt
op
Component
address/immediate
target address
Description
op, funct
codes that determine operation to perform
rs, rt, rd
register numbers for args and destination
shamt, imm, addr values embedded in the instruction
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Assembling instructions
machine code
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Name
$zero
$at
$v0$v1
$a0$a3
$t0$t7
$s0$s7
$t8$t9
$k0$k1
$gp
$sp
$fp
$ra
Usage
constant 0x00000000
assembler temporary
function return values
function arguments
temporaries
saved temporaries
more temporaries
reserved for OS kernel
global pointer
stack pointer
frame pointer
return address
Preserved?
N/A
N/A
7
7
7
3
7
N/A
3
3
3
N/A
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000000
rs
rt
rd
shamt
funct
R-type instruction
op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
32 bits
always zero!
1st argument register
2nd argument register
destination register
used in shift instructions (for us, always 0s)
code for the operation to perform
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rs
000000
rs
rt
rd
funct
shamt
= 10
= 11
= 9
= 32
= 0
rt
rd
shamt
funct
($t2 = $10)
($t3 = $11)
($t1 = $9)
(look up function code for add)
(not a shift instruction)
000000
10
11
32
000000
01010
01011
01001
00000
100000
Exercises
Name
R:
rs
rt
rd
sh
fn
$ra
$zero
$v0$v1
$a0$a3
$t0$t7
$s0$s7
$t8$t9
$sp
$ra
Instr
add
sub
mult
div
jr
Number
0
23
47
815
1623
2425
29
31
fn
32
34
24
26
8
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op
rs
rt
address/immediate
I-type instruction
op
rs
rt
imm
6 bits
5 bits
5 bits
16 bits
32 bits
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op
rs
op
rs
rt
imm
= 8
= 13
= 12
= 67
rt
address/immediate
13
12
67
001000
01101
01100
Exercises
Name
R:
rs
rt
I:
op
rs
rt
rd
sh
addr/imm
fn
$zero
$v0$v1
$a0$a3
$t0$t7
$s0$s7
$t8$t9
$sp
$ra
Instr
and
andi
or
ori
Number
0
23
47
815
1623
2425
29
31
op/fn
36
12
37
13
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I:
op
rs
rt
address/immediate
I-type instruction
op
rs
rt
imm
6 bits
5 bits
5 bits
16 bits
32 bits
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skip:
beq
nop
nop
nop
nop
...
offset = 3
loop:
nop
nop
nop
nop
beq
nop
# -5
# -4
# -3
# -2
$t0, $t1, loop
# 0 (start here)
offset = -5
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label:
op
rs
op
rs
rt
imm
=
=
=
=
beq
nop
nop
nop
rt
4
8
9
2
address/immediate
000100
01000
01001
Exercises
Name
R:
rs
rt
I:
op
rs
rt
rd
sh
addr/imm
fn
$zero
$v0$v1
$a0$a3
$t0$t7
$s0$s7
$t8$t9
$sp
$ra
Instr
add
addi
beq
bne
Number
0
23
47
815
1623
2425
29
31
op/fn
32
8
4
5
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J-type instructions
J:
op
target address
...
...
0x40000A4
label:
label
nop
...
...
0x404C100
label
0x40000A4
0x 0000A4 = 0xA4
10100100
101001
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label
...
...
0x40000A4
label:
nop
...
...
0x404C100
op
label
target address
op =
2
addr = 101001
101001
0000 10
Jump register jr
address is 32 bits (in register)
range: any addressable memory location (4GB)
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Outline
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mul
li
$t0, 0xABCD
ori
li
$t0, 0x1234ABCD
lui
ori
$at, 0x1234
$t0, $at, 0xABCD
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