Sei sulla pagina 1di 40

Unit 9

Multiplexers, Decoders, and


Programmable Logic Devices

Unit 9

Outline

Multiplexers (pp. 261-265)


Three-State Buffers (pp. 265-268)
Decoders and Encoders (pp. 268-271)
Read-Only Memories (pp. 271-275)
Programmable Logic Devices (pp. 275-280)
Complex Programmable Logic Devices (pp. 280-281)
Field-Programmable Gate Arrays (pp. 282-285)

Unit 9

Multiplexers (1/6)

A multiplexer (abbreviated as MUX) has a group of data


inputs and a group of control inputs used to select one
of the data inputs and connect it to the output terminal.

Z = AI0 + AI1
Unit 9

Multiplexers (2/6)
I0
I1
I2
I3

4-to-1
MUX

8-to-1
MUX

I1

Unit 9

4 1 : Z A' B' I 0 A' BI1 AB' I 2 ABI 3

I0

I2n-1

I2
I3

A B C

I0

A
I0
I1

I7

A A' B B'

2n-to-1
MUX

n control inputs

8 1 : Z A' B' C' I 0 A' B' CI1 A' BC' I 2 A' BCI3
AB' C' I 4 AB' CI5 ABC' I 6 ABCI7
2 n 1

2n 1 : Z m k I k
k 0

Multiplexers (3/6)
Quad multiplexer to select data
2:1 Mux
X0 S
1

2:1 Mux

Z0
D

X1 S
1

Y1 S
2

Y0 S
2
C

ENB

2:1 Mux

Z1
X2 S
1

Y2 S
2
C

ENB

2:1 Mux

Z2
X3 S
1

Z3
D

Y3 S
2
C

ENB

ENB

EN
A

Unit 9

Multiplexers (4/6)
4-to-1 MUX to realize 3-variable function

Ex :

I0

I1

F(A, B, C) A' B'AC


C
A' B'AC (B B' )
C
A' B'1 AB' C ABC

Unit 9

I2
I3

D
4-to-1
MUX

S1

S2

Multiplexers (5/6)
8-to-1 MUX to realize 4-variable function

F = ABC + ABC +
ABD + ACD +
BCD

A B C

= ABC(D+D) +
ABC (D+D) +
AB(C+C)D +
A(B+B)CD +
(A+A)BCD

Unit 9

A' B' C' 1


A' B' C D
A' BC' 0
A' BC 1
AB' C' D'
AB' C D
ABC' D'
ABC D'

1
D

I0
I1

0
1
D
D
D

I2
I3 8 to 1
I4 MUX
I5
I6

I7

A B C
7

Multiplexers (6/6)
I0
I1
I2
I3
I4
I5
I6
I7
Unit 9

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B C
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

D F
0 1
1 1
0 0
1 1
0 0
1 0
0 1
1 1
0 1
1 0
0 0
1 1
0 1
1 0
0 1
1 0

F = ABC(D+D) + ABC (D+D) +


AB(C+C)D + A(B+B)CD +
(A+A)BCD

D
0
1
D
D
D
D

V1 V2
0 0
0 0

Vn
0
1

F
0 0 1 1
0 1 0 1

0 Vn Vn 1

F A' B' C ' A' B' CD A' BC AB' C ' D'


AB' CD ABC ' D' ABCD'
A' B' C ' A' BC ABD' AC' D' B' CD
8

Three-State Buffers (1/4)


Buffer: to increase the driving capability of a gate output

Tri-state Buffer: permits gate outputs to be connected together

Unit 9

Three-State Buffers (2/4)

Data selection using three-state buffers

Unit 9

10

Three-State Buffers (3/4)


Circuit with two three-state buffers
S1

S2

S1

S2

F is determined from the above table


Unit 9

11

Three-State Buffers (4/4)


Applications
1. Bus

4-bit adder with four sources for one operand

2. Chip I/O

Unit 9

12

Decoders (1/4)
A decoder generates all of the minterms, and exactly one of
the output lines will be 1 for each combination of the values
of the input variables.

m0
m1
m2
m3
m4
m5
m6
m7

y0 a' b' c'


y1 a' b' c

y7 abc

m0
m1

m7

3-to-8 decoder
Unit 9

13

Decoders (2/4)
A

y0

y1

y1

y3

B
Unit 9

2-to-4
decoder

y0
y2

y0
y1
y2
y3

y7
14

Decoders (3/4)
BCD input

4-to-10 decoder
m9 m8m7m6m5m4m3 m2m1m0

Unit 9

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Decimal output
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

3
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1

4
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

5
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1

6
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

7
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1

8
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

9
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1

15

Decoders (4/4)
Realization of a multiple-output circuit using a decoder

F1 m1 m2 m4 F2 m4 m7 m9
A
B

C
D

Unit 9

0
1
2
4-to-10 3
Decoder 4
5
6
7
8
9

m1 '
m2 '
m4 '

F1

m7'
m9'

F2

16

Encoders

An encoder performs the inverse function of a decoder.


Consider the following 8-to-3 priority encoder

If input yi is 1 and the other inputs are 0, then abc outputs represent a binary number equal to i.

If more than one input is 1, the highest numbered input determines the output.

An extra output, d, is 1 if any input is 1, otherwise d is 0. The d signal is needed to distinguish the
case of all 0 inputs from the case where only y0 is 1.

Unit 9

y0

y1

y2

y3

y
4

y5

y6

y7

17

Read-Only Memories (1/6)

A read-only memory (ROM) consists of an array of


semiconductor devices that are interconnected to store
an array of binary data.

Once binary data is stored in the ROM, it can be read


out whenever desired, but the data that is stored cannot
be changed under normal operating conditions.

(1)Use "mask" to program ROM


(2)EPROM (Erasable Programmable) UV light
(3)EEPROM (Electrically Erasable)

Unit 9

18

Read-Only Memories (2/6)


Can be used to realize multiple functions

Inputs
A
B
C

ROM
8 words
4 bits

F 0 F1 F 2 F 3
Outputs

Unit 9

A B C F 0 F1 F 2 F 3
0 0 0 1 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 1 1 1 1 1

Stored
in ROM
(23 words of
4 bits each)

F 0 m0 m1 m5 m7
F 1 m 2 m3 m 4 m5 m 7
F 2 m0 m1 m3 m4 m5 m6 m7
F 3 m6 m7

19

Read-Only Memories (3/6)

General Fo rm
:
:
inputs
:

ROM
2n words
m bits

m
outputs

Unit 9

n inputs
0 0 0
0 0 1
:
:
:
:
:
:
:
:
1 1 1

m outputs
F 0 Fm 1
0 0 1
0
:
:
:
:
:
: 2n words
:
:
:
:
1 0 1
0

20

Read-Only Memories (4/6)


A

w0
w1
w2
w3

A
B

:
n
inputs :

w0
w1
w2
w3

n:

decoder

2 :
words

Memory array
2n words m bits

m
Basic ROM structure
Unit 9

outputs
21

Read-Only Memories (5/6)


Internal structure of a ROM
A B C F0
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

F1 F 2
0
1
0
1
1
1
1
0
1
0
0
0
1
1
1
0

F3
0
0
1
1
0
1
1
1

Equivalent OR gate for F0

Unit 9

m0
m1
m4
m6

F0

F0 m0 m1 m4 m6

22

Read-Only Memories (6/6)

Example: hexadecimal-to-ASCII code converter

Unit 9

23

Programmable Logic Devices (1/7)

Programmable Logic Device (PLD)

A general name for a digital integrated circuit capable of being


programmed to provide a variety of different logic functions

Combinational PLD

Programmable Logic Array (PLA)


Programmable Array Logic (PAL)

Sequential PLD

Unit 9

Complex Programmable Logic Device (CPLD)


Field-Programmable Gate Array (FPGA)

24

Programmable Logic Devices (2/7)


PLAs: n m realizes m functions with n inputs

AND
Array
(plane)

OR
Array
(plane)

not 2n

2 - level SOP implementation


ROM directly implements truth table
Unit 9

25

Programmable Logic Devices (3/7)


A' B'
AC'
B
BC'
AC

Unit 9

A
0
1

B C
0
0
1
1 0
1

F0
1
1
0
0
0

F1 F2
0 1
1 0
1 0
0 1
0 0

F3
0
0
1
0
1

26

Programmable Logic Devices (4/7)


Example
F1 m 2,3,5, 7,8,9,10,11,13,15
F2 m 2,3,5, 6, 7,10,11,14,15
F3 m 6, 7,8,9,13,14,15
Minimized multiple output expressions (using K-Map)
F1 a'bd abd ab'c' b'c
F2 c a'bd
F3 bc ab'c' abd

PLA table

Unit 9

a
0
1
1

b
1
1
0
0

0
1
1
1

d
1
1

F1
1
1
1
1
0
0

F2
1
0
0
0
1
0

F3
0
1
1
0
0
1
27

Programmable Logic Devices (5/7)


a
0
1
1

b
1
1
0
0

0
1
1
1

d
1
1

F1
1
1
1
1
0
0

abcd 0111

0001
1001

F2
1
0
0
0
1
0

F3
0
1
1
0
0
1

Inputs
b
c

PLA structure

Word
line

F1 F2 F3
Outputs

row 1,5,6 selected, F1 1(1st) 0(5th) 0(6th) 1


F2 1 1 0 1
F3 0 0 1 1
no rows selected, F1F2F3 000
row 3 selected, F1F2F3 101

Mask programmable PLA


Field programmable PLA
Unit 9

28

Programmable Logic Devices (6/7)


PALs: n m realizes m functions with n inputs
AND array programmable

A special case of PLA:

OR
array
NOT
programmable

Unit 9

29

Programmable Logic Devices (7/7)

Implementation of a full adder using a PAL

Unit 9

30

Complex Programmable Logic Devices (1/2)

Instead of a single PAL or PLA on a chip, many PALs


or PLAs can be placed on a single CPLD chip and
interconnected.

When storage elements such as flip-flops are also


included on the same integrated circuit (IC), a small
digital system can be implemented with a single CPLD.

Unit 9

31

Complex Programmable Logic Devices (2/2)

Xilinx XCR3064XL CPLD

CPLD function block and macrocell


Signals generated in a PLA can
be routed to an I/O pin through
a macrocell.

Unit 9

32

Field-Programmable Gate Arrays (1/8)

A field-programmable gate array (FPGA) is an IC that


contains an array of identical logic cells with
programmable interconnections.

The user can program the functions realized by each


logic cell and the connections between the cells.

The interior of the FPGA consists of an array of logic


cells, also called configurable logic blocks (CLBs). The
array of CLBs is surrounded by a ring of I/O interface
blocks. These I/O blocks connect the CLB signals to IC
pins.

Unit 9

33

Field-Programmable Gate Arrays (2/8)

CLB: configurable logic block


Layout of a typical FPGA
Unit 9

34

Field-Programmable Gate Arrays (3/8)

Implementation of a lookup table (LUT)

Unit 9

A four-input LUT is essentially a reprogrammable ROM with 16


1-bit words.

35

Field-Programmable Gate Arrays (4/8)

In order to implement a switching function of more than


three variables using 3-variable function generators, the
function must be decomposed into subfunctions where
each subfunction requires only three variables.

Example: expand the following function about the


variable a (based on Shannons expansion theorem):
Since f (a, b, c, d) = a'f (0, b, c, d) + a f (1, b, c, d) = a'f0 + a f1,
we have f (a, b, c, d) = c'd'+ a'b'c + bcd + ac'
= a'(c'd'+ bc + bcd) + a(c'd'+ bcd + c')
= a'(c'd'+ b'c + cd) + a(c'+ bd) = a'f0 + a f1

Unit 9

36

Field-Programmable Gate Arrays (5/8)

Function expansion using a K map

Unit 9

37

Field-Programmable Gate Arrays (6/8)

General form of Shannons expansion theorem for


expanding an n-variable function about the variable xi
f (x1, x2, . . . , xi1, xi, xi+1, . . . , xn)
= xi' f (x1, x2, . . . , xi1, 0, xi+1, . . . , xn) +
xi f (x1, x2, . . . , xi1, 1, xi+1, . . . , xn)
= x i' f 0 + x i f 1

where f0 is the (n 1)-variable function obtained by


setting xi to 0 in the original function and f1 is the (n
1)-variable function obtained by setting xi to 1 in the
original function

Unit 9

38

Field-Programmable Gate Arrays (7/8)


Realization of a 5-variable function with 4-variable function
generators (FGs)

Unit 9

39

Field-Programmable Gate Arrays (8/8)


Realization of a 6-variable function with 4-variable function
generators (FGs)

G(a, b, c, d, e, f)
= a'G0 + aG1
G0 = b'G00 + bG01
G1 = b'G10 + bG11

Unit 9

40