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Unit 9
Outline
Unit 9
Multiplexers (1/6)
Z = AI0 + AI1
Unit 9
Multiplexers (2/6)
I0
I1
I2
I3
4-to-1
MUX
8-to-1
MUX
I1
Unit 9
I0
I2n-1
I2
I3
A B C
I0
A
I0
I1
I7
A A' B B'
2n-to-1
MUX
n control inputs
8 1 : Z A' B' C' I 0 A' B' CI1 A' BC' I 2 A' BCI3
AB' C' I 4 AB' CI5 ABC' I 6 ABCI7
2 n 1
2n 1 : Z m k I k
k 0
Multiplexers (3/6)
Quad multiplexer to select data
2:1 Mux
X0 S
1
2:1 Mux
Z0
D
X1 S
1
Y1 S
2
Y0 S
2
C
ENB
2:1 Mux
Z1
X2 S
1
Y2 S
2
C
ENB
2:1 Mux
Z2
X3 S
1
Z3
D
Y3 S
2
C
ENB
ENB
EN
A
Unit 9
Multiplexers (4/6)
4-to-1 MUX to realize 3-variable function
Ex :
I0
I1
Unit 9
I2
I3
D
4-to-1
MUX
S1
S2
Multiplexers (5/6)
8-to-1 MUX to realize 4-variable function
F = ABC + ABC +
ABD + ACD +
BCD
A B C
= ABC(D+D) +
ABC (D+D) +
AB(C+C)D +
A(B+B)CD +
(A+A)BCD
Unit 9
1
D
I0
I1
0
1
D
D
D
I2
I3 8 to 1
I4 MUX
I5
I6
I7
A B C
7
Multiplexers (6/6)
I0
I1
I2
I3
I4
I5
I6
I7
Unit 9
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B C
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
D F
0 1
1 1
0 0
1 1
0 0
1 0
0 1
1 1
0 1
1 0
0 0
1 1
0 1
1 0
0 1
1 0
D
0
1
D
D
D
D
V1 V2
0 0
0 0
Vn
0
1
F
0 0 1 1
0 1 0 1
0 Vn Vn 1
Unit 9
Unit 9
10
S2
S1
S2
11
2. Chip I/O
Unit 9
12
Decoders (1/4)
A decoder generates all of the minterms, and exactly one of
the output lines will be 1 for each combination of the values
of the input variables.
m0
m1
m2
m3
m4
m5
m6
m7
y7 abc
m0
m1
m7
3-to-8 decoder
Unit 9
13
Decoders (2/4)
A
y0
y1
y1
y3
B
Unit 9
2-to-4
decoder
y0
y2
y0
y1
y2
y3
y7
14
Decoders (3/4)
BCD input
4-to-10 decoder
m9 m8m7m6m5m4m3 m2m1m0
Unit 9
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Decimal output
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
8
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
15
Decoders (4/4)
Realization of a multiple-output circuit using a decoder
F1 m1 m2 m4 F2 m4 m7 m9
A
B
C
D
Unit 9
0
1
2
4-to-10 3
Decoder 4
5
6
7
8
9
m1 '
m2 '
m4 '
F1
m7'
m9'
F2
16
Encoders
If input yi is 1 and the other inputs are 0, then abc outputs represent a binary number equal to i.
If more than one input is 1, the highest numbered input determines the output.
An extra output, d, is 1 if any input is 1, otherwise d is 0. The d signal is needed to distinguish the
case of all 0 inputs from the case where only y0 is 1.
Unit 9
y0
y1
y2
y3
y
4
y5
y6
y7
17
Unit 9
18
Inputs
A
B
C
ROM
8 words
4 bits
F 0 F1 F 2 F 3
Outputs
Unit 9
A B C F 0 F1 F 2 F 3
0 0 0 1 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 1 1 1 1 1
Stored
in ROM
(23 words of
4 bits each)
F 0 m0 m1 m5 m7
F 1 m 2 m3 m 4 m5 m 7
F 2 m0 m1 m3 m4 m5 m6 m7
F 3 m6 m7
19
General Fo rm
:
:
inputs
:
ROM
2n words
m bits
m
outputs
Unit 9
n inputs
0 0 0
0 0 1
:
:
:
:
:
:
:
:
1 1 1
m outputs
F 0 Fm 1
0 0 1
0
:
:
:
:
:
: 2n words
:
:
:
:
1 0 1
0
20
w0
w1
w2
w3
A
B
:
n
inputs :
w0
w1
w2
w3
n:
decoder
2 :
words
Memory array
2n words m bits
m
Basic ROM structure
Unit 9
outputs
21
F1 F 2
0
1
0
1
1
1
1
0
1
0
0
0
1
1
1
0
F3
0
0
1
1
0
1
1
1
Unit 9
m0
m1
m4
m6
F0
F0 m0 m1 m4 m6
22
Unit 9
23
Combinational PLD
Sequential PLD
Unit 9
24
AND
Array
(plane)
OR
Array
(plane)
not 2n
25
Unit 9
A
0
1
B C
0
0
1
1 0
1
F0
1
1
0
0
0
F1 F2
0 1
1 0
1 0
0 1
0 0
F3
0
0
1
0
1
26
PLA table
Unit 9
a
0
1
1
b
1
1
0
0
0
1
1
1
d
1
1
F1
1
1
1
1
0
0
F2
1
0
0
0
1
0
F3
0
1
1
0
0
1
27
b
1
1
0
0
0
1
1
1
d
1
1
F1
1
1
1
1
0
0
abcd 0111
0001
1001
F2
1
0
0
0
1
0
F3
0
1
1
0
0
1
Inputs
b
c
PLA structure
Word
line
F1 F2 F3
Outputs
28
OR
array
NOT
programmable
Unit 9
29
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30
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31
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32
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33
34
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35
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36
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37
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38
Unit 9
39
G(a, b, c, d, e, f)
= a'G0 + aG1
G0 = b'G00 + bG01
G1 = b'G10 + bG11
Unit 9
40