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FPGA Digital Design Lab Manual

2014-15

Digital design FPGA lab manual

2014-15

CONTENTS

18

18

2. MULTIPLIERS

I) Array Multipliers18……………………………………………………………………………………………………… 18

A) Unsigned number multiplier (4-bit)

B) Signed array multiplier

23

 3. Magnitude Comparator 4. Linear Feedback Shift Register (LSFR) 5. Universal Shift Register 31 34 37 6. 3-bit Arbitrary Counter 43 46 7. Sequence Detector A) B) Design of sequence detector with and without overlapping using moore state machine………46 Design of sequence detector with and without overlapping using Melay state machine………55 8. FIFO and LIFO 64 A) B) First In First Out (FIFO)…………………….……………………………………………………………………….64 Last In First OUT (LIFO)………………………………………………………………………………………… 69 9. FSM Model For Coin Operated Telephone System 75 APPENDIX A Tutorial for Xilinx FPGA flow. 81

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NOTE:

All the experiments in this manual are designed using Verilog HDL, simulated using Xilinx isim and ported to Xilinx Spartan 3E FPGA using Xilinx ISE14.2 design suite.

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Aim: To design and verify the working of an 8-bit ripple carry adder.

Block Diagram:

Theory:

shown above. The corresponding Boolean expressions given here are to construct a ripple carry

adder. In the half adder circuit the sum and carry bits are defined as,

Sum = A B Carry = AB

In the full adder circuit the Sum and Carry output is defined by inputs A, B and Carry in (C) as

Sum=ABC + ABC + ABC + ABC Sum= ABC + ABC + ABC + ABC = (AB + AB) C + (AB + AB) C = (A B) C + (A B) C =A B C Carry= ABC + ABC + ABC + ABC = AB + (AB + AB) C = AB + (A B) C

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Verilog Code:

module cra(a,b,cin,sum,cout); input [7:0] a,b; input cin; output [7:0] sum; output cout; wire c1,c2,c3,c4,c5,c6,c7; assign sum[0] = a[0] ^ b[0] ^ cin; assign c1 = a[0] & b[0] | b[0] & cin | a[0] & cin;

assign sum[1] = a[1] ^ b[1] ^ c1; assign c2 = a[1] & b[1] | b[1] & c1 | a[1] & c1;

assign sum[2] = a[2] ^ b[2] ^ c2; assign c3 = a[2] & b[2] | b[2] & c2 | a[2] & c2;

assign sum[3] = a[3] ^ b[3] ^ c3; assign c4 = a[3] & b[3] | b[3] & c3 | a[3] & c3;

assign sum[4] = a[4] ^ b[4] ^ c4; assign c5 = a[4] & b[4] | b[4] & c4 | a[4] & c4;

assign sum[5] = a[5] ^ b[5] ^ c5; assign c6 = a[5] & b[5] | b[5] & c5 | a[5] & c5;

assign sum[6] = a[6] ^ b[6] ^ c6; assign c7 = a[6] & b[6] | b[6] & c6 | a[6] & c6;

assign sum[7] = a[7] ^ b[7] ^ c7;
assign cout = a[7] & b[7] | b[7] & c7 | a[7] & c7;
endmodule

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Test Bench:

module tb; reg [7:0] a,b; reg cin; wire [7:0] sum; wire cout; cra R1 (a,b,cin,sum,cout); initial begin

a=8'b0000_0010;

b=8'b0001_0100;

cin=0;

#100;

a=8'b0000_0010;

b=8'b0001_0100;

cin=0;

#100;

a=8'b0000_0010;

b=8'b0011_0100;

cin=0;

#100;

a=8'b0000_0010;

b=8'b0011_0100;

cin=0;

#100;

a=8'b0000_0010;

b=8'b1111_0100;

cin=0;

#100;

a=8'b0000_1111;

b=8'b0000_0100;

cin=0;

#100;

end

endmodule

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Simulation results:

FPGA implementation- Design summary:

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Aim: To design and verify the working of 8-bit carry look ahead adder.

Block Diagram:

Theory:

A

adder improves speed by reducing the amount of time required to determine carry bits. It can

be

calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits (see adder for detail on ripple carry adders). The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits.

contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is

Carry lookahead logic uses the concepts of generating and propagating carries. The addition

of

of

if both A and B are 1. If we write G(A+B) to represent the binary predicate that is true if and only if A+B generates, we have: G (A, B) =A.B

two 1-digit inputs A and B is said to generate if the addition will always carry, regardless

whether there is an input carry In the case of binary addition, (A+B) generates if and only

The addition of two 1-digit inputs A and B is said to propagate if the addition will carry whenever there is an input carry. In the case of binary addition, (A+B) propagates if and only if at least one of A or B is 1. If we write P (A,B) to represent the binary predicate that is true if and only if A+B propagates, we have: P (A, B) =A^B

Hence the carry can be calculated as C i+1 =G i + (P i +C i ).

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Verilog Code:

//Design Carry look ahead adder using 4-bit module carry_look_adder(a,b,cin,sum,cout); input [3:0] a,b; input cin; output [3:0] sum; output cout; wire g0,p0,g1,p1,g2,p2,g3,p3; wire c1,c2,c3; assign g0 = a[0] & b[0]; assign p0 = a[0] ^ b[0]; assign sum[0] = a[0] ^ b[0] ^ cin; assign c1 = g0 | (p0 & cin);

assign g1 = a[1] & b[1]; assign p1 = a[1] ^ b[1]; assign sum[1] = a[1] ^ b[1] ^ c1; assign c2 = g1 | (p1 & c1);

assign g2 = a[2] & b[2]; assign p2 = a[2] ^ b[2]; assign sum[2] = a[2] ^ b[2] ^ c2; assign c3 = g2 | (p2 & c2);

assign g3 = a[3] & b[3]; assign p3 = a[3] ^ b[3]; assign sum[3] = a[3] ^ b[3] ^ c3; assign cout = g3 | (p3 & c3); endmodule

Test Bench:

module tb; reg [3:0] a,b; reg cin; wire [3:0] sum; wire cout; carry_look_adder R1 (a,b,cin,sum,cout); initial begin

a=4'b1100;

b=4'b1100;

cin=0;

#100;

a=4'b1110;

b=4'b1100;

cin=0;

end

initial

\$monitor("a=%b,b=%b",a,b);

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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Aim: To design and verify the working of an 8-bit carry skip adder.

Block Diagram:

C out

A
16:13
B
16:13
A
12:9 B 12:9
A 8:5
B 8:5
A 4:1
B 4:1
P
16:13
P
12:9
P
8:5
P
4:1
1
1
1
1
C
C 8
C 4
12
0
+ 0
+ 0
+ 0
+
S
16:13
S
12:9
S
8:5
S
4:1

Theory:

The above figure shows a carry skip adder built from 4-bit groups. The rectangles compute the bitwise propagate and generate signals and also contain a 4-input AND gate for the propagate signal of the 4-bit group. The skip multiplexer selects the group carry- in if the group propagate is true or the ripple adder carry-out otherwise. The critical path begins with generating a carry from bit 1, and then propagating it through the remainder of the adder. The carry must ripple through the next three bits, but then may skip across the next two 4-bit blocks. Finally, it must ripple through the final 4-bit block to produce the sums. The 4-bit ripple chains at the top of the diagram determine if each group generates a carry. The carry skip chain in the middle of the diagram skips across 4-bit blocks. Finally, the 4-bit ripple chains with the dark lines represent the same adders that can produce a carry-out when a carry-in is bypassed to them.

C in

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Program:

module CSA_task(Sum,Cout,A,B,Cin); output reg [7:0] Sum; output reg Cout; input [7:0] A,B; input Cin; reg w1; always @ (A or B or Cin) begin CSA_4bit (Sum[3:0],w1,A[3:0],B[3:0],Cin); CSA_4bit (Sum[7:4],Cout,A[7:4],B[7:4],w1); end task CSA_4bit; output [3:0] sum; output cout; input [3:0] a,b; input cin; reg [3:0] c,g,p; reg sel; begin

c[0]=cin;

sum[0]=a[0]^b[0]^c[0];

g[0]=a[0]&b[0];

p[0]=a[0]|b[0];

c[1]=g[0] | (p[0]&c[0]);

sum[1]=a[1]^b[1]^c[1];

g[1]=a[1]&b[1];

p[1]=a[1]|b[1];

c[2]=g[1] | (p[1]&(g[0] | (p[0]&c[0])));

sum[2]=a[2]^b[2]^c[2];

g[2]=a[2]&b[2];

p[2]=a[2]|b[2];

c[3]=g[2] | (p[2]&(g[1] | (p[1]&(g[0] | (p[0]&c[0])))));

sum[3]=a[3]^b[3]^c[3];

g[3]=a[3]&b[3];

p[3]=a[3]|b[3];

cout=g[3] | (p[3]&(g[2] | (p[2]&(g[1] | (p[1]&(g[0] | (p[0]&c[0])))))));

sel=(p[0]&p[1]&p[2]&p[3]);

if(sel)

cout<=cout;

else

cout<=cin;

end

endmodule

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Testbench:

module CSA_task_tb; wire [7:0] Sum; wire Cout; reg [7:0] A,B; reg Cin; CSA_task CSA1(Sum,Cout,A,B,Cin); initial begin

A=8'b00000000;B=8'b00000000;Cin=0;

#100;

A=8'b00001111;B=8'b00001111;Cin=1;

#100;

A=8'b11110000;B=8'b11110000;Cin=0;

#100;

A=8'b11001100;B=8'b11001100;Cin=1;

#100;

A=8'b11001100;B=8'b00110011;Cin=0;

#100;

A=8'b10101010;B=8'b10101010;Cin=1;

#100;

A=8'b10101010;B=8'b01010101;Cin=0;

#100;

A=8'b11111111;B=8'b11111111;Cin=1;

end

endmodule

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Simulation results:

FPGA implementation- Design summary:

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Digital design FPGA lab manual

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1.4 4-BIT BCD ADDER AND SUBTRACTOR

Aim: To design and verify the working of a 4-bit BCD adder and subtractor.

Block Diagram:

C= K+ Z1Z3+ Z2Z3

Theory: IC 7383 is a binary adder digital circuit that produces arithmetic sum of two binary

numbers. It can be constructed by cascading full adders; the output carry of each adder is connected to the input carry of the next full adder in the chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from left to right, the subscript 0 denoting the least significant bit. The carries are connected in chain through the full adder. The input carry to the adder is ‘C0’ and is rippled through the circuit to ‘C4’.

The truth table of the adder is as shown in the next page.

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TABLE 1: IMPLEMENTATION OF BCD ADDER TRUTH TABLE

Binary Sum
BCD Sum
Decimal
K
Z8
Z4
Z2
Z1
C
S8
S4
S2
S1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
2
0
0
0
1
1
0
0
0
1
1
3
0
0
1
0
0
0
0
1
0
0
4
0
0
1
0
1
0
0
1
0
1
5
0
0
1
1
0
0
0
1
1
0 6
0
0
1
1
1
0
0
1
1
1 7
0
1
0
0
0
0
1
0
0
0
8
0
1
0
0
1
0
1
0
0
1
9
0
1
0
1
0
1
0
0
0
0
10
0
1
0
1
1
1
0
0
0
1
11
0
1
1
0
0
1 0
0
1
0
12
0
1
1
0
1
1 0
0
1
1
13
0
1
1
1
0
1 0
1
0
0
14
0
1
1
1
1
1 0
1
0
1
15
1
0
0
0
0
1 0
1
1
0
16
1
0
0
0
1
1 0
1
1
1
17
1 0
0
1
0 0
1 0
1
0
18
1 0
0
1
1 0
1 0
1
1
19

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Program:

or(output_carry,carry_out,w1,w2);

or(c_out,carry_out,c_out);

endmodule

module adder_4bit(carry,sum,a,b,cin); output carry; input [3:0] sum; input [3:0] a,b; input c_in; assign {carry,sum}=a+b+cin; endmodule

Testbench

module tb_bcd; reg [3:0] addend; reg [3:0] augend; reg carry_in; wire [3:0] sum; wire output_carry; bcd_adder uut ( .sum(sum), .output_carry(output_carry), .addend(addend), .augend(augend), .carry_in(carry_in)

);

initial begin addend =3'b0001; augend = 3'b1110;

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carry_in = 0;

#5;

addend =3'b1110; augend = 3'b0010; carry_in = 1;

#5;

end

Simulation Results:

FPGA implementation- Design summary:

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Exp 2: MULTIPLIERS

Digital design FPGA lab manual

2014-15

2.1 ARRAY MULTIPLIERS

2.1A UNSIGNED NUMBER MULTIPLIER (4-BIT)

Aim: To design and verify the working of unsigned array multiplier.

Circuit/Block Diagram:

Theory:

Digital multiplication entails a sequence of additions carried out on partial products. In Array multiplier partial products are independently computed in parallel. Let us consider two binary numbers A and B of m and n bits respectively,

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There are m*n summands that are produced in parallel by a set of m*n numbers of AND gates. If m = n Then it will require n(n-2) full adders, n half-adders and n*n AND gates and worst case delay would be (2n+1)td .where td is the time delay of gates.

Basic cell of a parallel array multiplier:-

Consider computing the product of two 4-bit integer numbers given by A3A2A1A0 (multiplicand) and B3B2B1B0 (multiplier). The product of these two numbers can be formed as shown below.

Each of the ANDed terms is referred to as a partial product. The final product (the result) is formed by accumulating (summing) down each column of partial products. Any carries must be propagated from the right to the left across the columns.

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Program:

module arraymultiplierunsigned( input [3:0] a, input [3:0] b, output wire [7:0] product );

wire p0,p1,p2,p3,p4,p5,p6,p7; wire r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15; wire c1,c2,c3,c4; wire q1,q2,q3,q4,q5,q6; wire s1,s2; wire c11,c22,c33,c44,c55; and1 a1(.x(a[0]),.y(b[0]), .w(p0)); and1 a2(.x(a[1]),.y(b[0]), .w(r1)); and1 a3(.x(a[0]),.y(b[1]), .w(r2)); and1 a4(.x(a[0]),.y(b[2]), .w(r3)); and1 a5(.x(a[1]),.y(b[1]), .w(r4)); and1 a6(.x(a[2]),.y(b[0]), .w(r5)); and1 a7(.x(a[0]),.y(b[3]), .w(r6)); and1 a8(.x(a[1]),.y(b[2]), .w(r7)); and1 a9(.x(a[2]),.y(b[1]), .w(r8)); and1 a10(.x(a[3]),.y(b[0]), .w(r9)); and1 a11(.x(a[1]),.y(b[3]), .w(r10)); and1 a12(.x(a[2]),.y(b[2]), .w(r11)); and1 a13(.x(a[3]),.y(b[1]), .w(r12)); and1 a14(.x(a[2]),.y(b[3]), .w(r13)); and1 a15(.x(a[3]),.y(b[2]), .w(r14)); and1 a16(.x(a[3]),.y(b[3]), .w(r15)); ha h1(.e(r1),.f(r2),.g(p1),.h(c1)); ha h2(.e(r3),.f(r4),.g(s1),.h(c2)); ha h3(.e(r6),.f(r7),.g(s2),.h(c3)); ha h4(.e(q3),.f(c22),.g(p4),.h(c4)); fa i1(.j(r5),.k(s1),.l(c1),.m(p2),.n(c11)); fa i2(.j(r8),.k(s2),.l(c2),.m(q1),.n(c33)); fa i3(.j(r9),.k(q1),.l(c11),.m(p3),.n(c22)); fa i4(.j(r11),.k(r10),.l(c3),.m(q2),.n(q4)); fa i5(.j(r12),.k(q2),.l(c33),.m(q3),.n(c44)); fa i6(.j(r14),.k(r13),.l(q4),.m(q5),.n(q6)); fa i7(.j(q5),.k(c44),.l(c4),.m(p5),.n(c55)); fa i8(.j(r15),.k(q6),.l(c55),.m(p6),.n(p7));

assign product[0]=p0; assign product[1]=p1; assign product[2]=p2; assign product[3]=p3; assign product[4]=p4; assign product[5]=p5; assign product[6]=p6;

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assign product[7]=p7;

endmodule

module and1(input x, input y, output wire w);

assign w=x*y;

endmodule

module ha(input e, input f, output wire g, output wire h);

assign g=e^f;

assign h=e*f;

endmodule

module fa (input j, input k, input l, output wire m, output wire n);

assign m=j^k^l; assign n=(j*k)+(k*l)+(j*l);

endmodule

Testbench:

module tbarraymulunsign;

reg [3:0] a; reg [3:0] b; wire [7:0] product; arraymultiplierunsigned uut (.a(a), .b(b), .product(product));

initial begin

a =4'b1010;

b = 4'b0101;

#20;

a=4'b1111;

b=4'b1111;

#100;

end

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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2.1B SIGNED ARRAY MULTIPLIER (BAUGH-WOOLEY MULTIPLIER)

Aim: To design and verify the working of 4-bit signed array multiplier.

Circuit/Block Diagram:

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Theory:

The multiplication of signed numbers is done using the Baugh-Wooley algorithm. This is an efficient algorithm to handle signed bits. Consider two n-bit numbers A and B to be multiplied.

Multiplication of 2's complement numbers at first might seem more difficult because some partial products are negative and must be subtracted.The most significant bit of a 2's complement number has a negative weight. Hence, the product is: two of the partial products have negative weight and thus should be subtracted rather than added. The Baugh-Wooley multiplier algorithm handles subtraction by taking the 2's complement of the terms to be subtracted (i.e., inverting the bits and adding one). The upper parallelogram represents the unsigned multiplication of all but the most significant bits of the inputs. The next row is a single bit corresponding to the product of the most significant bits. The next two pairs of rows are the inversions of the terms to be subtracted. Each term has implicit leading and trailing 0's, which are inverted to leading and trailing Is. Extra Is must be added in the least significant column when taking the 2's complement. The multiplier delay depends on the number of partial product rows to be summed. The modified Baugh-Wooley multiplier reduces this number of partial products by pre-computing the sums of the constant I's and pushing some of the terms upward into extra columns. The AND gates are replaced by NAND gates in the hatched cells and I's are added in place of O's at a few of the unused inputs. The signed and unsigned arrays are so similar that a single array can be used for both purposes if XOR gates are used to conditionally invert some of the terms depending on the mode.

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Program:

module arraymultipliersigned( wire [19:0] x; wire [20:1] y; wire [4:1] co; assign y[4:1]=1'b0; assign x[3:0]=1'b0; assign y[8]=1'b0; assign y[12]=1'b0; assign y[16]=1'b0; assign y[20]=1'b1;

input [3:0] a,

input [3:0] b,

output wire[7:0] p

);

white w1(.a(a[0]),.b(b[0]),.ci(x[0]),.si(y[1]),.so(p[0]),.c_o(x[4])); white w2(.a(a[1]),.b(b[0]),.ci(x[1]),.si(y[2]),.so(y[5]),.c_o(x[5])); white w3(.a(a[2]),.b(b[0]),.ci(x[2]),.si(y[3]),.so(y[6]),.c_o(x[6])); white w4(.a(a[0]),.b(b[1]),.ci(x[4]),.si(y[5]),.so(p[1]),.c_o(x[8])); white w5(.a(a[1]),.b(b[1]),.ci(x[5]),.si(y[6]),.so(y[9]),.c_o(x[9])); white w6(.a(a[2]),.b(b[1]),.ci(x[6]),.si(y[7]),.so(y[10]),.c_o(x[10])); white w7(.a(a[0]),.b(b[2]),.ci(x[8]),.si(y[9]),.so(p[2]),.c_o(x[12])); white w8(.a(a[1]),.b(b[2]),.ci(x[9]),.si(y[10]),.so(y[13]),.c_o(x[13])); white w9(.a(a[2]),.b(b[2]),.ci(x[10]),.si(y[11]),.so(y[14]),.c_o(x[14])); white w10(.a(a[3]),.b(b[3]),.ci(x[15]),.si(y[16]),.so(y[19]),.c_o(x[19])); grey g1(.a(a[3]),.b(b[0]),.ci(x[3]),.si(y[4]),.so(y[7]),.c_o(x[7])); grey g2(.a(a[3]),.b(b[1]),.ci(x[7]),.si(y[8]),.so(y[11]),.c_o(x[11])); grey g3(.a(a[3]),.b(b[2]),.ci(x[11]),.si(y[12]),.so(y[15]),.c_o(x[15])); grey g4(.a(a[0]),.b(b[3]),.ci(x[12]),.si(y[13]),.so(p[3]),.c_o(x[16])); grey g5(.a(a[1]),.b(b[3]),.ci(x[13]),.si(y[14]),.so(y[17]),.c_o(x[17])); grey g6(.a(a[3]),.b(b[3]),.ci(x[14]),.si(y[15]),.so(y[18]),.c_o(x[18])); fa1 f1(.a(x[16]),.b(y[17]),.ci(1'b1),.s(p[4]),.co(co[1])); fa1 f2(.a(x[17]),.b(y[18]),.ci(co[1]),.s(p[5]),.co(co[2])); fa1 f3(.a(x[18]),.b(y[19]),.ci(co[2]),.s(p[6]),.co(co[3])); fa1 f4(.a(x[19]),.b(y[20]),.ci(co[3]),.s(p[7]),.co(co[4]));

endmodule

module white(input a, input b, input ci, input si, output wire so, output wire c_o); wire s; assign s=a*b; fa1 g1(.a(s),.b(ci),.ci(si),.s(so),.co(c_o)); endmodule

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module grey(input a, input b, input ci, input si, output wire so, output wire c_o); wire s;

assign s=(~(a*b)); fa1 g2(.a(s),.b(ci),.ci(si),.s(so),.co(c_o));

endmodule

module fa1(input a, input b, input ci, output wire s, output wire co);

assign s=a^b^ci; assign co=(a*b)+(b*ci)+(ci*a); endmodule

Testbench:

module tbarraymulsign; reg [3:0] a; reg [3:0] b;

wire [7:0] p;

arraymultipliersigned uut (
.a(a),
.b(b),
.p(p)
);
initial begin
a = 4'b1110;
b = 4'b0010;
#20;
a=4'b0011;

b=4'b0010;

end

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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2.1C BOOTH MULTIPLIER (RADIX - 4)

Aim: To design and verify booth multiplier.

Program:

module multiplier(prod, busy, mc, mp, clk, start); output [15:0] prod; output busy; input [7:0] mc, mp; input clk, start; reg [7:0] A, Q, M; reg Q_1; reg [3:0] count; wire [7:0] sum, difference; always @(posedge clk)

begin

 if (start) begin A <= 8'b0; M <= mc; Q <= mp;

Q_1 <= 1'b0;

count <= 4'b0;

end

else begin case ({Q[0], Q_1}) 2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q}; 2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};

default: {A, Q, Q_1} <= {A[7], A, Q};

endcase

count <= count + 1'b1;

end

end

alu adder (sum, A, M, 1'b0);

alu subtracter (difference, A, ~M, 1'b1); assign prod = {A, Q}; assign busy = (count < 8);

endmodule

//The following is an alu. //It is an adder, but capable of subtraction:

//Recall that subtraction means adding the two's complement--

//a - b = a + (-b) = a + (inverted b + 1)

//The 1 will be coming in as cin (carry-in)

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module alu(out, a, b, cin); output [7:0] out; input [7:0] a; input [7:0] b; input cin; assign out = a + b + cin;

endmodule

Testbench:

module testbench; reg clk, start; reg [7:0] a, b; wire [15:0] ab; wire busy;

multiplier multiplier1(ab, busy, a, b, clk, start); initial begin clk = 0; \$display("first example: a = 3 b = 17");

a = 3; b = 17; start = 1; #50 start = 0; #80 \$display("first example done");

\$display("second example: a = 7 b = 7");

a = 7; b = 7; start = 1; #50 start = 0; #80 \$display("second example done");

\$finish;

end

always #5 clk = !clk; always @(posedge clk) \$strobe("ab: %d busy: %d at time=%t", ab, busy, \$stime);

endmodule

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Simulation results:

FPGA implementation- Design summary:

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Exp 3: MAGNITUDE COMPARATOR

Digital design FPGA lab manual

2014-15

Aim: To design and verify the working of magnitude comparator.

Circuit /Block Diagram:

Theory:
A magnitude comparator is a combinational circuit that compares the magnitude of 2 numbers A and
B. It generates one of the following outputs,
1.
A=B

2. A<B

3. A>B

To implement the magnitude comparator EXOR, AND, NOT gates are used.

Equality: (A=B)

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The binary numbers A and B will be equal if all the pairs of significant digits of both numbers are equal. The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are equal.

Inequality: (A>B or A<B)

In order to manually determine the greater of two binary numbers, the relative magnitudes of
pairs of significant digits, starting from the most significant bit, gradually proceeding towards
lower significant bits until an inequality is found. When an inequality is found, if the
corresponding bit of A is 1 and that of B is 0 then conclude that A>B. (A>B) and (A < B) are
output binary variables, which are equal to 1 when A>B or A<B respectively.
Program:
module compare(A,B,y);
input [3:0] A,B;
output [2:0] y;
reg y;
always @(A or B)
if(A==B)
y=3’b001;
else if(A<B)
y=3’b010;
else
y=3’b100;
endmodule
Testbench:
module tbcompare1;
reg [3:0] A;
reg [3:0] B;
wire [2:0] y;
compare uut (
.A(A),
.B(B),
.y(y)
);
initial begin
A = 4'b0001;
B
= 4'b1110;
#5;

end

endmodule

A = 4'b0001;

B = 4'b0001;

#5;

A = 4'b1111;

B = 4'b1110;

#5;

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Simulation results:

FPGA implementation- Design summary:

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Exp 4: 4-Bit Linear Feedback Shift Register (LSFR)

Digital design FPGA lab manual

2014-15

Aim: To design and verify the working of 4-bit LFSR.

Circuit/Block Diagram:

Theory:

A

of

linear feedback shift register (LFSR) is a shift register whose input bit is a linear function

its previous state.

The most commonly used linear function of single bits is exclusive-or (XOR). Thus, an LFSR

is

shift register value.

most often a shift register whose input bit is driven by the XOR of some bits of the overall

The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.

Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations

of

LFSRs are common.

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Program:

module lfsr_1(output reg[3:0] out=4'b0000, input clk, input rst );

wire feedback; parameter A=4'b1101; assign feedback = (A[3] ^ A[2]); always @(posedge clk, posedge rst) begin if (rst) out <= A; else

out <= {A[3:1],feedback}; end

endmodule

Testbench:

module tblfsr_1; reg clk; reg rst; wire [3:0] out;

lfsr_1 uut ( .out(out),

.clk(clk),

.rst(rst)

);

always begin

clk=1;

#5;

clk=0;

#5;

end

initial begin

rst = 1;

#10;

rst=0;

#10;

end

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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Exp 4: UNIVERSAL SHIFT REGISTER

Digital design FPGA lab manual

2014-15

Aim: To design and verify 8-bit Universal shift register.

Circuit/Block Diagram:

Theory:

A universal shift register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. In order for the universal shift register to operate in a specific mode, it must first select the mode.

Operating Mode
S1
S0
Locked
0
0
Shift-Right
0
1
Shift-Left
1
0
1
1

To accomplish mode selection the universal register uses a set of two selector switches, S1 and S0. As shown in Table 1, each permutation of the switches corresponds to a loading/input mode.

In the locked mode (S1S0 = 00) the register is not admitting any data; so that the content of the register is not affected by whatever is happening at the inputs.

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In the shift-right mode (S1S0 = 01) serial inputs are admitted from Q3 to Q0.

In the shift left mode (S1S0 = 10) serial inputs are admitted from Q0 to Q3.

In the parallel loading mode (S1S0 = 11) data is read from the lines L0, L1, L2, and L3 simultaneously

The universal shift register is able to operate in all these modes because of the four-to-one multiplexers that supply the flip-flops.

Program:

module universalshiftreg_8( input clr, input clk, input s1, input s0, input dsr, input dsl, input pn, input [7:0] P, output reg p1=1’b0, output reg p2=1’b0, output reg p3=1’b0, output reg p4=1’b0, output reg p5=1’b0, output reg p6=1’b0, output reg p7=1’b0, output reg p8=1’b0, output reg [7:0] q=8’b00000000 ); always@(posedge clk)begin

if(clr==0)begin

p1<=0;

p2<=0;

p3<=0;

p4<=0;

p5<=0;

p6<=0;

p7<=0;

p8<=0;

q<=8'b00000000;

end

else begin

case({s1,s0})

2'b00: begin

q<=P;

end

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2'b01:begin

if(dsr==1)begin

q[7:0]<={dsr,P[7:1]};

end else if(dsr==0)begin

q[7:0]<={dsr,P[7:1]};

end

end

2'b10:begin

if(dsl==1)begin

q[7:0]<={P[6:0],dsl};

end else if(dsl==0)begin

q[7:0]<={P[6:0],dsl};

end

end

2'b11:begin

if(pn==1)begin

p1<=P[0];

p2<=P[1];

p3<=P[2];

p4<=P[3];

p5<=P[4];

p6<=P[5];

p7<=P[6];

p8<=P[7];

end

end

endcase

end

end

endmodule

Testbench:

module tbuniversalshiftreg_8; reg clr; reg clk; reg s1; reg s0; reg dsr; reg dsl; reg pn;

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reg [7:0] P;

wire p1; wire p2; wire p3; wire p4; wire p5; wire p6; wire p7; wire p8; wire [7:0] q;

universalshiftreg_8 uut ( .clr(clr), .clk(clk),

.s1(s1),

.s0(s0),

.dsr(dsr),

.dsl(dsl),

.pn(pn),

.P(P),

.p1(p1),

.p2(p2),

.p3(p3),

.p4(p4),

.p5(p5),

.p6(p6),

.p7(p7),

.p8(p8),

.q(q)
);

initial begin clr = 1; s1 = 1; s0 = 0; dsr = 0; dsl = 1; pn = 0; P = 8'b11110000;

always begin

clk=1;

#10;

clk=0;

#10;

end

#20;

clr = 1; s1 = 1; s0 = 0; dsr = 0;

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end

endmodule

dsl = 0; pn = 0;

P = 8'b11110000;

#20;

clr = 1; s1 = 0; s0 = 1; dsr = 1; dsl = 0; pn = 0;

P = 8'b11110000;

#20;

clr = 1; s1 = 1; s0 = 1; dsr = 0; dsl = 0; pn = 1;

P = 8'b11110000;

#20;

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Simulation Results:

FPGA implementation- Design summary:

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Exp 5: ARBITRARY COUNTER

Digital design FPGA lab manual

2014-15

Aim: To design a 3- bit arbitrary counter to detect the sequence 0,1,2,3,6,5,7,0

Circuit/Block Diagram:

O/P
3

COUNTER

clk
rst

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:

Asynchronous (ripple) counter changing state bits are used as clocks to subsequent state flip-flops

Synchronous counter all state bits change under control of a single clock

Decade counter counts through ten states per stage

Up/down counter counts both up and down, under command of a control input

Ring counter formed by a shift register with feedback connection in a ring

Johnson counter a twisted ring counter

modulus counter.

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Program:

module cntr(clk,rst,cnt); input clk,rst; output reg [2:0] cnt; reg [2:0] icnt; always@(posedge clk) begin if(rst) icnt <=0; else if(icnt==6) icnt <=0; else icnt <= icnt + 1; end always@(icnt) begin case(icnt) 3'b000 : cnt = 3'b000; 3'b001 : cnt = 3'b001; 3'b010 : cnt = 3'b010; 3'b011 : cnt = 3'b011; 3'b100 : cnt = 3'b110; 3'b101 : cnt = 3'b101; 3'b110 : cnt = 3'b111; endcase end endmodule

Testbench:

module tb; reg clk,rst; wire [2:0] cnt; cntr R1 (clk,rst,cnt); initial begin

clk=0;

rst=1;

#10;

rst=0;

end always #5 clk = ~clk; endmodule

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Simulated Waveform:

FPGA implementation- Design summary:

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Exp 6: SEQUENCE DETECTORS

Digital design FPGA lab manual

2014-15

6.1A SEQUENCE DETECTOR WITH AND WITHOUT OVERLAPPING USING MOORE STATE MACHINE

1011011

will

Aim: To design of sequence detector with and without overlapping using Moore state machine to detect

11101.

Theory:

The following state diagram describes a finite state machine with one input X and one output Z. The FSM asserts its output Z when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial "

cause the output to go high twice: Z = "

in state S4 (after having seen the sequence 1011). The FSM is thus a Moore machine.

state after it has recognized the string. As an example the input string X= " "

0001001

. The output will asserts only when it is

with overlap

i.

Program :

module moore_overlap( input x, output reg y, input clk, input rst ); reg[2:0] current_state,next_state; parameter A=3'b000; parameter B=3'b001; parameter C=3'b010; parameter D=3'b011; parameter E=3'b100; parameter F=3'b101; always@(posedge clk)begin if(rst)begin current_state=A; end

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else begin current_state=next_state; end end always@(current_state or x or rst)begin case(current_state) A: begin//----------------------A

if(rst==0&x==1)begin

y=0;

next_state=B; end else if(x==0)begin

y=0;

next_state=A; end end B:begin//------------------------B

if(x==1)begin

y=0;

next_state=C; end else if(x==0)begin

y=0;

next_state=A; end end C:begin//-------------------------C

if(x==1)begin

y=0;

next_state=D; end else if (x==0) begin

y=0;

next_state=A; end end D:begin//------------------------D

if(x==0)begin

y=0;

next_state=E; end else if(x==1) begin

y=0;

next_state=A; end end E:begin//-------------------------E

if(x==1)begin

y=0;

next_state=F; end else if(x==0) begin

y=0;

next_state=A;

end

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end F:begin//---------------------------F

if(x==1)begin

y=1;

next_state=C; end else if(x==0)begin

y=0;

next_state=A;

end

end

endcase

end

endmodule

Testbench:

module tbmooreoverlap;

// Inputs

reg x;

reg clk;

reg rst;

// Outputs

wire y;

// Instantiate the Unit Under Test (UUT) moore_overlap uut ( .x(x), .y(y), .clk(clk), .rst(rst)

);
initial begin
//
Initialize Inputs
x
= 0;
clk = 0;
rst = 0;

// Wait 100 ns for global reset to finish

#100;

end

always begin

clk=1;

#10;

clk=0;

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#10;

end

end

initial begin

rst=1;

#20;

rst=0;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#100;

endmodule

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Simulation Results:

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ii. Without Overlap

module moore_nooverlap(

input x, output reg y,

input clk, input rst

);

reg [2:0] current_state, next_state; parameter A=3'b000; parameter B=3'b001; parameter C=3'b010; parameter D=3'b011; parameter E=3'b100; parameter F=3'b101; always@(posedge clk)begin if(rst)begin current_state=A; end else begin current_state=next_state; end end always@(current_state or x or rst)begin case(current_state) A: begin//----------------------A

if(rst==0&x==1)begin

y=0;

next_state=B; end else if(x==0)begin

y=0;

next_state=A; end end B:begin//------------------------B

if(x==1)begin
y=0;
next_state=C;
end
else if(x==0)begin
y=0;
next_state=A;
end
end
C:begin//-------------------------C
if(x==1)begin

y=0;

next_state=D; end if (x==0) begin

y=0;

next_state=A; end end D:begin//------------------------D

if(x==0)begin

y=0;

next_state=E;

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end else if(x==1) begin

y=0;

next_state=D; end end E:begin//-------------------------E

if(x==1)begin

y=0;

next_state=F; end else if(x==0) begin

y=0;

next_state=B; end end F:begin//---------------------------F

if(x==1)begin

y=1;

next_state=B;

end

else if(x==0)begin

y=0;

next_state=F;

end

end

endcase

end

endmodule

Testbench:

// Inputs
reg x;
reg clk;
reg rst;
// Outputs
wire y;

module tbmoorenooverlap;

// Instantiate the Unit Under Test (UUT) moore_nooverlap uut ( .x(x), .y(y), .clk(clk), .rst(rst)

);

always begin

clk=1;

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 #10; clk=0; #10; end initial begin rst=1; #20; rst=0; x=1;#20; x=1;#20; x=1;#20; x=0;#20; x=1;#20; x=0;#20; x=1;#20; x=1;#20; x=0;#20; x=1;#20; x=1;#20; x=1;#20; x=0;#20; x=1;#20; x=1;#20; x=1;#20; x=0;#20; x=1;#100; end
endmodule

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Simulation Results:

FPGA implementation- Design summary:

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5.1B DESIGN OF SEQUENCE DETECTOR WITH AND WITHOUT OVERLAPPING USING MEALY STATE MACHINE

Aim: To design of sequence detector with and without overlapping using Mealy state machine

Theory:

In the theory of computation, a Mealy machine is a finite-state machine whose output values

are determined both by its current state and the current inputs. (This is in contrast to a Moore

machine, whose output values are determined solely by its current state.) A Mealy machine is

a deterministic finite state transducer: for each state and input, at most one transition is

possible.

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Program:

i. With overlap

module melay_overlap( input x, input clk,rst, output reg y ); reg [2:0] current_state,next_state; parameter A=3'b000; parameter B=3'b001; parameter C=3'b010; parameter D=3'b011; parameter E=3'b100; always@(posedge clk)begin if(rst)begin current_state=A;

end else begin current_state=next_state; end end always@(current_state or x)begin case(current_state) A: begin//----------------------A

if(x==1)begin

y=0;

next_state=B; end else if(x==0)begin

y=0;

next_state=A; end end B:begin//------------------------B

if(x==1)begin

y=0;

next_state=C; end else if(x==0)begin

y=0;

next_state=A; end end C:begin//-------------------------C

if(x==1)begin

y=0;

next_state=D;

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end else if (x==0) begin

y=0;

next_state=A; end end D:begin//------------------------D

if(x==0)begin

y=0;

next_state=E; end else if(x==1) begin

y=0;

next_state=D; end end

3'b100:begin//-------------------------E

if(x==1)begin

y=1;

#10;

next_state=D; end else if(x==0) begin

y=0;

next_state=A;

end

end

endcase

wire y; melay_overlap uut ( .x(x), .clk(clk), .rst(rst), .y(y)

);

endmodule

Testbench:

module tbmelayoverlap; reg x; reg clk; reg rst;

always begin

clk=1;

#10;

clk=0;

#10;

end

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end

initial begin

rst=1;

#20;

rst=0;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#100;

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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ii. Without overlap

module melay_nooverlap( input x, output reg y, input clk, input rst ); reg [2:0] current_state, next_state; parameter A=3'b000; parameter B=3'b001; parameter C=3'b010; parameter D=3'b011; parameter E=3'b100; always@(posedge clk)begin if(rst)begin current_state=A; next_state=A; end else begin current_state=next_state;end end always@(current_state or x)begin case(current_state) A: begin//----------------------A

if(x==1)begin

y=0;

next_state=B; end else if(x==0)begin

y=0;

next_state=A;
end
end
B:begin//------------------------B
if(x==1)begin
y=0;
next_state=C;
end
else if(x==0)begin
y=0;
next_state=A;
end
end
C:begin//-------------------------C

if(x==1)begin

y=0;

next_state=D; end else if (x==0) begin

y=0;

next_state=A;

end

end

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D:begin//------------------------D

if(x==0)begin

y=0;

next_state=E; end else if(x==1) begin

y=0;

next_state=D; end end E:begin//-------------------------E

if(x==1)begin

y=1;

#10;

next_state=E; end else if(x==0) begin

y=0;

next_state=A;

end

end

endcase

end

endmodule

Testbench:

module tbmelaynooverlap;

reg x;
reg clk;
reg rst;
wire y;

melay_nooverlap uut ( .x(x), .y(y), .clk(clk), .rst(rst)

);

always begin

clk=1;

#10;

clk=0;

#10;

end

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initial begin

rst=1;

#20;

rst=0;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=1;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=0;#20;

x=1;#20;

x=0;#20;

x=1;#100;

end

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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Exp 7: FIFO and LIFO

7.1

FIRST IN FIRST OUT (FIFO)

Aim: To design and verify the working of FIFO.

Circuit/Block Diagram:

Theory:

FIFO is an acronym for First In, First Out, a method for organizing and manipulating a data buffer, where the oldest (first) entry, or 'head' of the queue, is processed first. It is analogous to processing a queue with first-come, first-served (FCFS) behaviour: where the people leave the queue in the order in which they arrive. FCFS is also the jargon term for the FIFO operating system scheduling algorithm, which gives every process CPU time in the order in which it is demanded. FIFO's opposite is LIFO, Last-In-First-Out, where the youngest entry or 'top of the stack' is processed first. A priority queue is neither FIFO or LIFO but may adopt similar behaviour temporarily or by default.

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Program:

module fifo (clk,rst,rd,wr,wrptr, rdptr , full, empty);

input clk,rst,rd,wr; output [2:0] wrptr, rdptr; output full, empty;

wire [2:0] wrptrp1, rdptrp1;

reg [1:0] state;

reg

parameter EMPTY = 0, PARTIAL=1,FULL=2;

[2:0] wrptr, rdptr;

always @(posedge clk) begin if (rst) state <= EMPTY; else case(state) EMPTY:

state <= wr ? PARTIAL : EMPTY;

PARTIAL: case (1) wr : state <= (wrptrp1 == rdptr ) ? FULL: PARTIAL;

rd :

state <= (rdptrp1 == wrptr ) ? EMPTY: PARTIAL;

endcase FULL: state <= rd ? PARTIAL : FULL;

endcase
PARTIAL:

end

always @(posedge clk) begin if (rst) wrptr <= 0; else case(state) EMPTY,

end

Endcase

wrptr <= (wr && ~rd ) ? wrptr +1 : wrptr;

assign full = state==FULL; assign empty = state==EMPTY;

 assign wrptrp1 = (wrptr + 1); assign rdptrp1 = (rdptr + 1);

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endmodule

Testbench:

module tb;

reg clk,rst,rd,wr; reg rdnba,wrnba; wire [2:0] wrptr, rdptr; wire full, empty;

always @(wr or rd ) {wrnba,rdnba} <= {wr,rd};

fifo G1 (clk,rst,rdnba,wrnba,wrptr, rdptr , full, empty);

always #5 clk = clk === 1'bx ? 0 : ~clk;

initial

begin

rst = 1; wr=0; rd = 0; repeat (2) @(posedge clk); rst = 0;

end

initial

repeat (5) @(posedge clk);
write (10);
repeat (5) @(posedge clk);
repeat (5) @(posedge clk);

begin

end

task write; input integer n; repeat (n) begin repeat (1) @(posedge clk); wr = 1; repeat (1) @(posedge clk); wr = 0; end

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repeat (n) begin repeat (1) @(posedge clk); rd = 1; repeat (1) @(posedge clk); rd = 0; end

endmodule

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Simulation Results:

FPGA implementation- Design summary:

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7.2 LAST IN FIRST OUT (LIFO)

Aim: To design and verify the working of LIFO.

Circuit/Block Diagram:

Theory:

In computing, LIFO as a term generally refers to the abstract principles of list processing and temporary storage, particularly when there is a need to access the data in limited amounts, and in a certain order. A useful analogy is of the office worker: a person can only handle one page at a time, so the top piece of paper added to a pile is the first remove. In computing, the abstract LIFO mechanism is used in real data structures implemented as stacks; sometimes, such data structures are called "push-down lists" and "piles". The difference between a generalized list, an array, queue or stack, is defined by the rules enforced and used to access the mechanism. In any event, an LIFO structure is accessed in opposite order to a queue:

"There are certain frequent situations in computer science when one wants to restrict insertions and deletions so that they can only take place at the beginning or end of the list, not in the middle. Two of the data structures useful in such situations are stacks and queues."

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Program:

module LIFO( input [7:0] data_in, input push, input pop, input init, input clk, output reg full, output reg empty, output reg no_pop, output reg no_push, output reg [7:0] data_out ); reg [7:0] stack_reg; integer i,j; initial begin

full=0;

empty=0;

no_push=0;

no_pop=0;

data_out=8'b00000000;

stack_reg=8'b00000000;
i=0;
j=7;
end
always @(posedge clk)begin
if(init==0)begin
full<=0;
empty<=0;
no_push<=0;
no_pop<=0;
data_out<=8'b00000000;
end
else if(init==1)begin

if(push==1)begin

if(i<7)begin

stack_reg[i]<=data_in[i];

end

if(i==7)begin

stack_reg[i]<=data_in[i];

full<=1'b1;

empty<=1'b0;

i<=0;

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end

i<=i+1;

end

if(full==1)begin

no_push<=1'b1;

no_pop<=1'b0;

end

if(pop==1)begin

if(j>0)begin

data_out[j]<=stack_reg[j];

data_out[j]<=stack_reg[j];

empty<=1'b1;

full<=1'b0;

j<=7;

end

if(j==0)begin

end

j<=j-1;

end

if(empty==1)begin

no_pop<=1'b1;

no_push<=1'b0;

end

end

end

endmodule

Testbench:

// Inputs
reg [7:0] data_in;
reg push;
reg pop;
reg init;
reg clk;

// Outputs wire full; wire empty; wire no_pop; wire no_push; wire [7:0] data_out;

module tblifo;

// Instantiate the Unit Under Test (UUT) LIFO uut ( .data_in(data_in), .push(push), .pop(pop),

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.init(init),

.clk(clk),

.full(full),

.empty(empty),

.no_pop(no_pop),

.no_push(no_push),

.data_out(data_out)

);

always begin

clk=1;

#10;

clk=0;

#10;

initial begin // Initialize Inputs init = 1; data_in = 8'b10101010; push = 1; pop = 0;

#20;

init = 1; data_in = 8'b10101010; push = 1; pop = 0;

#20;

init = 1; data_in = 8'b10101010; push = 1; pop = 0;

#20;
init = 1;
data_in = 8'b10101010;
push = 1;
pop = 0;
#20;

init = 1; data_in = 8'b10101010; push = 1; pop = 0;

#20;

init = 1; data_in = 8'b10101010; push = 1; pop = 0;

#20;

init = 1; data_in = 8'b10101010; push = 1;

end

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pop = 0;

#20;

init = 1; data_in = 8'b10101010; push = 1; pop = 0;

#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;
init = 1;
data_in = 8'b10101010;
push = 0;
pop = 1;
#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;

init = 1; data_in = 8'b10101010; push = 0; pop = 1;

#20;

init = 1; data_in = 8'b10101010; push = 0;

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pop = 1;

#20;

end

endmodule

Simulation Results:

FPGA implementation- Design summary:

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Exp 8: FSM MODEL FOR COIN OPERATED TELEPHONE SYSTEM

Aim:

To design a coin operated public Telephone unit using Mealy FSM model with following operations i. The calling process is initiated by lifting the receiver.

ii. Insert 1 Rupee Coin to make a call.

iii. If line is busy, placing the receiver on hook should return a coin

iv. If line is through, the call is allowed for 60 seconds at the 45th second prompt another 1

Rupee coin to be inserted, to continue the call.

v. If user doesn't insert the coin within 60 seconds the call should be terminated.

vi. The system is ready to accept new call request when the receiver is placed on the hook.

vii. The FSM goes 'out of order' state when there is a Line Fault.

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Program:

input clk,rst; input Lift_receiver,Coin_insert,Invalid_number,Place_receiver,valid_number; input Line_available, line_busy, time_out,line_fault,line_ok; output reg display_error,display_ok,ok,return_coin,done,disconnect_line,dial,monitor_duration; reg [3:0] state,state_ns; parameter stateA = 4'b0001, //Ready stateB = 4'b0010, //Wait for Coin stateC = 4'b0011, //Wait for number stateD = 4'b0100, //Dialling stateE = 4'b0101, //Call in Progress stateF = 4'b0110, //Call terminated stateG = 4'b0111, //Unable to make call stateH = 4'b1000, //Invalid Number input stateI = 4'b1001; //Out of Order

always@(posedge clk) begin if(rst) state <= stateA; else state <= state_ns; end

usy

,Line_available,time_out,line_fault,line_ok)

begin display_error =1'b0;display_ok=1'b0;

ok=1'b0;return_coin=1'b0;done=1'b0;disconnect_line=1'b0;dial=1'b0;monitor_duration=1'b0;

case(state) stateA : begin if(Lift_receiver) begin state_ns = stateB; ok = 1'b1; end else if(line_fault) begin state_ns = stateI; display_error =1'b1; end

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end

stateB : begin if(Coin_insert) begin state_ns = stateC; ok =1'b1; end end stateC : begin if(Invalid_number) begin state_ns = stateH; display_error = 1'b1; end else if(valid_number) begin state_ns = stateD; dial = 1'b1; end end stateD : begin if(line_fault || line_busy) begin state_ns = stateG; display_error = 1'b1; end else if(Line_available) begin state_ns = stateE; monitor_duration = 1'b1; end end stateE : begin if(Place_receiver) begin state_ns = stateA; disconnect_line = 1'b1; end else if(time_out) begin state_ns = stateF; disconnect_line = 1'b1; end end stateF : begin if(Place_receiver) begin state_ns = stateA; done = 1'b1;

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end

end

stateG : begin if(Place_receiver) begin state_ns = stateA; return_coin = 1'b1; end end stateH : begin if(Place_receiver) begin state_ns = stateA; return_coin = 1'b1; end end stateI : begin if(line_ok) begin state_ns = stateA; display_ok = 1'b1; end end

endcase

end

endmodule

Testbench:

end

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task stimulus; input [9:0] input_stimulus_t; begin input_stimulus = input_stimulus_t;

#10;

end

initial begin

clk=0;

rst=1;

#10;

rst=0;

end always #5 clk = ~clk;

initial begin

stimulus(10'b1100_1100_11);

/*stimulus(10'b1100_1101_11);

stimulus(10'b1100_1100_11);

stimulus(10'b1100_1100_11);

stimulus(10'b1100_1100_11);

stimulus(10'b1100_1100_11);

stimulus(10'b1100_1100_11);*/

end

endmodule

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Simulation waveform:

FPGA implementation- Design summary:

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APPENDIX A

Tutorial for Xilinx FPGA flow

Xilinx Tool Flow Lab

From the Desktop: Double click on the icon

ISE Design

. The New

Create a New Project

Step 1

2 - 1.

Create a new project targeting the Spartan-3E device that is on the Spartan-3E kit. Specify your language of choice, Verilog, to complete the lab.

All Programs

1. Launch ISE: Select Start

Tools

Xilinx ISE Design Suite 13.2

Project Navigator.

2. In the Project Navigator, Select File Project Wizard opens.

New Project or click on

3. For Project Name, type lab1, leaving Top-level source type: as HDL.