EE 6325: VLSI DESIGN

Spring 2006 TR 3:30pm – 4:45pm ECSN 2.120

Instructor: Poras T. Balsara TA: Dheera Balasubramanian

(972) 883-2557, poras@utdallas.edu dheera@student.utdallas.edu
Office Hrs: TR 2:00pm – 3:15pm or by appointment
Room ECSN 4.928 / 4.612
http://www.utdallas.edu/~poras/courses/ee6325/

● Course Overview
Introduction to MOS transistor, equations for voltage, current, etc. Details of CMOS inverter, transmission
gates. Design of complex CMOS gates; combinational and sequential design techniques in VLSI; issues in
static, transmission gate, and dynamic logic design. Subsystem design: adders, multipliers, memory and I/O
circuits. Clocking and clock distribution. Introduction to low power design. Design for testability. CMOS
technology, and rationale behind various design rules. Use of CAD tools to layout, check and simulate
some basic circuits. Design, layout and simulation of a small full-custom project.
All announcements and homework assignments will be posted on the web page for this course. It is the
responsibility of each student to check this web page at least once a week for new announcements and
homeworks.
Prerequisites: EE 3320 and proficiency in using Unix platforms.

● Course Material.
o Text Book:
o J. Rabaey, A. Chandrakasan and B. Nikolic: Digital Integrated Circuits: A Design Perspective,
Second Edition, 2003. Prentice Hall, Englewood Cliffs, New Jersey 07632.
o References:
o N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison Wesley.

● Grading Policy
Final grades in this course will be based on several homework assignments given throughout the semester,
two examinations and a final project. All homework assignments and exams are to be done individually.
Project can be done in a group of no more than 2 students. No makeup examinations will be offered in this
course. Please look at the UTD course schedule and catalog for information on withdrawals, incompletes
and academic dishonesty. Any graded work can be disputed in writing within one week of the return of that
work. I will re-grade the work completely.

The tentative grading policy is:

Homework: 20%
Examination I: 20%
Examination II: 20%
Project: 40%

● Course Announcements and Homeworks

There will be several homework assignments during the semester. Assignments are due in class by 4:00pm
on the due date. Assignments can be turned in one day late, for 75% credit. Assignments that are turned in
more than a day late will not be graded. Homework assignments will be posted on the web page for this
course and may not be handed out in the class. It is a student's responsibility to print each assignment and
hand-in the solutions by the due date.

EE 6325 1 PTB 1/30/06

● Tentative List of Topics (with Section #s from Rabaey’s text book)

No. Lecture Topic Section #

1 Course Overview, Introduction to VLSI 1.1-3 (self-study)
2 Basic CMOS logic gates and layout A,2.3,ref. 1.3-6
3 CAD tools introduction
4 MOS transistor theory 3.3
5 CMOS inverter 5.1-2
6 Other CMOS characteristics 5.3
7 Parasitics estimation 4.3,5.4
8 Delay, power estimation 4.4,5.4-5,9.2-3
9 Gate design, device sizing, etc. 5.4-5,6.2.1,9.2-3
10 Combinational logic 6.1-2
11 Static combinational logic 6.2.1
12 Pseudo NMOS, PLA design 6.2.2,8.5
13 TGL, CPL, DPL gates 6.2.3
14 Dynamic combinational logic 6.3
15 Sequential logic 7.1,7.2.1
16 Static sequential circuits 7.2
17 Dynamic sequential circuits 7.3-4,7.6
18 Pipelining 7.5
19 Adders \& Shifters 11.3,11.5
20 Multipliers 11.4
21 Memory design 12.1,12.2.1,12.2.3,12.3
22 Input/Output circuits ref. 5.6
23 Clocking and timing issues 10.1,10.3-4
24 Intro. to low power design – dynamic power 5.5,11.7
25 Intro. to low power design – leakage power 5.5
26 Intro. to design for testability H.3
27 VLSI design styles 8.
28 Technology scaling 3.5

● Important Dates
Spring Break: March 6-11, 2006

Examination I: Thurs., March 2, 2006

Examination II: Thurs., April 13, 2006

Project Preliminary Study due: Tues., March 14, 2006

Final Project due: Mon., April 24, 2006

EE 6325 2 PTB 1/30/06