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DC Bus Ripple Minimization in Cascaded H-Bridge Multilevel Converters

under Staircase Modulation


Yusuke Fukuta , Giri Venkataramanan
Department of Electrical and Computer Engineering
University of Wisconsin Madison
1415 Engineering Drive, Madison, WI 53706
USA
Abstract Cascade connected H bridge multilevel converters
are becoming an attractive topology for very high power
applications. Due the single phase loading of the individual
bridges, the dc link capacitors required in these converters are
faced with a heavy stress. The problem is particularly acute
with stair-case type of modulation strategies. This paper
presents an approach for equalizing the power drawn from
each H bridge within less than one cycle period with the aim of
reducing capacitor sizing. The presented approach is based on
rearranging the switching strategies with focusing on the
redundancies in synthesizing output voltage of H bridge
multilevel converters. The proposed approach also holds nearly
the same degree of freedom in selecting conduction angles and
attains similar levels of harmonic performance as with
conventional switching angle selection approaches.
The
analysis presented in this paper is also confirmed by
simulation.

Keywords: H bridge multilevel converter, power balancing,


conduction angle, harmonic reduction, capacitor sizing
I. INTRODUCTION
Multilevel converters have been receiving increasing
interest as a cost effective solution for various high voltage
and high power applications including power quality
control as well as motor drive control [1-7]. At such high
power levels, they have the advantages of accomplishing
the smaller voltage step for waveform synthesis as well as
equalizing the voltage stress of each device
simultaneously. Staircase or stepped waveform modulation
schemes eliminate lower frequency harmonics suitable for
such high power applications have been presented in the
past [1-3, 8, 9]. Besides, H bridge multilevel converters
are superior to neutral-point-cramped multilevel converter
since H bridge multilevel converters can equalize voltage
stress of each switching semiconductors and accordingly
can overcome the overrating issue of switching devices
[10]. The 2m+1 level cascaded converters have m sets of
H bridges, and accordingly m conduction angles to be
determined if the staircase modulation is employed.
Approaches to determine the conduction angles synthesize
the output voltage waveform to eliminate particular
harmonics [1,8]. In these approaches, the dc power drawn
from the dc bus capacitor of single H bridge over each
cycle is different from one H bridge to another, and is
equalized over a period of m/2 cycles of output voltage
waveform. Limiting the dc bus voltage ripple to small

magnitudes requires large capacitors for all the bridges.


Thus, it is desirable to equalize bridge dc power over
shorter period
This paper proposes a method for attaining balancing
dc power drawn from each of all H bridges within a single
cycle, regardless of the number of discrete voltage levels
while also eliminating predominant lower harmonics to
similar levels as with conventional modulation strategies.
II. DC BUS POWER INJECTION ANALYSIS APPROACH
The proposed approach uses a switching function model
to determine the dc bus currents based on the output voltage
waveforms and conduction angles to determine the
switching strategy that shortens the dc power equalization
period. The schematic of a 2m+1 level-cascaded H bridge
converter is shown in Fig. 1. The switching functions Hk
(where k = 1, m) for each H bridge may be defined to
relate the dc bus quantities to the output quantities. Then the
relation among switching functions Hk , switching state of
the devices SA1, SA1, SA2, SA2 and the output voltage of the
corresponding one H bridge Vo,k are described as Table 1.
Van
1st H bridge

SA1,1

VDC

SA1,1

SA2,1

VDC

Vo,1

Io

2nd H bridge

SA1,2

SA2,2

SA1,2

SA2,2

+
-

Vo,2

mth H bridge

VDC

SA1,m

SA2,m

SA1,m

SA2,m

+
-

Vo,m

Fig. 1 One phase of 2m+1 Level H bridge Cascaded


Multilevel Converter

0-7803-7420-7/02/$17.00 2002 IEEE

1988

SA2,1

Table 1. Relation between switching function, switching


th
state and output voltage of k H bridge
Sw. Function
Hk
1
0

SA1,k

SA2,k

Vo,k

1
1
0
0

1
0
1
0

VDC
0
0
-VDC

equalized, which is m/2 cycles for conventional switching


approach [1,8].
One of popular approaches for modulation is to
determine conducting angles so that the predominant lower
harmonics can be eliminated, since the 2m+1 level cascaded
converters (with m sets of H bridges) under staircase
modulation has m arbitrary conduction angles for
synthesizing the output voltage waveform. Fig. 2 shows
example switching states for a 7 level H bridge multilevel
converter [1,8], where H1, H2, H3 represent the switching
function of 1st, 2nd and 3rd H bridges as shown in Fig. 1.
Nevertheless, since these approaches determine m
conduction angles in regards to harmonic elimination, halfcycle based average dc power of each H bridge is different
from one H bridge to another, and accordingly draw m
different values of dc powers are drawn from various H
bridges. For example, three different levels of dc power are
drawn from seven (7) level H bridge multilevel converters,
as denoted as I, II, III and a, b, c in Fig. 2 respectively.
Consequently, each of the bus powers are equalized through
a round-robin approach over several cycles. This is the
reason why classical approaches need at least m/2 cycles to
equalize dc power drawn from all of H bridges.

-1
where
SA1,k, SA2,k = 1 means that SA1,k, SA2,k are turned on.
SA1,k, SA2,k = 0 means that SA1,k, SA2,k are turned on.
(k=1, m)
Io

Van

1 2
2 1
2
2
1
3 3 1 2 3 3 2 1
3 3 1

Pattern I
H1

H2

III

II
II

III

H3

III. MINIMIZED RIPPLE MODULATION STRATEGY

III

II

One of the advantages of cascaded multilevel


converters is the redundancy available in synthesizing
certain output voltage. Utilizing this feature, it is possible
to attain dc bus power equalization over a single cycle
regardless of the number of voltage steps, while
simultaneously optimizing the harmonic performance as
with conventional switching approaches. The proposed
switching patterns are presented in Fig. 3 for seven (7)
level and Fig. 4 for nine (9) level where 1, 2, 3, 4 are
the conduction angles. The conduction angles 1, 2,
T
- k (T: one cycle
3 4 are determined by k =
2
period), which let the first and second quarter cycle of the
output waveform to be even symmetric. Recalling the
output current, Io, is Io = Ipksin( t + ) as stated in (3), it
is clear that Io( t + ) = -Io( t ). Therefore, the dc power
for the same conduction angles would be equalized by
means of inverting the output voltage from positive to
negative in the second half cycle.

Pattern II
H1

H2

H3

Fig. 2: Output waveforms and switching function


of seven level H bridge cascade converter
It may be deduced from Table 1 that the single H bridge
output voltage (Vo,k) can be written as:
Vo,k = Hk VDC

(1)
th

where Hk is the switching function of k H bridge


The input current Iin (the current flowing through the dc
bus) can be also derived as:
Iin, k = Hk Io

(2)

Io = Ipk sin ( t + )

(3)

where = cos-1 ( power factor)


It should be noted that that the only fundamental component
of output current is considered since high frequency
harmonic components do not generate average power.
th
Therefore, the average dc power supplied by k H
bridge over a certain time period can be calculated as:

PDC , k =

1
T'

/ 2
/ 4
3/4
0
1 2 3 3 2 1 1 2 3 3 2 1

H2

IV

H3

T'

Vo, k I in, k dt

H1

(4)

where T is the duration of making dc power of all H bridges

1989

IV

Fig. 3 Proposed switching function of seven (7) level


H bridge cascaded converter

This can be seen from Fig. 3 and Fig. 4 where the shaded
areas with the same roman number (i.e. I, II ) indicate
equal dc power. For example, the area II in Fig. 3 appears
on both H2 and H3, and both area II begin to commutate at
1 and terminate at 3 with 180 degree apart. In
addition, the area II in H2 is positive quantity, whereas the
one in H3 is negative quantity. Thus, when one recalls
equation (3), it is apparent that both areas II are the same.
From this observation, one can see H2 and H3 provide the
same dc power, and thus, dc power balance can be
achieved within one cycle by choosing the conduction
angles that allow dc power of H1 and H2 (or H3) to be
equal. That is to say,
PDC, 2 + PDC, 3 = 2 PDC, 1

(5)
st

Since the switching function for 1 H bridge, H1,


always commutates from the conduction angle of 2
through 2, thus, 2 can be expressed as a function of the
desired dc bus power provided by single H bridge, Pbus ,
load power
where Pbus =
.
number of H bridge

Pbus =
=

vdc

2 '

vdc Ipk

I pk sin( ) d
(6)

(cos( 2 + ) + cos( 2 ))

Pbus

2 = cos 1
2 vdc Ipk cos

(7)

The rest of conduction angles can be computed by DC


power balance equations in terms of either bus #2 or #3.
Pbus =

+1

vdc Ipk

2
0

+ 3 '

Pbus =

vdc Ipk

sin( )d
+1 '

cos (cos 1 + cos 3 )

(8)
(9)

or

3 = cos

(2 cos 2 cos 1 )

H1

H2

VI

V
VII

H3
V

H4

VI

VII

Fig. 4 Proposed switching function of nine (9) level


H bridge cascaded converter
strategy requires larger number of cycles in order for the
DC bus power equalization of each of H bridge as the
number of voltage step increases. Fig. 4 is the switching
function for nine (9) level cascaded converters, where it is
apparent from the figure that:
PDC, 1 = PDC, 3

(11)

PDC, 2 = PDC, 4

(12)

Consequently, dc power balance of all four (4) H bridges


can be accomplished by dc power bus power balance
st
nd
between 1 and 2 H bridge, which means:
PDC, 1 = PDC, 2

(13)

or specifically,

Pbus,2 =

I pk vdc
2
I pk vdc
2

{A cos + B sin }

(14)

{A cos B sin }

(15)

where A = cos 1 + cos 2 + cos 3 + cos 4


B = sin 1 sin 2 + sin 3 sin 4
Therefore, dc bus power balance can be attained by:

Finally, substituting (8) into (6) yields:


cos 3 = 2 cos 2 cos 1

T / 4
T / 2
3 T / 4
T
1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1

Pbus,1 =

sin( )d + K

sin( )d +

(10)

It may be noted that the selection of 1 in (10) is arbitrary;


accordingly, this degree freedom can be utilized for lower
harmonic elimination as presented in [1,8]. It should also
be noted that the proposed approach has one degree
freedom from seven level converter while these
conventional approaches have three degrees freedom,
nevertheless, the fundamental component is already
adjusted with the proposed approach through dc power
balancing. Therefore, the proposed approach is capable to
attain dc power balance for single cycle with one degree of
freedom less than conventional approaches.
This approach is more beneficial for converters with
higher number of levels since conventional switching

1990

Pbus,1 = Pbus, 2

(16)

B sin = 0

(17)

As one can see from (17), this approach provides up to


three degrees of freedom in terms of conduction angle
selection under general cases (i.e. sin 0 non unity
power factor). Although this is one degree of freedom less
than conventional approach, it reduces the number of
cycles to ensure the equalization of dc bus power drawn
from every H bridge. The rest of conduction angles can
be expressed as a function of the desired dc bus power as
follows:
Pbus =

vdc Ipk
A cos
2

(18)

It should be noted that in case of unity power factor, the


followings are true from Fig. 4.

area I = area IV

IV. SIMULATION RESULTS

area II = area III


area V = area VI

Phase Voltage [V]

Phase Voltage Van (V)

Therefore, the constraint (17) is always true for any


combination of conduction angles (1, 2, 3, 4), and
subsequently, the harmonic performance from this
switching approach would be the same as the conventional
one.
It should be noted that the switching schemes can be
easily extended to higher than nine (9) level multilevel
converters. Multilevel converters with odd number of H
bridges (i.e. 11, 15 level) should add another pair of
switching function to Fig. 3, whereas Fig. 4 in case of
multilevel converters with even number of H bridges (i.e.
9, 13 level).

800
400
0
-400
-800

The simulation of phase leg output voltage (Van) and


its Fourier analysis is carried out. The simulation results
of the conventional approach for seven level (7) and nine
level (9) case are illustrated in Fig. 5 and 7 while the
results of the proposed approach are presented in Fig. 6
and 8, respectively. Both simulations are preformed under
the average dc bus capacitor voltage of 230VDC, per H
bridge supplied power of 1kW (3kW in total for a 7 level
converter and 4 kW in total for a 9 level converter), under
0.8 leading power factor, 60Hz staircase modulation. It
should be noted that the Fourier analysis results are of
single phase case. The numerical data is also shown in
Table 2 and 3 for seven (7) level, and in Table 4 and 5 for
nine (9) level cases.

4.17

8.33

12.5

800
400
0
400

800

16.67

4.17

8.33
Time [ms]

Time (ms)

12.5

16.67

1000
3

Phase voltage Van [V]

Phase voltage Van [V]

1 .10
100
10
1
0.1

60

300

540

780

1260

1020

100
10
1
0.1
0.01

Frequency [Hz]

Fig. 5 Seven (7) level phase leg voltage [top] and


harmonic components [bottom] by ordinal
approach
1=0.2036, 2=0.5467, 3=1.0254 [rad]
THD = 0.105

60

300

540

780

Frequency [Hz]

1020

1260

Fig. 6 Seven (7) level phase leg voltage [top] and


harmonic components [bottom] by proposed
approach
1=0.2044, 2=0.5338, 3=1.0205 [rad]
THD = 0.138

Table 2: Seven (7) level H bridge multilevel


converter dc bus power simulation
by classical approach

Table 3: Seven (7) level H bridge multilevel


converter dc bus power simulation
by proposed approach

DC Bus Power [W]

DC Bus Power [W]

# of cycle 1st H bridge 2nd H bridge 3rd H bridge

# of cycle 1st H bridge 2nd H bridge 3rd H bridge

0.5 cycle

639.0

1087

1269

0.5 cycle

999.8

1273

726.8

1 cycle

954.8

863.6

1176

1 cycle

999.8

1000

1000

1.5 cycle

998.0

998.4

998.4

1991

500
0
500

1000

1000

Phase Voltage [V]

Phase Voltage Van (V)

1000

4.17

8.33
Time (ms)

12.5

500
0
500

1000

16.67

4.17

8.33
Time [ms]

12.5

16.67

Phase voltage Van [V]

Phase voltage Van [V]

1000
1000

100
10
1
0.1

60

300

540

780

1020

1260

100
10
1
0.1
0.01

Frequency [Hz]

60

300

540

780

1020

1260

Frequency [Hz]

Fig. 7 Nine (9) level phase leg voltage [top] and


harmonic components [bottom] by ordinal
approach
1=0.1756, 2=0.3826, 3=0.7052, 4=1.0734
[rad], THD =0.076
Table 4 Nine (9) level H bridge multilevel
converter dc bus power simulation
by ordinal approach
st

DC Bus Power [W]


nd
rd
2 H3 Hbridge
bridge
1205
944.0

Table 5 Nine (9) level H bridge multilevel


converter dc bus power simulation by
ordinal approach

th

0.5 cycle

1 Hbridge
1264

1 cycle

1236

1072

768.9

1.5 cycle

1139

916.6

935.3

1023

2 cycle

1002

1002

1002

1002

# of cycle

Fig. 8 Nine (9) level phase leg voltage [top] and


harmonic components [bottom] by proposed
approach
1= 0.1542, 2= 0.4018, 3= 1.0812, 4=
0.7011 [rad], THD = 0.072

st

4 Hbridge
594.4

0.5 cycle

1 Hbridge
1273

1 cycle

1000

# of cycle

930.5

DC Bus Power [W]


nd
rd
2 H3 Hbridge
bridge
1273
727.6
1000

1001

th

4 Hbridge
727.6
1000

Although the THD level of the proposed approach is


slightly inferior to conventional approaches due to the one
less degree of freedom in switching angle selection, in a 7
level converter, the difference becomes negligible in 9
level converter and beyond. Nevertheless, Fig. 6 and Fig.
8 presents that the proposed approach is capable to
eliminate the specific harmonic component. In addition,
Tables 25 clearly show the proposed approaches
complete dc bus power of every H bridge within one cycle
regardless of the converters voltage level.

converters, which is nearly the same harmonic


performance as conventional method. The graphical
explanations for the proposed switching strategy also show
the flexibility in extending this method towards higher
level converters. Detailed simulation results clearly
indicate the power balancing within one cycle as well as
better harmonic performance. Experimental verification of
the approach is under progress and will be results will be
reported in the future.

V. CONCLUSION

ACKNOWLEDGMENT

This paper has presented switching schemes for dc


power balance realization within single cycle for H bridge
multilevel converters. While the conventional modulation
approaches for a 2m+1 level converter require m /2 cycles
for equalization, the proposed approach requires only one
cycle regardless of the number of converters voltage
steps, which makes it possible to reduce the capacitor
sizing. In addition, it has been shown that the proposed
switching strategies is capable to eliminate m-2 harmonic
components from 2m+1 level H bridge multilevel

Support for this project from the Wisconsin Electric


Machines and Power Electronics Consortium (WEMPEC)
and the Office of Naval Research through grant N0001401-1-0623 is gratefully acknowledged.

1992

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