Using CMOS Chip

1.
HIGH SPEEDCMOS PRODUCT GUIDE
Type Number
Function Page
Number of Pins
TC74HCOoP/F OUAD 2.INPUT NAND GATE 14 107
TCT4HCO2PIF OUAD 2-INPUT NOR GATE 14 110
TC74HC03P/F O U A D 2 . I N P U T N A N D G A T E ( O P E ND R A I N ) 14 113
TCT4HCO4PIF HEX INVERTER 14 117
TCT4HCTO4P/F HEX INVERTER 14 120
TCT4HCUO4P/F H E X I N V E R T E R( S I N G L ES T A G E ) 14 123
TC74HC08P/F OUAD 2.INPUT AND GATE 14 125
TC74HC10PlF T R I P L E 3 . I N P U TN A N D G A T E 14 129
TC74HC1lPlF T R I P L E 3 - I N P U TA N D G A T E 14 132
TC74HC14PlF H E X S C H M I T TI N V E R T E R 14 135
TC74HC20PlF DUAL 4-INPUT NAND GATE 14 139

TC74HC21PlF DUAL 4.INPUT AND GATE 14 142,
TC74HC27PlF TRIPLE 3.INPUT NOR GATE 14 145
TC74HC30P/F S.INPUT NAND GATE 14 148
TC74HC32PlF OUAD 2.INPUT OR GATE 14 151
TC74HC42PlF BCD TO DECIMALDECODER 16 154
TC74HC51P/F D U A L 2 W - 2 1A N D / O R I N V E R T G A T E 14 158
TC74HC73PlF D U A L J - K F L I P . F L O PW I T H C L E A R 14 162
TC74HC74PlF D U A L D F L I P - F L O PW I T H P R E S E TA N D C L E A R 14 167
TC74HC75PlF 4.BIT D-TYPE LATCH 16 't72
TC74HC76PlF D U A L J - K F L I P - F L O PW I T H P R E S E TA N D C L E A R 16 177
TC74HC77PiF 4-BIT D.TYPE LATCH 14 182
TC74HC85P/F 4.BIT MAGNITUDE COMPARATOR 16 187
TC74HC86P/F O U A D E X C L U S I V EO R G A T E 14 192
TC74HC107P/F D U A L J . K F L I P . F L O PW I T H C L E A R 14 196
TC74HC109P/F D U A L I - R T L I P - F L O PW I T H P R E S E TA N D C L E A R 16 201
TC74HC112PlF D U A L J . K F L I P . F L O PW I T H P R E S E TA N D C L E A R 16 206
TC74HC113P/F D U A L J . K F L I P - F L O PW I T H P R E S E T 14 211
TC74HC123PlF D U A L M O N O S T A B L EM U L T I V I B R A T O R 16 216
TC74HC125PlF OUAD BUS BUFFER (3-STATE) 14 224
Type Number
Function Page
Number of Pins
TC74HC126PlF OUAD BUS BUFFER (3.STATE} 14 224
TC74HC131PlF 3-TO€ LINE DECODER/LATCH 16 229
TC74HCr32PlF OUAD 2.INPUT SCHMITT NAND 14 235
TC74HC133P/F l3-INPUTNAND GATE 16 239
TC74HC137PlF 3-TOA LINE DECODER/LATCH 16 ,242
TC74HCT137PlF 3-TO€ LINE DECODER/LATCH 16 248
Tg74HC138P/F 3-TO-8 LINE DECODER 16 254
TC74HCT138P/F 3-TO€ LINE DECODER 16 259
TC74HC139P/F DUAL 2-TO4 LINE DECODER 16 264
TC74HC147PlF 1 O . T O 4 L I N E P R I O R I T YE N C O D E R 16 268
TC74HC148PlF 8-TO-3 LINE PRIORITY ENCODER 16 272

TCT4HC1slP/F S . C H A N N E LM U L T I P L E X E R 16 277
TC74HC153P/F D U A L 4 - C H A N N E LM U L T I P L E X E R 16 282
TC74HC154P 4.T0-16 LINE DECODER 24 288
TC74HC155P/F DUAL 2.TO4 LINE DECODER 16 293
TC74HC157PlF O U A D 2 . C H A N N E LM U L T I P L E X E R 16 297
TC74HCls8P/F O U A D 2 . C H A N N E LM U L T I P L E X E R( I N V . ) , 16 297
TC74HC160P/F SYNC. DECADE COUNTERWITH ASYNC. CLEAR 16 302
TC74HC161P/F S Y N C . B I N A R Y C O U N T E RW I T H A S Y N C . C L E A R 16 302
TC74HC162P S Y N C . D E C A D E C O U N T E RW I T H S Y N C . C L E A R 16 302
TC74HC163P/F S Y N C . B I N A R Y C O U N T E RW I T H S Y N C . C L E A R 16 302
TC74HC164PlF 8 - B I T S I P OS H I F T R E G I S T E R 14 512
TC74HC165P/F 8 . B I T P I S OS H I F T R E G I S T E R 16 317
TC74HC166P/F 8 - B I T P I S OS H I F T R E G I S T E R 16 323
TC74HC173PlF OUAD D-TYPE REGISTER(3-STATE) 16 329
TC74HC174PlF H E X D F L I P . F L O PW I T H C L E A R 16 334
TC74HC175PlF O U A D D F L I P - F L O PW I T H C L E A R 16 339
TC74HC181P A L I T H M E T I CL O G I C U N I T 24 344
TC74HC182PlF LOOK AHEAD CARRY LOGIC 16 355
TC74HC190PlF' BCD UP/DOWNCOUNTER 16 362
Type Number Page
Function
Number of Pins
TC74HC191P/F 4-BIT BINARY UP/DOWNCOUNTER 16 362
TC74HC192PlF SYNC. UP/DOWNDECADE COUNTER 16 372
TC74HC193P/F IFF 16 372
-"ilYll.g'.-uP/"P.9Jx-,"atNARY,"c.*o",!llf
TC74HC194PlF 4 . B I T P I P OS H I F T R E G I S T E R 16 381
TC74HCl95P/F 4.BIT PIPO SHIFT REGISTER 16 387
TC74Hg221PlF DUAL MONOSTABLEMULTIVIBRATOR 16 393
TC74HC237PlF 3-TO€ LINE DECODER/LATCH 16 401
TC74HC238PlF 3.TO-8 LINE DECODER 16 107
TC74HC240PlF OCTAL BUS BUFFER (3.STATE/INV.} 20 411
TCt4HCT240P OCTAL BUS BUFFER (3-STATE/INV.I 20 117
'tc74HC241PlF
OCTAL BUS BUFFER (3-STATE) 20 411
TC74HCT241P OCTAL BUS BUFFER (3-STATE) 20 117
TC74HC242PlF OUAD BUS TRANSCEIVER(3-STATE/INV.) l4 122
TC74HC243PlF OUAD BUS TRANSCEIVER(3.STATE) 14 422
TC74HC244PlF OCTAL BUS BUFFER (3-STATE) 20 4il
TC74HCT244P OCTAL BUS BUFFER (3.STATE} 20 417
TC74HC245PlF OCTAL BUS TRANSCEIVER(3-STATE) 20 127,
TC74HCT245PlF OCTAL BUS TRANSCEIVER(3.STATE) 20 432
TC74HC251PlF 8-cHANNEL MULTrPueien (3-srATE) 16 437
TC74HC253PlF DUAL 4-CHANNEL MULTIPLEXER (3.STATE) 16 282
TC74HC257PlF OUAD 2-CHANNEL MULTIPLEXER (3.STATE) 16 442

TC74HC258PlF O U A D 2 . C H A N N E LM U L T I P L E X E R( 3 . S T A T E / I N V . ) 16 442
TC74HC259PlF 8.BIT ADDRESSABLELATCH 16 447
TC74HC273PlF O C T A L D F L I P - F L O PW I T H C L E A R 20 453
TC74HC279PlF OUAD S.R LATCH 16 458
'TC74HC280PlF
9-BIT PARITY GENERATOR/CHECKER 14 462
T.cta{czegplr 4.BIT BINARY FULL ADDER 16 466
TC74HC298P/F O U A D 2 . C H A N N E LM U L T I P L E X E R / R E G I S T E R 16 470
TC74HC299P 8-BIT PIPOSHIFT REGISTER 20 475
TC74HC323P 8 . B I T P I P OS H I F T R E G I S T E R 20 475
Type NumberPage
Function
Number of Pins
TC74HC3ilP/F S.CHANNEL MULTIPLEXER/REGISTER 20 485
TC74HC356P/F S.CHANNEL MULTIPLEXER/REGISTER 20 191
TC74HC365P/F HEX BUS BUFFER I3-STATE} 16 497
TC74HC366P/F HEX BUS BUFFER (3-STATE/INV.I 16 197
TC74HC367P/F HEX BUS BUFFER (3.STATE) 16 502
TC74HC368P/F HEX BUS BUFFER (3.STATE/INV.) 16 502
TC74HC373P/F OCTAL D-TYPE LATCH (3-STATE} 20 507
TC74HCT373PlF OCTAL D.TYPE LATCH (3-STATEI 20 514
TC74HC374PlF OCTAL D.TYPE FLIP.FLOP (3-STATEI 20 519
TC74HCT374PlF OCTAL D.TYPE FLIP.FLOP (3-STATE} 20 526
TC74HC375P/F OUAD D.TYPE LATCH 16 532

TC74HC377PlF OCTAL D-TYPE FLIP.FLOP 20 536
TC74HC386P/F O U A D E X C L U S I V EO R G A T E 14 541
TC74HC390P/F DUAL DECADE COUNTER 16 545
TC74HC393P/F .
3L BlNARYCouNrrER.".-.- 14 552
P.-y.
TC74Hc/.23PlF DUAL MONOSTABLEMULTIVIBRATOR 16 5s8
TC74HC533P/F OCTAL D.TYPE LATCH (3.STATE/INV.) 20 507
TC74HC534P/F OCTAL D-TYPE FLIP.FLOP (3-STATE/INV 20 519
TC74HC540P/F OCTAL BUS BUFFER (3-STATE/INV.) 20 566
TC74HCT540P/F OCTAL BUS BUFFER (3.STATE/INV.) 20 571
TC74HC541PlF OCTAL BUS BUFFER (3.STATE} 20 566

TC74HCTs41PlF OCTAL BUS BUFFER (3.STATE} 20 571
TC74HC563P/F OCTAL D-TYPE LATCH (3-STATE/INV.) 20 507
TC74HCT563P OCTAL D.TYPE LATCH (3.STATE/INV.) 20 576
TC74HCs64P/F OCTAL D.TYPE FLIP-FLOP(3.STATE/INV 20 519
TC74HCT564P OCTAL D.TYPE FLIP-FLOP(3-STATE/INV 20 582
TC74HCs73P/F OCTAL D-TYPE LATCH (3-STATE) 20 507
TC74HCT573P OCTAL D-TYPE LATCH (3.STATEI 20 576
TC74HC574PlF OCTAL D.TYPE FLIP-FLOP (3.STATE} 20 519
TC74HCT574P OCTAL D-TYPE FLIP.FLOP(3-STATE) 20 582
Type Number
Function
Number of Pins Page
TC74HC590P (3.STATE)
8-BIT BINARY COUNTER/REGISTER 16 s88
TC74HC592P 8.BIT REGISTER/BINARY
COUNTER 16 596
TC74HC593P * 8.BIT REGISTER/BINARYCOUNTER (3-STATE) 20
TC74HC595P 8.BIT SHIFT REGISTER/LATCH(3-STATE} 16 604
TC74HC597P/F 8 . B I T L A T C H / S H I F TR E G I S T E R 16 612
TC74HC620P OCTAL BUS TRANSCEIVER(3.STATE/INV.) 20 620
TC74HC623P OCTAL BUS TRANSCEIVER(3-STATE) 20 620
TC?4HC640P/F OCTAL BUS TRANSCEIVER(3.STATE/INV.} 20 427
TCT4HCTilOP/F OCTAL BUS TRANSCEIVER{3-STATE/INV.) 20 452
TC74HC643PtF OCTAL BUS TRANSCEIVER(3-STATE) 20 127
TC74HCT643PlF OCTAL BUS TRANSCEIVER(3-STATE) 20 132

TC74HC646P (3-STATE)
OCTAL BUS TRANSCEIVER/REGISTER 24 625
TC74HCT646P OCTAL BUS TRANSCEIVER/REGISTER
{3-STATE) 24 633
TC74HCil8P (3-STATE/INV.}
TC74HCT648P (3.STATE/INV.)
TC74HC651P (3-STATE/IITIV.}
TC74HCT651P OCTAL BUS TRANSCEIVER/REGISTER
f3-STATE/INV.) 24 649
TC74HC652P (3.STATE)
OCTAL BUS TRANSCEIVER/REGISTER 24 61r
TC74HCT652P (3-STATE}
TC74HC670P 4-WORDx 4-BlT REGISTERFILE (3-STATEI 16 657
TC74HC688P/F 8-BIT EOUALITY COMPARATOR 20 661

TC74HC690P DECADE COUNTER REGISTER(3.STATEI 20 668
TC74HC691P 4.BIT BINARY COUNTER REGISTER(3.STATEI 20 668
TC74HC692P DECADE COUNTER REGISTER(3.STATE) 20 680
TC74HC693P 4-BIT BINARY COUNTER REGISTER(3.STATE} 20 680
TC74HC696P (3.STATEI
U/D DECADE COUNTER/REGISTER 20 692
TC74H0697P U/D 4.BIT BINARY CTR./REGISTER(3.STATE} 20 692
TC74HO698P r (3-STATEI
U/D DECADE COUNTER/REGISTCN 20
TC74HO699P' U/D 4.BIT BINARY CTR./REGISTER(3-STATEI 20
TCT4H@,0p,2PIF DUAL +INPUT NOR GATE 14 703
Type Number
Function Page
Number of Pins
TC74HO.l017PlF D E C A D EC O U N T E R / D I V I D E R 16 706
TC74HC4020PlF 1 4 - S T A G EB I N A R Y C O U N T E R 16 712
TC74HC4022PIF OCTAL COUNTER/DIVIDER 16 717
TC74HC4024PlF 7 - S T A G EB I N A R Y C O U N T E R 14 723
TC74HC4028PlF DECODER
BCD-TO-DECIMAL 16 728
TCT4HC40/,OPIF 12.STAGEBINARY COUNTER 16 733
TC74HC4049PlF H E X B U F F E R( I N V . ) 16 738
TC74HC40s0P/F HEX BUFFER 16 738
TC74HC4051P* S . C H A N N E LA N A L O G M U L T I P L E X E R 16
TC74HC4052P * D U A L 4 . C H A N N E LA N A L O G M U L T I P L E X E B 16
TC74HC4053P r T R I P L E 2 - C H A N N E LA N A L O G M U L T I P L E X E R 16
TC74HC4060P/F 14.STAGEBINARY COUNTER/OSCILLATOR 16 u,
TC74HC4066P/F OUAD BILATERALSWITCH 14 748
TC74HC4072PlF D U A L 4 - I N P U TO R G A T E 14 753
TC74HC4075PlF T R I P L E 3 - ! N P U TO R G A T E 14 757
TC74HC4078PlF S . I N P U T . O R / N O RG A T E 14 761
TC74HC/,O94PlF (3-STATE}
8 . B I T S I P OS H I F T R E G I S T E R / L A T C H 16 765
TC74HC40102P DUAL BCD PROGRAMMABLE
DOWNCOUNTER 16 772
TC74HC40103P 8.BIT BINABY PROGRAMMABLEDOWN COUNTER 16 772
TC74HC4511PlF BCD TO 7 SEGMENTL/D/D (LED} 24 785
TC74HC4514P 4 - T O - 1 6L I N E D E C O D E R / L A T C H 24 790
TC74HC4515P (!NV.)
4.T0-16 LINE DECODER/LATCH 24 790
TC74HC4518PlF D U A L D E C A D EC O U N T E R 16 795
TC74HC4520PtF DUAL 4.BIT BINARY COUNTER , 16 795
TC74HU538P/F DUAL MONOSTABLEMULTIVIBRATOR 16 802
TC74Hc4il3PlF BCD TO 7 SEGMENT LIDID (LCD} 16 8r0
TC74HCT70o7PlF HEX BUFFER l4 816
TC74HC7266P/F OUAD EXCLUSIVENOR GATE 14 Er9
TCt4HC7292P PROGRAMMABLEDIV IDER/TIMER t6 023
TC74HC729ttP PROGRAMMABLE
DIVIDER/TIMER 16 E2g
Note: 1. All DIP 24 pin productsserviceasan enclosureof the narrow type (300mil)
2. * denotesthe productsunder development
2. HIGH SPEEDCMOS SETECTIONGTIIDE
FTJNCTTON TYPE N['MBER,
GATE NAND 74HC{n,74HC'03,
74HC10, 74Hc,;O,74HC30,74HCl33
NOR 74H@2,74HC27,74HC4002,74HC407 8
AND 74HC08,74HCll,74HC2l
OR 74HC32,74HC4075, 74HC4072, 74HC407I
II{VERTER 74HCU04,74HCI)4,74HC|O4
SCHMITT TRIGGER 74HCt4,74HCt32
MULTIFUNCTION 74HC5l, 74HC86,74HC386,7 4HC7266
BI,JFFER 74HC4049,74HC4050,74HCT7007
3.STATE 7 4HCt25, 7 4HCl26, 7 4HC240, 7 4HCT240, 7 4HC24l,
7 4HCT24t, 7 4HC244, 7 4HCT244, 7 4HC365, 7 4HC366, 74HC367,
74HC368,74HC540,74HCT540,'.| 4HC54l, 74HCT541
BIDIRECTIONAL 74HC242, 7 4HC243, 7 4HC245, 7 4HCT245, 7 4HC620
7 4HC623, 7 4HC640, 7 4Hef 640, 7 4HC643,'t 4HCT643
FLIP.FLOP J-K, FLIP-FLOP 7 4HC73, 7 4HC76, 7 4HCt07, 74 HCI 09, 7 4HCt 12, 74HCl I 3
D F L IP-FLOP 7 4HC74, 7 4HCt7 4, 7 4HCL75, 7 4HC273,',t 4Hc37'.l
3.STATE 74HC374,74HCT3747 4HC534,',t4HC564,7 4HCT5 64,
74HC574,74HCT5747 4HC646, 7 4HCT646, 7 4HC648,
74HCT648,74HC651 74HCT65l, 7 4HC652,7 4HCT652
LATCH 7 4HC75, 7 4HC77, 7 4HC259, 7 4HC279, 7 4HC37S
rsrarE 7 4HC373, 7 4HCt 373, 74HC533, 7 4HC563, 74HCT563,
't4HC573,74HCT573
I
MULTIVIBRATOR 7 4HCt23, 7 4HC22t, 7 4HC423, 74HC4538
DECODER 7 4HC42, 7 4HCl3l, 7 4HCt37, 7 4HCT137, 74HC138,
74HCT138, 74HCl 39, 7 4HCr54, 74HC155, 7 4HC237,
7 4HC2?8, 7 4HC4028, 7 4HC45 | 4, 74HC45r 5
I z-sncrtrnxr 74HC45t1,74HC4543
ENCODER 74HC147,74HC148
REGISTER 7 4HCt 64, 74HCt 65, 7 4HCt 66, 7 4HCt7 3, 7 4HCI94, 74HC195,
7 4HC299, 7 4HC323, 74HCs95, 7 4HC597, 7 4HC670, 7 4HC4094
COUNTER BINARY 7 4HCt6t, 7 4HCt 63, 74HCl 9 1, 7 4HCt93, 74HC393,74HC590,
7 4HC592, 74HC59 3, 7 4HC69t, 7 4HC693, 7 4HC697, 7 4HC699,
74HC4520
DECADE 74HCI 60, 7 4HCt 62, 74HC190, 7 4HCt92, 74HC390,74HC690,
7 4HC692, 7 4HC696, 7 4HC698, 74HC45I 8
DIVIDER 74HC4017,74HC4020,74HC4022,74HC4024,74HC4040,
74HC4060,?4HC40I 02, 74HC40tO3,74HC7292,74HC7294
MULTI.PLEXER ANALOG 74HC4051, 7 4HC4052,74HC4053,7 4HC4066
DIGITAL 74HC151, 74HCl 5 3, 74HCl 57, 74HC158, 7 4HC2SI,7 4HC25?,
7 4HC257,74HC258, 7 4HC298,7 4HC354,74HC356
OTHERS CQMPARATOR 74HC85,74HC688
ADDER 74HC283
ALU 74HC181,74HCt82
PARITYTREE 74HC280
l0
GATE
Type Function Equivalent Equivalent Pin
Number LSTTL cMos. Number
74HC 00 QUAD2-INPUT NANDGATE LSOO 4011, 740O L 4

74HC 03 QUAD2-TNPUT NANDGATE (oPEN DMrN ) LSO3 ,k40107,' 15029T 4
74HC 10 TRIPLE 3-INPUT NA}ID GATE LS]-O 4023 14
74HC 20 DUAL 4-INPUT NAND GATE LS2O 40L2 T4
74HC 30 8-INPUT NAND GATE LS3O 4068 I4
TAHC I 3i l3-INPUT NAND GATE LS133 16
7 4HC 02 QUAD2-INPUT NOR GATE LSO2 4001 14
74HC 27 TRIPLE 3-INPUT NORGATE LS27 4025,*4000 L4
74HC4002 DUAL 4-INPUT NOR GATE *LS25 4002 L4
TLHe.ttOTR 8-INPUT OR/NORGATE 4078 14
74HC 08 QUAD2-INPUT AND GATE LSOS 4081 T4
74HC 1 1 TRIPLE 3-INPUT AI{D GATE LS11 4073 L4
74HC 2 L DUAL 4-INPUT AND GATE LS21 4082 L4
74HC 32 QUADz-INPUT OR GATE LS32 4 07 L 14
74HC4075 TRIPLE 3-INPUT OR GATE 4075 14
74HC4072 DUAL 4-INPUT OR GATE 4072 L4
74HC4078 8-INPUT OR/NORGATE 4078 14
74HC 04 HEX INVERTER LS04 * 4069U L4
74HC T04 HEX INVERTER LS04 * 4069U 14
74HC u04 HEX INVERTER(SINGLE STAGE) *LS04 4069u.7404u I4
74HC 51 DUAL 2W-2I AND/OR INVERT GATE LS51 *4085 L4
74HC 86 QUADEXCLUSIVE0R GATE L S 8 6 ,L S 3 8 6 4030 14
74HC7266 QUADEXCLUSM NOR GATE *LS266 4077 14
74HC 386 QUADEXCLUSIVEOR GATE L S 8 6. t S 3 8 5 4030 I4
7 4HC L4 HEX SCHMITT INVERTER LS14 4584 14
74HC I32 QUAD2-INPUT SCHMITTNAND LS132 4093 14
* Suggestedalternative
GATE
QUAD 2.INPUT NAND GATE QUAD z-INPUT NOR GATE
00 02
P o s i t i v e ' l o g i c :Y = A E P o s i t i v el o g i c : Y = A + E
3A
11
GATE (Continued)
(0PENDRArN)
NANDGATE
0uAD2-TNPUT H E XI N V E R T E R
04
03 T04
Positivelogic: f = AB u04
P o s i t i v el o g i c : f : F
vcc 4E} 44 4Y 3B 3A 3Y vcc 6A 6Y 5/, 5Y 4A 4y
QUAD2.INPUTANDGATE T R I P L3
E. I N P U N
T A NG
DATE
08 t0
P o s i t i v el o g i c : f = A B Positivelogic: Y=ABd
vCC 49 4A ay 38 3A vcc 1c LY 3C 38 3A
TRIPLE-3-INPUT ANDGATE HEX SCHMITTINVERTER

l1 14
'logic:
Positive ABC Positivelogic: Y r
5Y 4 A
1Y
12
GATE (Continued)
DUAL4.INPUT NAND GATE DUAL 4-INPUT ANDGATE

20 21
'log'ic: = 'logi
Positive Y IBCD P o stii v e c: Y = ABCD
vcc zD zc Nc pB zA zy vcc 2D 2c Nc ?B 2A
T R I P L E3 - I N P U TN O RG A T E 8-INPUT NAND GATE

27 30
'logic:
Positive Y = A+B+C Positive log'ic: Y =TBCDEFGH
VCCNCHGNCNCY
vcc l-c lY
QUADz.INPUTORGATE D U A L2 W ID E -2IN P U TA N D /OR

IN V E R T
GA -
32 5l
Positjvelogic: Y=A+B P o s ' i t i v el o g i c : 1 Y = f f i
2Y=2[-291fi.fi
VCC 48 4A 4Y 3B 3A 5Y
I
'-.;
i-l , t--'
:f t i
'"--f'_!'-
r, :..i I i
' -j '',--
ii
t;
I
I
13
G ATE (C ont inued)
2 -IN P UTE X CLUS IVE -O
QU AD GART E QUAD2-INPUT SCHMITTNANDGATE
86 132
Po si ti ve logic : Y = A @ B= A B+ A E Positive logic: Y =TB-
VCC 48 4A 4Y 38 3A 3Y VCC 48 4A 4Y 3B 3A 3Y
I 3-IN PU TNA NDG A T E QUAD2-INPUTEXCLUSIVE-NOR

GATE
.|33
7266
Positive logic: Y=ABCDEFGHTJK[]*f Positive logic: Y=[-@-9=43+ffi
VCCMLKJIHY 48 4A 4Y 3Y 3B 3A
VCC
QUADz-TNPUT EXCLUSTVE-OR
GATE DUAL 4-INPUT NORGATE
386 4002
P o si ti ve logic : Y = A O B = AB + AB - Positive logic: Y=ATBTCTD
vcc 48 +t ax 3Y 38 3A vcc 2y 2A 28 2C 2D
14
GATE ( Cont inued)
DUAL4-INPUT ORGATE T R IPL E3.IN P U TORGA TE
407? 4075
Positive logic' Y=A+B+C+D Positive logic: Y=A+B+C
vcc 2Y 2D 2c 28 2A vco 3c 3E| 3A 3Y
8 -INP UTNO RG A T E
4078
P o s i t i v e l o g i c : Y=A+B+C+D+E+F+G+H
VCCXH GFENC
NC GND
15
BUFFER
Type Equivalent Equivalent Pin
Function
7 4HCr700i HEX BUFFER * LS0T L4

74HC4049 HEX BUFFER(INVERTING) 4049 16
74HC4050 HEX BUFFER 4050 16
74HC L25 QUADBUS BUFFER LS125 5024 L4
74HC L26 QUADBUS BUFFER LS126 5025 L4
74HC 240 OCTALBUS BUFFER(II{VERTING) LS24O 20
74HCT240 OCTALBUS BUFFER(INVERTING) rs240 20
74HC 24L OCTALBUS BUFFER LS24L 20
74HCT24L OCTALBUS BUFFER LS24I 20
74HC 244 OCTALBUS BUFFER L5244 20
74HCr244 OCTALBUS BUFFER L5244 20
74HC 365 HEX BUS BUFFER LS3654 16
74HC 366 HEX BUS BUFFER (INVERTI}IG) LS366A 16
74HC 367 HEX BUS BUFFER LS367A 50r_2 16
74HC 368 HEX BUS BUFFER (INVERTII.IG) LS368A 16
74HC 540 OCTALBUS BUFFER(rlrvERTrNG) LS540 20
74HCT540 OCTALBUS BUFFER(INVERTING) LS540 20
74HC 54r OCTALBUS BUFFER LS541 20
74HCT54L OCTALBUS BUFFER LS541 20
74HC 242 QUADBUS TMNSCETVER (INVERTING) L5242 L4
74HC 243 QUADBUS TRANSCEIVER LS243 L4
74HC 245 OCTALBUS TMNSCEIVER L5245 20
7 4HCT245 OCTALBUS TMNSCEIVER L5245 20
74HC 620 OCTALBUS TMNSCEIVER (TNVERTTNG) LS62O 20
74HC 623 OCTALBUS TRANSCEIVER L5623 20
74HC 640 OCTALBUS TMNSCEIVER (INVERTING) LS64O 20
74HCT640 OCTALBUS TRANSCEIVER (INVERTING) LS640 20
74HC 643 OCTALBUS TRANSCEIVER LS643 20
74HCT643 OCTALBUS TMNSCEIVER LS643 20
B UFFER
H EXBUFF E R. QUADBUSBUFFER
T7007 125
Positivelogic: Y=A P o s i t i v e ' l o g i c :Y = A
vcc 6A 6Y 5A 5 Y 4A 4Y
r.-e l,c, t y zd zt 2Y GND
l6
B U F F E R( C o n t in u e d)
B USB UF F E R
QU AD OCTALB U SB U F F E (RI N V E R T I N G )
126 240
'logic:
Positive T240
vcc LG 4A 4Y 3G 3Y v"o eo rTr a.g ttezns rW eez lt{ 2A"r
IA IY 2G 2A 2Y
rE r,c,r z1+ ua ?ft rAs zre t* e?r el.ro
OCTALBUSBUFFER B U ST R A N S C E I V(E
QUAD I NRV E R T i N G )
241
T241 242
20 lYl 2A4 IYz 2A3 1Y5 2|A I.r4 2AI vcc NC 1B 2B 3B 4B
tG l.Al 2y4 IAZ zys l-AS 2y? 1A4 Ayl oND
QUADBUSTRANSCEIVER OCTALBUSBUFFER
24s 244
T244
v"s zd- t-yt ?A4 lYz 3A3 IW 2A2 r-Yt 2AL
rG ]-A.I ZYL IA?" ?Y3 1A5 ?YZ IA4 2Y1 OND
17
B U F F E R( C o n t i n u e d )
OCTALBUSTRANSCE
I VER HEX BUS BUFFER
245 365
T245
vcc c B1 B3 Py'. B.5 B6
DIR A 1 jtz Ag A4 A6 L7 A8
HEX BUS BUFFER( I N V E R T I N G ) HEX BUS BUFFER

366 367
Q2 6A 6Y 4A 4y vcc c2 6A O Y 5Y 4A
H E XB U SB U F F E(RI N V E R T I N G ) L U SB U F F E(RI N V E R T I N G )
O C T AB
368 540
T540
-ys
v"" Ea ?r Tz T+ yo tb y? VR
1A 1v 2A 2Y 3Y Af AZ A4 A5 A6 A1 A8
t8
B U F F E R( C o n t in u e d )
OCTALBUS BUFFER O C T AB
L U ST R A N S C E I V(E
I NRV E R T I N G )
541
T5 4 t 620
ENABLE GBA
VOc OZ y1 yz Y4 Y5
olf, al- az !|.6 A7 A8 GND AI

ENABLE GAB
OCTALBUS TRANSCEIVER OCTALBUSTRANSCEIVER

( INVERTING)
623
640
T640
vcc c Bt 92 B3 84 B5 B? B8
ENABLE GAB
DIR A I L2 A3 A4 A5 A6 A7 A8
OCTALBUS TRANSCEIVER H E XB U F F E R / C O N V E(RI N

TVEE
RR T I N G )
643 4049
T6 4 3
6Y 6A NC 5Y 5A +Y 4A
vcc 1Y l-A 2Y 2A 3Y
l9
BUFFER( Cont inued)
) ":
HEXBUFFER/CONVERTER
4050
20
FL I P - F L O P
lYpe Equivalent Equivalent Pin
Function
Number LSTTL CMOS. Number
74HC 73 DUAL J-K FLIP-FLOP WITH CLEAR L S 7 3 A L, S 1 0 7 t L4
74HC 76 DUAL J-K FLIP-FLOP WITH PRESET
L S 7 6 A L, S l 1 2 d 4027,7 47 ( 16
AND CLEAR
74HC rO7 DUAL.J-K FLIP-FLOP WITH CLEAR L S 1 0 7 AL, S 7 3 r L4
74HC LOg DUAL J-R FLIP-FLOP WITH PRESET
LSlO9A L6
AND CLEAR
74HC LLz DUAL J-K FLIP-FLOP IÎITHPRESET
L S 7 6 A , L S 1 1 24027
r ,7 47C I6
AND CLEAR
74HC LL3 DUAL J-K FLIP-FLOP WITH PRESET
LS113A L4
t4HC t4 DUAL D FLIP-FLOP WITH PRESET
AND CLEAR
LS744 4013 L4
74HC l-74 HEX D FLIP.FLOP T{ITH CLEAR LSIT 4 40174 L6
74HC L75 QUAD D FLIP-FLOP WITH CLEAR L5175 40175 16
74HC 273 OCTAL D FLIP-FLOP WITH CLEAR L5273 20
7 4 H C3 7 7 OCTAL D-TYPE FLIP.FLOP 20
74HC 374 OCTALD-TYPE FLIP.FLOP (3-STATE) LS374,L557 4 20
74HCT374 OCTALD-TYPE FLIP-FLOP (3-STATE) LS374,L557 4 20
74EC 534 OCTALD-TYPE FLIP.FLOP (3-STATE/INV. ) LS534 20
74HC 564 OCTALD-TYPE FLIP.FLOP (3-STATE/INV.) 'LS564
20
74HCT564 OCTALD-TYPE FLIP-FLOP (3-STATE/INV. ) LS564 20
74HC 574 ocTAL D-TYPE FLrP-FLOP (3-STATE) LS374 ,L557 4 20
74HCT574 ocTAL P-TYPE FLrP-FLOP (3-SrAru; L S 3 7 4 ,L S 5 7 4 20
74HC 646 OCTALBUS TRANSCEIVER/REGISTER LS646 24
74HCT646 OCTALBUS TMNSCEIVER/REGISTER LS646 2.4
74HC 648 OCTALBUS TRAI{SCEIVER/REGISTER (INV.) LS648 24
74HCT648 OCTALBUS TMNSCEIVER/REGISTER (INV.) LS648 24
74HC 65L OCTALBUS TRAI{SCEIVBR/REGISTER (INV.) LS651 24
74HCT651 OCTALBUS TMNSCEIVER/REGISTER (INV.) LS651 24
74HC 652 OCTALBUS TMNSCEIVER/REGISTER LS652 24
74HCT652 OCTALBUS TRANSCEIVER/REGISTER L5652 24
FLI P-FLOP
CLEAR DUALD L
73 C L E AR
74
vcc eclF eo ecx EFn zQ ZC
rET rdlF rx vcc Zd zcr,F ar
21
F L I P - F L 0 P( C o n t i n u e d )
hlI T HP R E SEAN
DUALJ-K F LI P - F LO P T D DUALJ - K F LIP -FLOP
W ITHC LE A R
CLEAR 107
76
_ 9^v
vcclcLR lc1( 2K zcLR-""
DUALJ-R- FLIP-FLOPt^lITHPRESET D U ALJ -K F LIP -FLOP

W ITHP R E S E T
CL EAR CLEAR
109 112
vcc LCLRecmZcr ar Z; 'Zen zq
yqg krcl,R ZJ zK acK zpR ze zq
DU ALJ-K FLI P - F LO P
t , J I TH H E XD F L IP -FLOP
I' ' | ITHC LE A R
ll3 174
vcc 6e 6D 5D oe 4D 4e CI.oCK
ka
CLR
lQ GND
22
F L I P - F L O P( C o n t i n u e d )
QU AD W I THC L E AR
D F LI P - F LO P OC T AL W ITHC LE A R
D FLIP -FLOP
175 273
7D ?Q 6Q 6D
dr.een rq rE- ro 2D ?0
(3-STATE)
OCTALD FLrP-FLoP OCTALD FLIP-FLOP
374 377
T374
5Q CI,oK
o c r A LD F L r P - F L 0(P3 - S T A T E / r N V . ) O C T ADL F L I P - F L O( P
3.STATE/INV.)
534 564
T564
voo d6 oJ qT G a4 G G GoLosK
Q4 CTOCX,
Q1 de
23
FLIP-FL0P(Continued)'
0CTALD F LI P - F L0P ( 3- ST A T E) B U STR A N S C E IVREERGIS TE R
OC T AL
( 3-STATE )
574
T574 646
T646 crc&aBlcr
vcc BO 86 87 BB
tr.'
Ql Q4 Q6 Q7 cIOCK VccBA o Bl BA BS 84
I
JAFryFryry
trrrrllllll:J:
Fryryry
.'uo.*o 81 Bz Bs 84 Dt, Bc Bry
| |
it-1'* '" lIi II
l l I * A B D I R AATz A s 4 4 A b A 6 A ? A s I i
l\-Twl_i
MG]iTEb-TiIjJ
A.r A2 A A5 46 A? A8 GND
43 4
"i"f- "+fl.fi
O C T AB L U ST R A N S C E I VRI R
EGISTTR O C T AB L U ST R A N S C I I V R
EERG I S T I R
( 3 - S T A T E / I N)V . ( 3 -s rATEI/ N V. )
64 8 6 5 .|
'10:*
T 64 8 T65l CLOCK TENABL,E
vcc M i GBA Bl- Ba Bs 84 B5 86 B? BB
,t4lTltTltTryqqF,Tl
FqEtiab=r
CBA SBA Bf 82 B5 84 85 86 B? | | caecee B1 82 Bs 84 85 B5 El
GBA lll
II *l-JI
cAB 88
ldcAB
SAB DIR A1 A;E A3 A4 A5 A6 A7 A8 lll s A B o A B A r A z A s A 45 A 6 A z A 8 | |
Af A2 A3 Aa As A4 A5 .c'6A? AB GND
"T{rt#fffiEAr
. DIRECTION
O CTAL BU ST RA NS CE I V ERRESG IS T ER
( 3 -STAT)E
652
T652 sELEcr
cTPcK;h'IABLE
vcc s I llne ar na Bg 84 E|5 86 B7
CBA SBA B1 BA B3 84 B5 86 gI
C}BA
CAB
8A3 CIAB Af A2 A5
cl,oq( | ENABLE AL A2
AB I GAB
SELECT
AB
24
MULTIVIBRATOR
Function
74HC l23 DUAL MONOSTABLE
MULTIVIBMTOR LSl23 rt4538,*4528 16
74HC 22L DUAL MONOSTABLE
MULTIVIBRATOR LS22L *4538,*4528 16
74HC 423 DUAL MONOSTABLE
MULTIVIBMTOR L5423 *4538,x4528 16
74HC4538 DUAL MONOSTABLE
MULTIVIBMTOR :tLS423 4538, 4528 16
+ Suggestedalternative
MU L TI V I B M T O R
DUALRETRIGGERABLE MULTI-
MONOSTABLE DUALMONOSTABLE
MULTIVIBRATOR
VIB RA T O R 221
123
F U N CT I O N T A B I , E FUNCTION TABIJE
INPUTS OU T P U T S I N P U TS OUTPUTS
ci.nen A B ee, CIJEAR A B ce

L XX I,H L xx !H
H HX I,H HX LH
H XL r. H H XL lrH
.|'f
H LJ JL H Ll: ft 1r
H 1_H J L 1 r 'rr H 1_H JL 1.r
r l r n n _f I,H -rL 1r
X: DON'T CA.RE X : D O N T CA-RE
tRdcx
]*/"*."* ro zi lCx 2Q 2Q zCLR 28
DUALRETRIGGERABLE
MONOSTABLE MONOSTABLE
M U L T I . DUALRETRIGGERABLE MULTI.
VI BRATOR VI BRATOR
4?3 4538
FUNCT lON TAB,],E FUNCTION TABLE
INPUTS O U T P U TS INPUTS O U T P U TS
AB e,q
IJ XX I,H
H HX LH
H XL I,H
H ! J L Jt 1f
H -fH JL1r
X:DON CARE X : D O N T CARE
lpt/cx ?1I'r ztz aCD 2A
VCC f0x ra Eb 2CLR
1B lcLR
25
M U L TI P L E X E R
Dpc Equivdent Equivalont Pin
Numbcr Functlon LSTTL cMos. ItLmbcr
74HC405L 8-CHANNELAI.IALOGMULTIPLEXER 405L 16
74HC4052 DUAI 4-CIHNNEI AIIALOGMULTIPLEXER 4052 t6
74HC4053 TRIPLE 2-CIIANNEI AI.IAIOGMULTIPLEXER 4053 16
74HlC4066 QUADBII.ATEMI ST{ITCH 4016.4066 14
74rrc151 8-CITANNELMI'LTIPLEXER LS151 {.45L2 16
74HC153 DUAI 4-CIIANNEL MULTIPLEXER rs153 4539 16
74HC L57 QUAD2-CHANNELMULTTPLEXER rsL57 15
74HC 158 QUAD2-CIIANNELMULTIPLEXER(II\VERTING LS158 16
74HC 25L 8-CTIANNELMULTIPLEXER(3-STATE) rs25L ,c45L2 16
74rrc 253 DUAL 4-CHAI{NEI MULTIPLEXER(3-STATE) LS253 ,t4539 16
74rrc 257 QUAD2-CHANNEI MULTTPLEXER (3-SrArn) L5257 16
74HC258 QUAD2-CHANNEI MUTTTPLEXER
(3-STATE II\IVERTING) LS258 16
74EC298 QUAD2-CHANNELMULTIPTEXER/REGISTER LS298 16
74HC354 8-CHANNELMULTIPLEXER/REGISTER LS354 )t.45L2 2Q
74HC356 8-CI{ANNELMULTIPLEXER/ REGISTER LS356 *45L2 20
r Suggcstedaltcrnativc
MULTIPLEXER
8-CHANNELMULTIPLEXER DUAL4-CHANNELMULTIPLEXER
l5l 153
vcc 20 A 3cg 2c? zcl 2c0
Ds'c
DZDlD0ywS
QUADz-CHANNEL
MULTIPLEXER QUAD z-CHANNEL
MULTIPLEXER
.I58
157 NONINVERTED
DATAOUTPUTS INVERTED
DATAOUTPUTS
ffiEE
vcc 4A 48 4Y gA 3B 3Y vo ffi ar ls E g.A,ss
O 4A484Y 3A3B
fA 18 lY 2A 28 2Y
2A 2S 2Y oND
26
M U L T I p L E X(ECRo n t i n u e d )
8- CHAN NE (3 R
MLULT T P LE XE -ST A T E) D U A L4 -C H A N N E
MUL LTTP LE X(3-S
E R TA TE )
251 253
vcc 2G A zcs 2c2 ?cI ?c0
D4D5D6D?AB
D3c
D2 D], DO Y ]Y ST
QUADz-CHANNEL (3-STATE) QUAD

MULTTPLEXER z-CNANNEL (3-STATE)
MULTTPLEXER
257 NONINVERTED
DATA
OUTPUTS 258 INVERTED
DATAOUTPUTS
3A
oE 4A 48 4y 3A gB OE 4A 48 4Y gA 3B
s3Y S3Y
1A 1B lY 2A ?B 2Y IA 1B ]Y ?A 2B ?Y
SELECT IA ?A 2B 8Y OND
QUADz.CHANNELMULTIPLEXERS
WITH B.CHANNELMULTIPLEXER
WITH LATCH
OU TPURE
T GISTER (3-srATE
)
298 354
IXORD
SELECT
lm aA aB Qc qP 6-Locx cl
ef
A QBQC (D CKI[s
Y w oS 02 01 so s1s2
2CI
msc
A2 AT BI C2 D2 D]
D6FD4BD2DlDODC
D2
27
M U L T I P L E X E( R
Continued)
8-CHANNEL WITHFLIP-FLOP B-CHA.NNEL

MULTIPLEXER ANALOG
MULTIPLEXER
( 3-STATE
) 4051
356
CONTROL
/+
vccz703ABC
S2
Y w 03G2 G-t SOSlS2 2703AB
? o Il:H
F D5 D4 D3 D2 D]. DO CK
+ 6 COl ,{ON7 5
D6 E
y'o ,*rBITt*
DUAL4-CHANNEL MULTIPLEXER
ANALOG TRIPLE z-CHANNELANALOGMULTIPLEXER
4052 4053
COI\mROL
col9oN
vcc zx rx ox sx ?-
Ix co{-x ox 3x ccDd-Y coM-x l-x ox A B
OY IYC
2Y CO,r-y gy oY 1Z ^^-. _ oZ I NH
fy 1NH Ur rr-1r
12
col"4,,tct'loz it'tHlgttwE
QUADBILATERALSWITCH
4066
tv'o tq,/t zo/r zy'o
28
C O U NT E R
Type Equivalent E'Cuir.'alent Pin
Function LSTTL civlus.
Numbet Number
7 4 H C 1 6 1 SYNC. BINARYCOUNTER WITH ASYNC. CLEAR LS161A 40161 16

74HC L63 SYNC. BINARYCOUNTER WITH SYNC. CLEAR LS163A 40r63 16
74HC LgL 4-BIT BINARYUP/DOWN COUNTER LS191 *4516 16
7 4 H C 1 9 3 SYNC. UP/DOWN BINARYCOUNTER LS193 40193 16
74HC 393 DUAL BINARY COUNTER LS393 *1+520 L4
7 4 H C 5 9 0 8-BIT BINARY COUNTER/REGISTER (3-STATE) rs590 16
74HC 592 8-BIT REGISTER/BINARY COUNTER LS592 16
7 4 H C 5 9 3 8-BIT REGISTER/BINARY COUNTER(3-STATE) rs593 20
74HC 69L 4.BIT BINARY COUNTER REGISTER(3-STATE) LS691 20
74HC 693 4-BIT BINARY COUNTER REGISTER(3-STATE) LS693 20
74HC 697 U/D 4-BIT BINARYCTR.IREGISTER(3-STATE) LS697 20
7 4HC 699 U/D 4-BIT BINARYCTR./REGISTER(3-STATE) LS699 20
74HC4520 DUAL 4-BIT BINARY COUNTER 4520 L6
7 4 H C 1 6 0 SYNC. DECADECOUNTER WITH ASYNC. CLEAR L S 16 OA 40150 16
7 4rrc 162 SYNC. DECADECOUNTER WITH SYNC. CLEAR LS162A 40L62 16
74HC L9O BCD UP/DOWNCOUNTER LS19O *4510 16
74HC L92 SYNC. UP/DOWNDECADECOUNTER LS192 40L92 16
7 4 H C 3 9 0 DUAL DECADECOUNTER LS39O 16
74HC 690 DECADECOUNTER REGISTER(3-STATE) LS69O 20
74HC 692 DECADECOUNTER REGISTER(3-STATE) L5692 20
74HC 696 u/D DECADECOUNTER/nrCrSrrn(3-Sretn) LS696 20
74HC 698 U/D DECADECOUNTER/REGISTER (3-STATE) LS698 20
7 4HC45L8 DUAL DECADECOUNTER 4518 16
74HC40L7 DECADECOIJNTER/DIVIDER 40L7 16
74He4020 l4-STAGE BINARY COUNTER 4020 16
74HC4022 OCTAL COUNTER/DIVIDER. 4022 r.6
74HC4024 7-STAGE BINARY COI]NTER 4024 L4
74HC4040 12-STAGE BINARY COUNTER 4040 16
74HC4060 ].4-STAGE BINARY COUNTER/OSCILLATOR 16
74HC40L02 DUAL BCD PROGRA},IMABLE DOWNCOUNTER 40LO2 16
74HC40L03 8-BIT BINARY PROGM},IMABLE DOWNCOUNTER 401_03 16
74HC7292 PROGM},IMABLE DIVIDER/TIMER *LS2g2 l_6
74HC7294 PROGM},IMABLE DIVIDER/ TIMER *LSzg4 16
COUNTER
PR ESE T T A B4LE
.BIT COUNTER sYN.4-BIT UP/DO"C
, J0NU N T E R
I 60 DECADE ASYNCHRONOUS
, CLEAR 19 0 BC D
I6l B I N A R YASYNCHRONOUS
, CLEAR I9I BINARY
162 DE CA DES,Y NCH R O NC OLUEA
S R
I63 B I N A R YS, Y NCH R O NC
OLUEA
S R MAVfuIN
QAWOA @ QC AD T A cK RcoMNT LOAD C

MIN
CL LOAD 6 u
A B C.D P DOWN
cK
CLOCK
AB C D EMEE GND
CLEAR P
29
COUNTER (Continued)
SYNC.4 - B I TUP/DOWN
COUNTER DIVI DER/TIMER
PROGRAMMABLE
192 BCD 7292 FRoM22 b 231
1 9 3 BINARY
ar{ u ru(I,^^* c C DTPS CLRA

BORROW LvAu
COI'NT D
B
COUNI UP
TP2
Q/\ uouN colrNt ^^ QD

DOml UP VV B E TPl cLKT T
CLKE
DIVIDER/TIMER
PROGRAMMALBE DUALDECADE
COUNTER
7?g4 FR 0 M2 2 t o 2I 5 390 (Br-QUINARY
0R BCD)
z-cl,deF fribcKB
dffiF'
NC
TP CLKICLK2
ICLEAR
B A TP OIJ(ICLKSNC Q OND
DUAL4-BIT BINARYCOUNTER IÎITHOUTPUT

8-BIT BINARYCOUNTER
REGTSTER(3-STATE)
393
590
vcc eA 6 ncncrrnx-coccdilLnnd6
OA e RoK ccK ccLR

CCKEN
nP RCO
Qc aD @r aF aG arr
QO
30
(Continued)
COUNTER
8-BIT BINARYCOUNTER
}IITH INPUT 8-BIT BII{ARYCOUI{TER}IITH INPUT
REGISTER REGISTER (1,il'LTIPLEXED
3-STATE
592 oTJTPUTS)
593
CI,(h,D CCKBN 6-qn ffint
vc A RcK ccx T6-o rcrccf,pr COrg.n nE
A Ccr e o,/ rcr crxgrf acr ocLR

Rcr. tl
rcf,Er I
A c{xaN R0
v@ E&B q/@ cLm
C D E F OE
A/eA c/ac E/aE q/@ a

B/tts Qr'cD F/{OF H/@
SYNCHRoNoUS C0UNTERS/REGTSTER
LTITH sYNC
HRo]r0r,s
uP/Dollr{cor,l{TERs/
REGr sTER
I'IIJLTIPLEXED
3-STATEOUTPUT }IITH II'LTIPLEXED3-STATECI'TPUTS
690 DECADE,DIRECTCLEAR 696 DECADE,DIRECTCLEAR
691 BINARY,DIRECTCLEAR 697 Btrt{ARY,DIRECTCLEAR
692 DECADE,SYNCHROI{OUS
CLEAR 698 DECADE,SYNCHR0]{0USCLEAR
693 BINARY,SYNCHRONOUS
CLEAR 699 BINARY,SYNCHRONOI'SCLEAR
RIFPLF
RIPPLE ENABI,B
B/t ifrfrFi= W\EI^B ifr
vccNqa en ec ADT sBLngt vcc qA qB qc QD T E,m6.srragr
RCO qA QB S QD BNT LOAD O QA QB QC QD F| TI)AD
6KA B c DENpRtLRRcK
DECADE
COUNTER/DIVIDER I4-STAGEBINARYCOUI{TER
4017 4020
vcc au aro aB € ar*Anclc*-
CARRY Q9 Q8 q9 CtR Cx
A{
OUT QI2
Q13 Qrr A0 as (rt ar

Or ao @ Ao qf, qg
QrS QIr a0 a5 qt a+ oND
3l
C O U N T E(RC o n t i n u e d )
OCTALCOUNTER/DIVIDER 7-STAGEBINARYCOUNTER
4022 4024
urocr
6IIEIE-
vcc oLEARcr,ocr | %mt
CLR CK CE CARtrQ4 Q7 Q2 Q3
Q]
OUT
CK
Ql
.CLR Q? Q6 Q5 Q4
eO Qz Q5 Q6 Qs
CTOCK CLEAX Q?
I z - S T A GBEI N A RCYO U N T E R I4 .S T AGEBIN A R Y

C OU N TE R /OS C ILLA TOR
4040 4060
vcc ett eto eB e9 cluen cr,odn or vcc q1O e8 e9
Q]l QlO Q8 Q9 CLR CK
Qf
Q]?
Q6 Q5 qt Q4 Q3 Q2
12 Q13 QI4 Q6 Q5 Q7 Q4
Q13 Q15 Q14 Q6 Q5
DUALDECADECOUNTER PROGRAMMABLE
DOL.JN
COUNTER
15 .|B 4O1O? DUALBCD
DUALBINARYCOUNTER 4OI03 B-BITBINARY
4520
- Eonn
--' -12
vcc sPE J6
26 28 ?Ql zQo
SPE J7
coy'o
APE
c/cn
CLR JO J 1 J 2 J 3
32
ENCODER
Function
7 4HC r47 1O-TO-4 LINE PRIORITY ENCODER LS147 L6

7 4HC 1 4 8 8-TO-3 LINE PRIORITYENCODER LS148 *4532 16
* SUGGESTED ALTERNATIVE
ENCODER
I O - T O - 4L I N E P R I O R I TE
YN C O D E R B . T O - 3L I N E P R I O R I TE
YN C O D E R
14 7 148
OUTPUT INPI]TS OUTPUT OUTPUTS II'IPUTS OUT?UT
A
D32T9 C"S,5zi-0
aAO
5678C8 567ElrA2A_t
\4 5 I ? 8__9.___9-olto
INPUTS OUTPUTS INPUTS OUTPUTS
33
DECODER
Type Equivalont Equivalent Pin
Number Function LSTTL cMos. Number
74HC 42 BCD TO DECIMAL-DECODER LS42 *4028 16
74HC L3t 3-TO-8 LINE DECODER/LATCH LS131 16
74HC L37 3-TO-8 LINE DECODER/LATCH LS137 16
74HCT137 3-TO-8 LINE DECODER/LATCH LS137 16
74HC 138 3-TO-8 LINE DECODER LS138 16
74HCT138 3-TO-8 LINE DECODER LS138 16
74HC 139 DUAL 2-TO-4 LINE DECODER LS139 4 5 5 6 *, 4 5 5 5 16
74HC 154 4-T0.16 LINE DECODER LS154 'k4515 24
74HC 155 DUAL 2.TO-4 LINE DECODER LS155 * 4 5 5 6 *, 4 5 5 5 16
74HC 237 3-TO-8 LINE DECODER/LATCH 16
74HC 238 3.TO-8 LINE DECODER t5
74HC4028 BCD-TO DECIMAL DECODER 4028 16
74HC45L4 4-T0-16 LrNE DECODER/IATCH *LS154,'tLS159 45r4 24
7 4 H C 4 5 1 5 4-T0-16 LINE DECODER/IATCH * L S 1 5 4 ,* L S 1 5 9 4515 24
7 4 H C 4 5 1 1 BCD TO 7 SEGMENTLlDID (LED) L S 4 7' *. L S 4'8*. L S 4 4511 16
74HC4543 BCD TO 7 SEGMENT LIDID (rCD)
*
LS47,LS48,LS4 4s43 16
t Suggestedalternative
DECODER
BCDTO DECIMALDECODER 3 .T O-BL INE D E C OD E R /LA TC H
42 l3l
ABCD Y! Yl Y2 Y3 Y4 Y5
YOYfY2!3 l4F]6 Y']B 19
B CCK Cl2 01 rt
Yo Y1 Ya vs it vs i6 QID
3-TO-8 LINE DECODER/LATCH 3-TO-8 LINE DECODTR

137 138
Tl 38
B C OQA O2B Cl Y'/
oEe oae or rr sxo

&or
34
D E C O D E( C
Ro n t i n u e d )
BCDTO VER 4-TO-I6LINEDECODER/LATCH
LATCH/DECODER/DRI
SEGMENT
451I 45.|4
INHIBIT
vcc D c sto su s8 s9 slA sl5 sla sl3
!Eaboal IMI D C Slo Su S8 89 gl4 St5 Sl2
OLTBILEDA A BVS6SS4SgSlSeSo
Sz sO 85 s4 Sg S1 Sa SOorO
4-TO-16 LTNEDECODER/LATCH BCD.TO.7SEGMENT LCD

LATCH/DECODER/
DRIVER
4 5 15
4543
INHIBIT
INII. D O SI)S,1 S8 S9 SU, 815 Sl2 fg6dob
Lr' a
A B S?S68ES4S.gSISASO OBDAPIIBI
35
D E C O D E(RC o n t in u 6 d )
DUAL2-T0.4 LINE DECODER 4 - T O - I 6 L I N ED E C O D E R

.|54
139
zYO 2Y1 tt? 2Y3 e2 0]Y15)14 flSYJzYl]
B C D @ elu5Y14u3
Y216Y41516y/18)B
YO Y] Y? Y3
lYO lYL 1Y21Y3 oND S?EE%FrF YrEFtuou
DU AL2 -T O - 4 LI NE DE COD ER 3-TO-BLINE DECODER/LATCH

3-TO.BLI NE DE CO DE R
.|55 237
ffiF-mzfr YO YI Yg Y4 Y5 Y6
YO Yl Y2 Y3 Y4 Y5
1 c r-e frs 1E M. ffi eno
3 -TO-BL I NE DE CO DT R DECODER
BCD-TO-DECIMAL
238 4028
vcc Yo Yl Y2 Yg 14 Y5 Y6
YSYlBCDAYS
AY6
B C E?A E?B Gl Y?
Y2 YO Y'I Y9 Y5 Y6
6EqifrB er Yl
't4 Y2 YO Y9 Y5
36
COMPARATOR
Function
74HC 85 4-BIT MAGNITUDECOMPARATOR LS 85 x 4 0 6 3 ,* 4 5 8 5 16

7 4 H C6 8 8 8-BrT EQUALTTYCOMPARATOR LS688 20
COMPARATOR
4-BIT MAGNITUDE
COMPARATOR B.B IT EQU A LITY
C OMP A R A TOR
B.5 6 BB
vcc AS 82 A? A1 Bf Ao Bo v"6 F= Q Q'/ P'/ Q6 P6 Q5 P5 QL P4
A5 B2 A? A1 81 -AO
=Q Q7 P7 Q6 Po Q5 Ps Q4
B3 BO
Ke l: eP4
DB DB rru,qG
IIJ IN IN our. ou,r Offi
Po Qo Pl Qf Pe Q? P3 Q3
ns <F r- Ds Ds F.e(pexo
+
CASE,ADE INPI'TS OIITPUTS
ADDER
Function
74HC 283 4.BIT BINARY FULL ADDER ts283, LS83 4008 16
ADDER
4-BIT BINARYFULLADDER
283
Bg AS Zs t+ s+ 2+
2z c4
Bz A? Jr et nr oo
37
ALU
TYPC Equivdent Equivalent Pin
Function
lhmbcr ISTTL cMos. lfumber
74HC 181 ARITII}IETIC LOGIC ITNIT LS181 24
7Atrc182 LOOK AIIEAI) CARRYLOGIC LSl82 16
ALU
ARITM.IETIC
LOGICUNIT/FUNCTION LOCKAHEADCARRYGENEMTOR
GENERATOR
*: OPFI DRAIN CT'TPITT
l82
r8l
ff s:I A-a ila e-s Fs d crn++i ril eT v* Fa o? cnGu+r&+y-o c.."
pe o? cn culr(bry o
P}OOPOOSPS P
AOsg S? $1 SO cD I FO FIF?
ol pl oo po og pg p (}rD
B-o fr ss sa sr so ca n rT F-t F? oro
PARI TY TREE
Type Equivdent Equivalent Pin
Function
lrlumbcr I.STTL cMos. Numbcr
74HC280 9-BIT PARITY GENERATOR/CIIECKER LS28O *4531 14

PARITYTREE
PARITYGENERAToR/
9-BIT oDD/EVEN
CHECKER
280
Y@FEITcBA
FBDCB
&%-*
38
LATCH
TYF Rmtio Equinhot nquinlcnt Pln
f.Iumbcr ISTTL cuos. l{umber
74HC 75 4-BTT TTYPE I.ATTE LS75 *4042 16

74EC 77 4.BIT IFfi?E I.ATCII LS77 *4042 14
74HC 259 8-BIT ADI}RESSABI.EI.ATCN LS259 *4099 t6
74HC 279 qIAD s-R'r,ATCH LS279 *4043,*4044 16
74EC 375 OUAI) IFTYPE I.ATCH LS375 r6
74nC 373 OCTAL IFTTPE I.ATGE (3-STATE) rs373,LS573 20
74ncr373 OCTAL IFTTPE I,ATSN (3-STATE) LS373,LS573 20
74EC 533 oimr. rFTrpE LATCH (3-srATE/rNV.) LS533 20
74HC 563 ocral, rFrIr"E r.arcH (3-STATE/rNV. ) LS563 20
74HCT563 OCTAL IFIYPE I.ATCN (3-STATE/IN\I.) LS563 2A
74AC 573 OCTAL IFTYPE IATCE (3-STATE) LS373,LS573 20
74HCT573 OCTAL IFTYPE I,ATCN (3-STATE) LS373.LS573 20
r $tgggstcd dbrnetivr
LATCH
4-BIT LATCH 4-BIT LATCH
75 77
FUil GT IO }I TABI,E FUTICTIOII TABI,E
ITTPUTS OIITPT'TS IIIPT'TS OI'TPUTS
X:DON'T X:IX)NI T
D o c q
CARE
D G Q, 0 CARE
LE LH LS LE
ES HI, SE EL
XL an d-n XL QnG
IQ 2Q 2q dt.zorf) Sq 3Q +q tQ aQcl.a (ilD xC sq 1 q
Ia ID ?DF34 gD ID aQ rD 2lrg3-ll Ycc sD aD llc
8-BIT ADDRESSABLE
LATCH qrAD s-R LATCH
15s 279
FIIUCTIOII TABI,E
ITIPUTS OUTPUT * FOR IrATCEES TIlg
DOUBLE F INTUTS:
s R a
ua qn rFH)Tts F TIrotS
LS E HIOE
HI, L IJ:OXE OT DOTII
r, I, s IUPIITS I,OT
vo rE rF rq s32 sEr si sq
qo (&@Q3a*qss cr?
ql Q2 q3 (xil)
rF rEr r& ro aF zE 8q tlrto
39
L A T C H( C o n t i n u e d )
0C TALL ATCH( 3- S T A T E ) QUADLATCH
373 NONI NV E RTDA E DT AO U T PU T S 375
T 37 3
2
'D
2Q <u
Dl" D3
0 C T A LL A T C H( 3 - S T A T E ) 0 c r A LL A T C (H3 - S T A T E )
533 INVERT EDA D T AO UT PU T S 563 INVERTED DATAOUTPUTS
T563
&o3o?05'F.o?
OCTALL A T CH( 3- S T A T E )
573 N ONI NV E RTDA E DT AO I,IT P U T S
T573
40
R E GI S T E R
TYpe Equivalent Equivalent Pin
Function
74HC L64 8-BIT SIPO SHIFT REGISTER LST64 *4034 T4

74HC L65 8-BIT PISO SHIFT REGISTER LS165 14014,*402L L6
74HC L66 8-BIT PISO SHIFT REGISTER LS166 k4014,x402L I6
74HC L73 QUAD D-TYPE REGISTER (3-STATE) L5173 4076 L6
74HC L94 4-BIT PIPO SHIFT REGISTER LS194A 4OL94,,k40104 16
74HC L95 4-BIT PIPO SHIFT REGISTER LS195A *4035 16
74HC 299 8-BIT PIPO SHIFT REGISTER L5299 ik4034 20
74HC 323 8-BIT PIPO SHIFT REGISTER LS323 *4034 20
74HC 595 8.BIT SHIFT REGISTER/LATCH (3-STATE) LS595 16
74HC 597 8-BIT LATCH/SHIFT REGISTER LS597 L6
74HC 670 4 IÎORDX 4-BIT REGISTER FILE(3-STATE) LS67O 16
74HC4094 8-BIT SIPO SHIFT REGISTER/LATCH
4094 L6
(3.STATE)
REGISTER
8 - B I T S E R I A L - I N / P A R A LO
LEU LTS H I F T S H IFT
8 -BIT P A R A LLE L-IN /S E R IA L-OU T
REGISTER R E G IS TE R
164 165
cLoct( SERIAL
Vcc AJ{ QC QF QE CLEAR CIIJCX v"gINHIBIt o INPUT
QH QG QF QE CK DCBASI
INH
c,1{ {r ofi
clK
BQAQBAOO! EFGHOH
B . B I T P A R A L L E L - I N / S E R I A LS- O
HUI FTT QUAD (3-STATE)
D FLIP-FLOP
REGISTER
173
166
DATA EbIABI,E
INPUTS
SEIV
vcc-foAD H en o F Eeffi- vcccLEAR ].D ?D 3D 4D & (}1
HQHCFE
oIJEA.R lD 2D 3D 4D
SI CLR
CK CK
ABcDINH.
SERIAL CLOCK CND 4Q CI.0CK or.rD

IN INH. CIOCK
41
(Continued)
REGISTER
UNI
4-BIT BIDI RE CT I O NA SH IF T
L VE R S AL 4-BIT PARALLEL- S H IFT
I N/PARALLEL-OUT
REGISTER R EGIS T ER
I94 195
qA QB QC Ou tl QA eB ec QD 0D oK
"_*
CLEAR SO gLEAR 6
SRABCDSL JKABCD
CLEAR D SHIFT Cil[D

SHIIII LEFT
RIOilT
8-BIT BID I RE CT I O NA
UNIVE
L S H IF T
R S AL (3-S
8 .B IT SH IF TR E GIS TE R /LA TC H TA TE )
R EGTST E( 3-
R STATE) 595
299 D IREC T CLE A R
323 SYNCHRONOUS CLEAR
vcc
sHIFr ' '{qo^'^^cIocr
--/w---- flf[ffi
st LEFT
e,, ty'on{a{ -O SCLR
vCC eA SI nCr SCX OH/
s] sL aH' ly'av nlatroo{as cr

QA sI o RcK ScK scLF
so sR
a
s s/qo daadqc/aâ^' aL
QO QD QE QF' QG QH
QB
.g--&rsloo {qe , r/o.l or'sm oNo
OIITPUT VAC
CONTROLS
8-BIT L ATCH/ S HI FRE

T G IS T ER 4 WORD B I T R E G I S TFEIR
LE(3-STATE)
597 670
SLOAD WRITE
SELECiI ENABLE ouTpUTs
RCK $(:KSCLR OH.
DAfA.-r-
vcc D1 wa wBmIffiRffi af aP
scK SclJt
A sI sLoADRcK
Dl W.e, WB Ow OR Q1
B QH,
maz
CDEFOH
B, D4RBR6Q4 Og
D2 D5 D4 RB.RA
-Q 4 Q3
,-t
42
(Continued)
REGISTER
8-BrT SERIALIN/PARALLEL-0uT
SHIFT
REGTSTER/LATCH(3-STATE)
4094
oE q5 Q6 q? Q8 Qsl
8T QS
roKQrQz0SAr
ou)G gr qa q3 qa (x|D
43
3. OUTLINE OF PRODUCTS
3.1 Naming Method of TC74HC Series
TC74HC Series was named by the Standard naming method of JEDEC.

Its formal type number i-s as shor^rn below.
TC74
(5) 0ther sections
(4) Sections for Package type

(P or F)
(3) Change contrr.rl symbol (blank

when there is no change. )
(2) Figures showing functions
(f) Type classification by JEDEC.

(HC, HCU, HCT)
(Example) rcz+ttcT24OF
High speed C2UOS IC which is pin and functionally compatible
with the bipolar 74LS24O device.
Input is designed with TTL leve1, and direct driving from

LSTTL is possible.
'
Package type is plastic llini Flat Package.
(1) Hc, Hcu, HCT
In the high speed CIvlOS, HC series, there are HCU type and HCT
type beside the fundamental HC type. These sections l^/ere decided
by JEDEC in order d prevent the difference i-n electrical

performance produced by input level and existence of buffer even
in the case of C M O So f same function.
44
Input threshold
TyPe Internal stage
vol tage
T\ro stages and
HC CMOS level
above
HCU One stage CMOS 1evel
T\^ro stages and

HCT TTL level
above
Taking inverter as an exampl-er w€ can show the difference of
these types as fo11ows.
TC74HCO4 TC74HCUO4 TC74HCTO4
Logic Di-agram w -+"- w

Input-Output
Vol tage
transfer Er
ir
character-
is tics ?
I
2.5V
vr ll
(2) Classification of functions
Functions are expressed by English numerals of two to five,figures.
In the case of TC74HC Series, there are provided the product
having same pin connecti-on and function with LSTTL, and the
product having same pin connection and fr:nction with 40008/45008
series of standard CD'IOS.
00 n,999 Product of sanp pi-n connection and same
function with 74LS series
(Example) 74L5240 <--+74HC24O
45
4OOOq4O199 . ... Product of satp pin coanection and sane
4500{4599 frnction with standard C}I)S 4ffiOB/45OOB series.
(Erample) 401028 .-* 74EG4Q!O?
TOOO7999 .. .. . Frnction proper to 74HC series. Eouever, sorc

function approaches ISTIT,.
(Exemple) Sam fincElon yith 748C7266 ++ 74LS266.

Eoryener, output is of nornal buffer
' structure.
(not open drain structure.)
(3) Change control symbol
Ttris syfrol is given to clarify the rewision of product stren in-

proverent strLch sill remarkably change the characteristics of
product is "rade. Nornally, it is blank, but if there is a chauge,
hglish characters are given successively from A.
(4) Partitiou for package designator
English characters shorring type of package.
P ....... dual ln line p a c k a g e (D Ip) pl asti c

F . - .. .. . nini flat package (l,FP) plastic
In 1f,748C series, arrow 3fi) nil-l type 24 pfn..package nas

newly developed. By this development, in' the case of rrprt
tyPe, l4lf:6l20l24lpil;s are all unified into 300 nill Eidrh
(7 .62 rm width) .
Alsor'in the case of mini flat "Ft' type , L4lL6l20 pins are all
uaified iito ErA"r 30o nil1 type package (TypE I[, Form A).
46
rn the case of both DIP and MFP types, pin arrangement of same
width and sarr= pitch is adopted regardless of pin nrrmberr and
s o it is poss i b l e to a rra n g e th e p a rts systemati cal l y w hen
designing the printed boJrd, and automatic rnor.rnting can be
eas ily m ade .
(5 ) O t her par t it io n s
In the case of mini flat IC Taping specification, the followlng

indic at ion is a d d e d to th e p a rts n a m e.
f P l or - W 2 (D i ffe re n c e i n s t i cki ng di recti on)
3-2 . Feat ur es
Tg74HC Series has the following features in conparlson with other

standard Logic IC;
(1 ) Hlgh S peed op e ra ti o n : Sa me a s L ST TL
(2 ) Low P ower Dis s i p a ti o n : S a m e a s s ta ndard C InC Sseri es (ut{)

(3 ) Out put Dr iv e C a p a b i l i ty :C a p a b l e o f d i rectl y dri vi ng 10 LS TTL
l o a d s (S ta n d ard output type).
Capable of directly driving 15 TSTTL

l o a d s (Bu ffe r butput rype).
(4 ) H igh Nois e I mmu n i ty : H C/n C U T y p e ... 45y" V C C (Typ.)
HCT Type .. .. . 25%VCC (Typ.)
(5) Wide Operating Vulrage Range i t
H C / H C UT y p e . . . 2 to 6V
H C TT y p e . . . o . , 4 . 5 to 5.5V
(6) tlide operating Temperature Range z -40 to *g5oc
47
(7) Self-contai-ned static electricity protective circuit:
+2000V (min) (All inputsand Outputs)
by EIAJ method
(8) Ample Latch up Capacity: Total input a70mA and above (Restricted
by input protective resi-stance)
Total output +300 mA and above.
(9) Based on the same pin connection and function with LSTTT..
(10) Wide Line up, and products amounting to 180 kinds.
Table 3-1 shows compari-son of characteristics of various logic
famili-es.
Table 3-1 Performance Comparlson of Each Loglc Famlly
HS-Cal,os HS-C2l0S
Paramter (rc74rrc) LSTTL (1'C40H c2los Condition
'serles 'sert es)
Propagation delay time

SnstYP 9ns typ 15ns tYP 1 25ns tlp v D D= 5 . o v
GAIE(C1=15PF)
Maxlmum clock freqency

60t'ctztYP 4SwtztyP 201'fiztYP zyftlztyp Ta = 25"C
J/Kr'F (C1=5Op;
Total temper
QuiescenE Supply Current 0.01uWtYP SmIÎtYP 0 . 0 1 u w t v P 0 . 0 1 u W t Y P ature voltage
(GAIE)
range
VIH 3.5Vmin 2.OVmin 4.OVmin 3.SVrnin vDn=5.0v

Input Voltage
vtl 1.5Vmax 0.8Vmax I .0Vmax 1.5Vmax Total temper
ature range
48
HS-CzMOS HS-CzMOS
Parameter (rc71Hc) LSTII. /t T Cr4i e
0 sH' \ CzMoS Condition
aer1-es se
* 1 V cc= 4.5V
lronI 46min*l 6.4,,,4min*2 0 .36nrA mi n* 36.12r4nin*3 *2 YcC=4.75Y
Output Current
* 3 V 6g= 5Y
rot 4611min 4r6min g.gnxlmin g.36o,4min
Total temper-
ature range
Operating Voltage Range 2"v6y 4 . 7 5 q ' 5. 2 5 Y 2 'r,8V 3 ^, 18V
Operating Temperature -40 ,r,85 "C 0,r, 70"C -40 'r,85 "C -40^85"C
Range
4. EXPLANATIONS OF RATINGS AND STANDARDS
4-I. MaximumRatings
Regarding C MOS IC, the maximumRating is regulated for each

product.
In general, the rnaximumrating value should not be exceeded in

or der t o gua ra n l e e th e l i fe a n d re l i abi l i ty of i ntegrated ci rcui t
pr oduc t s . H e re i s a d o p te d th e n o t i on of absol ute maxi mumrati ng
as the maximuur rating.
Absolute Maximum Rating should not be exceeded even for a rnoment,

and any one standard of ratings should not be exceeded.
When the unit is used in excess of the maximum rating, the
characteristic will nbt recover sonptimes, and in an extreme case,
permanent breakage will be caused.
In designing the circuit, therefore, it is necessary to pay at-
tention to the fluctuation of supply voltage, characteristics of

connecting parts, ambient temperature, and surge of input and out-
put siganl liner so that the maximum rating not be exceeded.
49
Table 4-I indicates cormron rnaximum ratings of TC74HC series.
When the maximum rating of each unit and common rating differ,
the former shall control. As for the meaning of each item,
. refer to Table 4-2.
Table 4-L Absolute Maximum Rating
Pararneter Symbol Value U ni t
Supply Voltage Range vcc -0.5 t' J V
DC Input Voltage vtu -0 .5 '', VCC+ 0.5 V
DC Output Voltage vout -0 .5 ' \,V C C+ 0.5 V
Input Diode Current rrk +20 mA
Output Diode Current rot< +20 mA
+ 2 5 (Standard)
DC Output Current rout + 3 5 (Buf f er)
mA
+ 5 0 (Standard)
DC VCC/GND Current rcc Tzd (Buf fer)
mA
s00 (DIP)*
Power Dissipation Pp m['l
180 (IfrP)
Storage TemPerature Tstc -65 ^, 150 OC
Lead Temperature (10sec) Tf 300 oc
* 5 0 0 m Wi n the range of Ta=40oCT,65oC. In the range of Ta=65'C
to 85"C, derating factor of -10mW/"C shall be applied until 300mtl.
50
a
Table 4-2
Pararneter Symbol Explanation
Indicates the voltage range in which IC does
not cause breakage, deterioratj-on of character-

Supply Voltage vcc
istics and fall'of reliability when voltage is
impressed on Vgg termi-nal.
Indicates the voltage range in which IC does

DC Inpunt
Vttt not cause breakage, deterioration- of character-
Voltage
D C Ou tp ut
vout istics and fal1 of reliability when voltage is
Voltage impressed on input and output terminals.
Indicates the current value at which IC does
Input not cause breakage due to latch up when input

rtx
Diode Current current or output current is fed.
Ou tp u t * Practically, the design in which DC current

ror
Diode Current flows is not recomnendable. When flow of cur-
rent cannot be prevented, adopt the ctrrrent
value lower than this.
Output current indicates the current value which
DC Output rout can be fed for one output.
Cu rre n t
As VCC/CIUOcurrent includes output current, in
Vgg/Gl.Io Current rcc the case of IC having rnany output terminals,
substantial output current is controlled by it.
Indicates consumption power not causing break-

Power
Pp age of IC in the entire operating temperature
Dissipation
range
51
Parameter Sumbol Explanation
Indicates the ambient temperature range not

Storage causing deterioration of characteri-stic and fall
Ts tg
Temperature of reliability when left for a long time in the
state not impressed with supply voltage.
Load Temper- Indicates the conditions when solderi-ng is car-

T1
ature Time ried out after IC is mounted on printed board.
4-2. Reconrnended Operating Conditions
This is the range in which the operation of 74HC series is

guaranteed, and when this range is exceeded, the operation is
not guaranteed even if it is within the maximum rating of 4-I.
Cornmon recommended operating conditi-on of 74HC seri,es is shown
in Table 4-3. When recommended operating condition of each unit
and common reconmended operating conditi-on differs, the former
shall control. As for the meaning of each item, refer to Table
4-4.
Table 4-3 Common Recommended Operating Condition
(a) 74HC Type
Parameter Symbol Limit Unit
Supply Voltage vcc 2c'6 V
Input Voltage vtu 0 ^, VCC V
Output Voltage vout 0 n, VCC V
Operating Temperature Topr -40 tu 85 oc
trrtf 0 q , 1 0 0 0( V C C = 2 . 0 V )
Input Rise and Fal1 Time 0'v 500 (VCC=4.5V) NS
0n,400 (VCC=6.0V)
52
(b) 74HCT Type
Parameter Symbol Limit Uni t
Supply Voltage vcc 4.5 tu 5.5 V
Input Voltage vtu OTVCC V
Output Voltate Vout O .u VCC V
Operating Temperature Topr -40 tu 85 .C
Input Rise and Falling Time tr tf 0tu500 ns
Table 4-4
Parameter Symbol Explanation
Supply Voltage Vcc Indicates supply voltage range guaranteeing

normal theoretical operation of IC.
Input Voltage vrn Indicates voltage range guaranteeing normal

Output Voltage Vout theoretical operation and electric charac-
teristic of IC.
Indicates operating temperature range guar-

0perating Temperature Topr anteeing normal theoretical operation and
elec tri.c charac ter is tic of IC .
Indicates rising and falling time range of

Input Rise and Fall (,u input signal not causing malfunction due to
Time
oscillation of outout.
53
4-3. DC characteristics
Table 4-5 shows DC characteristics of HC Type. As for the meaning

of each item, refer to Table 4-7. Table 4-5 is a standard DC
characteristics Tab1e, and when it differs from individual
characteristic, the latter sha1l control. DC characteristics is
regulated by JEDEC (International standards). In TC74HC series,
all units satisfy this international standard value, and some items
(
guarantee the characteristics surpassing the international
standards. Table 4-6 indicates characteristics Table standardized
by JEDEC.
Table 4-5 TC74HC Series DC Characteristics Table
DC Electrical characteristics
Ta = 25"C
t;
Ta=-40tu85"C
Parameter Symbol Test Condi ti-on
U ni t
MIN. T Y P . },IAX. M I N . MA X .
2.0 1.5 1.5
High-1eve1
vtH 4 . 5 3. 1 5 V
3.15
Input Voltage
6.0 4.2 4.2
**Low-leve1 2.0 0.5 0.5
vtt
Input Voltage
4.5 1.35 1.35 V
6.0 1.8 1.8
2.0 1.9 2.O , 1. 9
**High-leve1
roH=-2ouA 4 . 5 4 . 4 4.5 4.4
Output Voltage
voH vrN=
6.0 5.9 6.0 s.9
V1g or V
vtl I8fi::19;A 4.5 4.18 4.3r 4.L3
* 6.0 s.68 5.80 s.63
2.O 0.0 0.1 0.1
** Low-level
vrN= rol=2ouA 4.5 0.0 0.1 0.1
Output Voltage Vol
VIH or 6.0 0.0 0.1 0.1
V
Vtt 161={41* 4 .5 o.r7 0 26 0 33
IO L = 5.2 m Atr
6.0 0.18 0.26 0.33
54
Ta = 25"C Ta=-40.r85"C
Parameter Symbol Tesr Condirion Unit
I uaa MIN. T Y P . MA X . M I N . MAX.
3 State Output VIN = V1g or Vfl
0ff-s tate roz 6.0 {.5 +5.0
C urre n t vour=vcc or GND
Input Leakage
Current
rtu VIN = VCC or GND 6.0 -rc.1 +1.0
uA
GATE 6.0 1.0 10.0
**Quiescent vrN =
rcc FF 6.0 2.0 20.o
Supply Current VCC or cND
MSI 6.0 4.0 40.0
Note) * Buffer Type assumes 1.5 times value, respectively.

( lrOH | = IOL = 6d, 7.8mA)
** Items guaranteeing the characteristics surpassing JEDEC standards.
Table4-6 JEDECStandardNo. 7A
DC Electrical characteristics
Ta = 25"C Ta=-40185 "C

Parameter Symbol TesE Condition Unit
Vcc M I N . T Y P . MAX. MIN. MAX.
High-1evel 2.0 1.5 1.5
Input
vtH 4.5 3.1s 3.15 V
Voltage
6.0 4.2 4.2
Low-leve1
2.0 0.3 0.3
Vtl 4.5 0.9 0.9 V
Input Voltage
6.0 r.2 L.2
2.0 1.9 1.9

roH=-2ouA 4 . 5 4.4 4.4
High-leve1
VoH
vrN= 6.0 5.9 5.9 V
Output Voltage V1g or
IOH=-4mA* 4.5 3 .9 8 3.84
Vtl
IoH=-52mA* 6.0 s.48 5.34
55
Parameter Symbol Test Condition Ta = 25oC Ta=-40-85t
vcc Unit
MIN. TYP. IqAX. MIN. MAX.
2.0 0.1 0.1

Low-level rol=2oue 4 . 5 0.1 0.1
Output Voltage
vor, 6.0 0.1
VrN = 0.1 V
V 1 g o r V1 1 I91=(nxtr* 4.s 0.26 0.33
I O L = 5 . 2 m A6* . 0 0.26 0.33
'-BF?:?"!;'n"t VIN = V1g or V11
roz 6.0 ]{.5 +5.0
Current VOUT= Vgg or GND
Input leakage
Current I tlt VIN = VCC Or GND 6.0 -t{.1 +1.0
GATE- UA
6.0 2.0 20.0
Quiescent T/
Icc FF 6.0
Supply Current 4.0 4 0. 0
V66 or GND
MSI 6.0 8.0 8 0. 0
Note) * Buffer Type assumes 1 . 5 t i m e s v a l u e , respectively.

(lrOHl=Iol=6mA, 7.8mA)
Table 4-7
Parameter Symbol Explana tion
High level This is an input voltage capable of judging input

Input of IC as r r H r t
level, and the minimuu value is
Voltage guaranteed. Judgement in this case is made by
confirming that it is above the prescribed VOH
when output voltage should be at rr11il
level, and
below the prescribed Vg1 when output voltage
should be at 'rl't
1eve1.
56
Low 1eve1 vtt, This is an i-nput voltage capable of judging input

Input of IC as t'Ltt level, and the maxi-mum value is
Vol tage guqranteed. In thils case, the judging method is
sarrn as VIH.
High 1evel voH This is an output voltage when each input ter-
Output minal is connected to VtH or Vtf, so that the out-
Vo1tage put level becomes rrgfr. In this case, there is
guaranteed the minimum value of output voltage
obtainable when the specified output current

(IOtt) is flown out.
Lo w l e vel Vol This is an output voltage when each input Lermi-

Ou tp u t nal is connected to V1g or V11 so that the output
Vo l ta g e 1evel becomes rrl.rr. In this case, there is guar-
anteed the minimum value of output voltage ob-
tai-nable when the specified output current ( rol,)
is flown in.
Input Current rtu This is the current flowing in the input terminal
when the voltage is impressed on the input ter-
minal of IC. Norma1ly, this current is so small
that measurement is nnde with the maximum value
of supply voltage.
3-state Toz This i-s a l e a k a g e current flowing in the output
Output Off- terminal when the output has become high imped-
l e a k C ur r ent ance, in the device having three state output
terminal or open drain output terminal.
57
Quiescent rcc This is a current flowing from vgg terminal into

Supply IC when V6g or GND level is held without chang_
Current ing IC input, and the maximum value under all
theoretical conditions allowable for measured rc
is guaranteed.
4-4. AC Characteristics
AC characteristics guarantees transient characteristic of produts.

rn general, impressed input waveform is so set as to have
amplitude of vcc-cun level and rising and fatl time of 6ns.
Table 4'8 shows the meani.ng of each item of AC characteristics,
Fig. 4-I indicates the output connection diagram of measuring
time, and Fig. 4-2 illustrates the measured waveform.
Table 4-8
Parame ter Symbol Drawing No.

Explana tion
Output trlH Indicates the time during which the out-

R isi n g Tim e put voltage (VOl, VOH) rises from L0% to
Output Fal1- TTHL 9O7", and the time during which the output
ing Time voltage falls down from 9 0 " / "t o LOZ.
58
Drawins No.
Parameter Symbol Explana tion
HC HCT
Propaga tion tpLH Indicates the delay time, i.e., af ter in- (1)- ( 2 )-
Delay Time tpHL put signal is given and until output re- (i) (i)
sponse is made. tpLH is the case in which

trtrrr level rr11tf
the output changes from to
level, and tpHL is the case in which the

rrHrf level to
output changes from 1tL"
0utput dis- tPLZ Indicates the delay time, i.e., after a
ab l e Ti m e tpHZ signal is given to the output control t€r-
minal and until 3 state output becomes
high impedance state. ( r )- ( 2 )-

( iii) (iii)
Output t pzL Indicates the delay time, i.e., af ter
Enable Time tpzH signal is given to the output control
terminal and until 3 state output be-

ttHtt level
comes rttrfr level or from the
high impedance state.
Minimum tg Regarding a certain data, indi-cates the
Set up time in which the data must be added and
Time held, before the input regarding that data
(clock input, etc.) changes. For in-
stance, when the data is read in at a

(1)- ( 2 )-
rise of next clock pulse, it is neces-
(ii) (ii)
sary to add data before the rising of
clock pulse, maximum value of ts.
Minimum Hold rh Regarding a certain data, indicates the
Time time in which the data must be held even
after the input regarding that data
(c1ock input, etc.) has thanged.
59
Drawing No.
HC HCT
Minimum t r em Indicates the minimum time, i.e., after re

Rernoval Time leasing of asynchronous input (cJ-ear, pre-
set input, etc.) and until receiving of
next operation input (clock, etc.)
Minimum tw Indicates the minimum pulse width at which (1)- ( 2 )-

Pulse ilock input, etc. is accepted as a normal (ii) (ii;
IÎidth signal.
Max. Clock fuRx Indicates a limit clock frequency at which

Frequency IC carries out normal operaiton.
Input Indicates the capacity between input and

ctu
Capacitance GND.
F ig.4 -1 O ut put Conne c ti o n D i a g ra m. vcc
Meaeur i ng To Outqut
Point Terminaf
To. output Measurins
Termi na 1 Point
r'"
CMOSOutput Open Output
vcc
i.ieaeurinr4 T Note) C1 contains the capacity
Pornt
s1 J
I R
- ' . L- of probe, etc.
i'o output
Termi na L
T cL
L 1""
3 state output
60
Fig. 4-2 S wit c hing C h a ra c te ri s ti .c s T e s t l rl aveform
(1) H C TyPe
i.) tTLH, tfiIL, tpLH, tpHL
t1 6ns
90%
vcc
I NPUT
50|/a
trul ro% GND
voH
]NVERTING
CUTPUT
ii) twr t", th, trem
t,1 6ns 6ns
eo% vcc
CLOCK
o.%
INPUT
C}ND
vcc
DATA
INPUT 50%
GND
ttHl
voit
OUTPUT
vot
vcc
S E T, R E S E T
oT PRESET
GND
61
iii) tpLZ, tpl/.Zt tpL, tpZJ/.
tr 6ne t1 6ns
Vnn
CUTPUT
50%
DISABLE
qND
f
*PLZ
v6H(4ss )
O U T P U T :L O W
TO OFF
vor,
vott
n rtmnrrm i'iir nrr
vUIrUl.-t:l-L\t.rl
TO OFF
v61(4No)
OUTPUTS OUTPUTS
DISABLED ENABIJED
( 2) HCT T y pe
i) tTLH, ttttl, tpLH, tpHL
ty 6ns
INPUT
INVERTING
OUTPUT
62
ii) twr t"t, thr trem
6ns
3.0v
CLCCK
INPUT
GND
trr(l)
&ov
DATA
INPUT
GND
von
OUTPUT
vcl
tpul
&ov
sET,RESET
or PRESET
GND
iii) tpLZ, tpHZ, tpZL, tpZll
tr 6ng t1' 6ns

3V
OUTPUT
DISABIJE
GND
\pzr
von(lvcc )
OUTPUT: IrOW
TO OFF vor,
tpzu
vott
OUTPUT:HIGH
TO OFF
Vol(:<clll)
OUTPUTS OUTPUTS
63
5. How TO READ LOGIC SYMBOL AND TRUTH TABLE
5-1. How to read Logic Symbols
Table 5-1 shows the basic logical block used in high-speed CMOS
rc. The theoretical chart printed in individual technical

data of each product is composed of the- basic block shown in
the tab1e. This logical chart is based on MIL-STD-806B, and
clocked inverter and transmj-ssion gate. employ specific symbol.
Table 5-1 Basic Logical Circuits
Logic Symbol Logical Equation or Truth Table
Inver ter A=>r B a--o)-n
NAND Gate
f-D,'- c f; _D-c C=A B=A*B
NOR Gate $=Nn--c $ €-c C=A*B=A
AND Gate
fi{F-c t _D*c A+B
i-Dci-5o_c A-.8
6 A B X: Dont t Care
Clocked . td Ld-
Inver ter a*fo B A --Xtt H H L
Zz High
(Note 1) H L H Impedance
L X Z
F 6 A B
Transmission
Ga te
(Note 2)
A -#F' H
H
H
L
H
L
X: Dont t Care
Zz High
t6 Impedance
L X Z
EXCLUSIVE-OR A
Gate B :fD-c C= (A+B) (A+B)
64
Table 5-1 (Continued)
Circuit Function Logic Symbol Logical Equation or Truth Table
EXCLUSIVE-NOR
Gate $ :1f>-. c=(a.B)+(A.B)
S R D CK a
H L x X H X: Dodt
D-Type
a L H X X L Care
Fl i p Fl op
a L L H -r H A: No
L L L .r
-t-
L Change
L L X QnA
S R J K CK a
H L X X X H
L H X X X L
L L L L -|- qnA
J / K Typ e J aJ
CK -cK
L L L H _r L
Flip Flop K aK L L H L -r H
L L H H _r Qnv
L L x X -l_
QnA
x Donrt Care
A No Change
V Toggle
Note 1) Clocked Inverter vcc
Clocked inverter ha3 the circuit shown in -s

o-1
Fig. 5-1. In this figure, Ql and QZ are
' P-channel MOS FET, and Q3 and Q4 are
ll-channel MOS FET, and four FET are all con- "{
nected in series from Vg6 to GND.
s*1
rr11rrlevel,
If 6 signal i-s at Ql and Q4 turn
oDr and can b e regarded as a mere inverter
composed of Qz a n d Qf.
Fig. 5-1 Clocked Inverter
65
When I signal i-s atrT,ftlevel, both Qf and Q+ turn off, and
irrespective of the condition of A i-nput, the output B becomes
high impedance condition cut off from both Vgg and GND.
That is to ssy, clocked inverter can be applied as a switch to
cut off input and output,
Note 2) Transmission Gate
Transmission gate has the circuit s h o r n r ni n Fig . 5-2. As shown

in this figure, Ql is P channel MOS
FET and QZ i.s N channel I.OS FET, and vcc

z
. l
these are connected in para1le1.

rN'/our cuT,/lN
If d signal is at "H" level, both Qf
and QZ turn on, and a signal can be
given
Tn.
from either direction. Further, / Gllr)
if 6 s ignal is a t ttl tt l e v e l , b o th Q1
Fi g.5_2 Transmi ssi on Gate
and QZ turn off , and a si-gnal cannot
be passed.
5-2. How to Read Truth Table
Table 5-2 indicates the explanation of symbols described in

Tru th T able.
Table 5-2
Synbol Explana tion
H High Level (Indicates stationary input or output level)
L Low Lerrel (Indicates stationary input or output level)
ftlrr to rt11rr.
-J- Indicates leading edge changing from
66
Symbol Explana tion
-1_ Indicates trailing edge changing from ttlrt

"Ht' to
X (nither ttHtt ItLrf)

Donrt care or
z High impedance state
a....h Input level of stationary state of each input of A to H.
Level of Q just before the realization of input condition

Qo indicated in Truth Table.
Qn Level of Q just before inputting of active edge (Jorl_l .
JL One tlltt leve1 pulse
Lf One
ttl.tt
level pulse
6. COMMONELECTRICALCHARACTERISTICS
6-1. Supply Current Characteristics
(1) Qui-escent supply current
In the case of CI'{OS, under the condition in which input is

fixed at tT,tt ttHt'level, either
or, N-channel FET or P-channel
FET turns off. For this reason, the current
following from Vg6 to GND becomes only the reverse-direction
saturated current of PN junction and the surface leakage cur-
rent due to the stain of chip surface alone, and becomes the
current of less than several nA at room temperature.
(2) operating supply current
The operating supply current of high speed CMOS fC can be

considered as the sum of the following ttatt and rrbrr.
67
rrafr The switching current to charge and discharge each
capacity added to the gate output when the gate in the
ci-rcuit including output buffer makes inversion.
tt6rt
The through current flowing when P-channel FET and
N-channel FET which eonstitute gate during inversion time
turn on transi.ently at the same time.
When rise time and fa1l time of input signal are small (about
6 ns) r through current of gate is usually negligibly small

in comparison with switching current. For the reason, the
operating supply current is governed by internal capacity of
IC And charging and discharging current of load capacity.
By obtaining the total sum (Power Dissipati.on Capacitance:CPD)
of the capacity connected as a load to the gate operating in
the ci-rcuit, the mean operating supply current can be decided
as follows:
IOO (opr.) = fin.CpO.VCC (6-1)
For.the inversion of gate output from low level to high level,
it is necessary that the electric charge

vcc corresponding to CI.VCC is supplied from
corresponds to the mean current to be
supplied from Vgg line to IC during that
period.
68
rn the actual rc, operating gate exists in plural number,
and their respective load capacity and inversion frequency
a re dif f er ent . T h e re fo re , o p e ra tl n g suppl y current as rc i s
a s f ollows :
rno (opr) = VcC.lrrr.ar'
As fn is certainly ai.ri"ible by integer of input frequency

(.fin1 , the gate operating with fn/m frequency can be considered
equivalently as rhe capacity of
+.
Hence, the above equation can be developed as
Ioo (opr) = VCC.fin.i C*

Im
rn equat ion ( 6-1 ), th e fi n a l i te m i s defi ned as cpD .
Here, cpf and rcc (opr) are obrained by raking TC74Hc74p

as an example- connection diagram at the measurement
time is shown in Fig.6, and it is assumedthat 265ttl
was obt ained i n th e m e a s u re d rc c (o pr). rn thi s case,
CL = 0, and IC C i s n e g l i g i b l e .
Thus, from the above

equation,
Û*P_D= rcc (opr.)

@TffN
Cf,n
f:] rrdHz
.trrt
E -
265 x 10-6
CK s' (T;107
f
z D
= 53 (pF)
Fig. 6-1
69
Nex t , by V CC = 5 V , fIN = 8 MH z , C P D = 53pF (ti si ng gnl y one
c ir c uit ) , I C C (o p r) a t th e ti me o f load capaci ty C tr =
50pF (Q output only) can be obtained as follows:
I C C( o p r . ) = CpD'VCg'fin * Ctr'Vgg'fOUT
= (53x 10-1t).5. (8 x 10u)+(50x10-r2)
.5. (4 x 106)
= 3.I2 (mA)
As Cpp under standard operating condition is described in a
separate data sheet, operating supply current can be calculated
for each unit separately.
However, in the specific application such as crystal oscil-

lation, it becomes supply current characteristics controlled
by through current, and the calculation result by Cpp cannot

be used.
6-2. Output current characteristics
The output current characteristics of TC74HC series can be
devided into standard type and buffer type.
IC of standard type is capable of directly driving 10 LSTTL,
and guarantees VOO-VOU:0.37V, VOL-<0.33V in the entire temper-

ature range. Alsoi in buffer type, it is possible to directly
dri.ve 15 LSTTL under the same conditions.
70
Fig. 6-2 shows the standard output current characteristics of
each type when used at the supply voltage of 4.5V.
Fig. 6-2 Standard Output Current Characteri-stics
High level output current Low level output current

characteris tics characteris tics
output voftoge VgH-Vgg(V)

-3 -2 ..1 0
Pa p^ AA
d< c{
ta:?fc(TYP.
9E )
H . v tv
.^ ! E ;J
-IU .{ /\ q.n
5 .Y
OFI C)F
P P
-20 P'
P p20
Ta:gb'C( MIN. ) FI
o 1a:g5l(MIN. )
-tn d -t
-" 0) o ]n
o q)
_l r-l
-40
s
Ta:zb"dtyp. ) u
,.1
012- 345
IJow level output voltoge VoL(V)
(i) Standard TyPe

High level output current Low l evel output current
charac teris tics charac teri sti cs
Iiqh feve-l- output voftoge Vog Vgg(V)
ta:a s"C( t ..p )
P,^
i< +:{
0 oE F E tn
lrv OvE"
tFJ
.10 OH
--
c)
P
1a:35'Q( MI N )
P
20 Jon
P
P
._an
-l "10
0) -1
c)
|-' >o
o-
e1
b0 F
'1a:2 VgC:45V +
5lQ( TYP '-l Low Ievel- output vol-toqe Vg1(V)
(fi) Buffer Type
71
(trtote) Solid line shows stanilard characteri.stics chart. In the
actual case, there is a variation depending uPon the
samples, and so, adopt the broken line and separete
standard values when making design.
When the structure of device is decided, the current flowing
in MOS FET is determined by gate voltage V6g and voltage VDS
between source and drain.
In the actual IC, the gate voltage of output step IOS FET be-
comes nearly Vgg or GND level. The.refore, if IVCSI = VCC is

considered, the following equation is realized in rion-
saturation zone3
. ros = ( 12Vos (vcs- vr) -vos2l
If, Vpg is made constant, IDS is proportional to Vgg-V1. In the
satura tion' zorJle,
IoS=f(VCS .-Yy)z t
Th u s , it is pr op o rti o n a l ' to (VC C- V T )2 no t by . Here, V1

_VDS
is the threshold voltage pfoper to I-{OSFE T, and i s set at a
v.a 1 ue of , about 0 .7 V i n T C 7 4 H Cs e ri e s .
Fi g . 6- 3 s hows su p p l y v o l ta g e - o u tp u t c urrent characteri sti cs

o f st andar d t y pe o u tp u t. T h i s fi g u re i ndj -cates standard val ue.
No te t hat t he v a ri a ti o n o f o u tp u t c u rre n t at the ti me of l ow
supply voltage becomes large in comparison with that at the
time of 4.5V
72
vgg-vsH (v)
5432
vcc:2'ov
Ta: 5t
3.rr v
_2.5v =
'r
l- 7;: r -10
-20
4
s,sv
4 .ov# -30
H I 7 tl
H
r.f
o
4.5
5.OV (-
5.5V
v -1/
^/
I/
-40
-50
H
rl
o
-60
6.OV
Vg6:2.0V
-10
-0L2345
vol, (v)
Ig1 Characterietics Igg Characterietics
F ig. 6- 3 S ta n d a rd O u tp u t C u rre n t C haracteri sti cs
6-3. AC Electrical Characteristics
(1) Supply voltage dependence
T r ans ient c h a ra c te ri s ti c s o f rc s u c h as propagati oi i del ay ti me

and maximum ope:ating frequency are determined by delay time
of inner gat e o r ri s e ti me a n d fa l l ti me of output buffer.
Internal delay is considered to be chiefly due to intepfal effect

of on resistance of MOS FET and load capacity, but as the
internal capacity does not remarkably depend upon supply
voltage, the drain current characteristic of MOS FET determines
the dependability of AC electric characteristics on supply
vol tage .
Fig. 6-4 shows the dependability on supply voltage of propaga-

tion delay time i-n a representative gate IC.
73
\
In JEDEC, the coefficient of dependability on supply voltage
is decided as follows as the standard. In the worst case,
adopt the broken line indicated in Fig . 6-4 which was made
on the basis of JEDEC standard.
Table 6-1 Calculation llbthod of AC Standard Value

(excepting ft"tRX)
vcc Ta = 25"C Ta = -40 't,85 "C
2.0 5.00x 5.00Y

4.5 x Y=1.25X
6.0 0.85X 0.85Y
Table 6-2 Calculation Method of fUeX Standard Value
vcc Ta = 25"C Ta = -40 n, 85 oC
2.0 0.20x 0 .20Y

4.s X Y = 0.80X
6.0 1.18X 1 .18Y
-l lr
d
t\ I
o
\
4J \
<dz I
-l
h.
CD
tr
p<!
xa
\ ts.
_- ---
I . t
,oint" ..roorro*ruur.cul
F i g . 6-4 Dependabilit y o n Su p p l y V o l ta g e o f P r opagati on D el ay Ti me (Gate IC )
74
(2) Load capacitance dependence
rn TC74HCseries, output current has been widely improved in

comparison with the conventional 40008/45008 series, and
load can be driven at high speed.
""p""!.ty
Howeverr 4s output impedance is decided when supply voltage

is determined, rise time and fall time of output waveform,
or propagation delay time will increase in proportion to an
increase of load capacitance.
Fig. 6-5 indicates the load capacitance dependence of output

rise time and fal1 time at supply voltage of 4.5V, while
Fig. 6-6 shows the load capacitance dependence of propagation
delay time.
Standard Type Buffer Type
3,zo Ezo
Fl Fl
t-r F{
P p
d |T1
sr €10
dts dF
4J to P
U U
trq)
.-ll
C0 .d @ .'+
.Fi P .,-r P
ii l.
U U
Pc 0
15'A
q- u F.: 0 50 100
P F I
0 50 100 i i Lood capacity cL (pF)
Oq{ UH
Lood Capaci ty Cf, ( pF)
Fig. 6-5 Load Capacitance Dependence

of tTltt, TTIIL
(s ta n d a rd c h a ra c te ri s ti cs)
75
Standard $pe Buffer Type
ID o
E E
.d rl
P P
>o >o
alc rt Fl
OFI OFI
€E! dE
A
g+t
A
H+t
o-
..r !E
P>l
.tA
3. t A5
QP or5
at a,
A A
o o
t{ k 50 100
ft *
rcT
Ioad. capactty (1,t) Load Celnclty C1, (pF)
Fig. 6-6 Load Capacitance Dependence of tpLH' tpHL

( s t a n d a rd c h a ra c te ri s ti c s ) o
In TC74HC serLes, AC characteristics of 50pF during load
capacitance is guaranteed. Therefore, ProPagatlon delay time
during load capacitance other than the above is obtained by
the f ollowing eqr:ation.
(Example) High level propagation delay time in the case of load
capacitance of XpF.
tpln (x) = d (X - 50) + tpLH (50)
A: I{igh leve1 propagation delay time increase rate
per unit load capacitance (ns/pF)
76
Table 6-3 Load Capacitance Dependence of AC Electrical
Characteris tics (ns/pF)
Sta n d a rd O u tp u t Buffer Output

Tlpical va1rc Limit value Typd-cal vaLtre Limit value
( T a= 2 5 ? e ) (Ta = 85'C) (Ta = 25"C)- (Ta = 85'C)
0.33 0.83 0.22 0.55

tttH, tTHL o. r 2 0.24 0.08 0.16
0.09 0.16 0.06 0.11
o.L7 0.43 0.13 0 .33

tpt fi, tPHL 0.96 o.L2 0.05 0.10
0.043 0.77 0.038 0.068
Table 6-3 indicates increase rate per unit capacity of AC

electrical characteristics having load capacitance dependence.
In the case 'of h e a v y c a p a c i t a n c e load, it is necessary to make

calculation by using the limit value in this table.
6-4. Temperature Parameters of Various Characteristics
In TC74HC series, 3D operation in a wide temperature range of
such as -40 to 85"C is guafanteed. This chapter shows how the

switching time and output current are influenced by temperature.
(1) Temperature Characteristi-cs of Output Current
Fig. 6-7 indicates temperature dependence of output current.

In this figure, solid line shows the temperature dependence
in standard sample. Therefore, at the time of designing, use
the broken line indicated as the worst case.
77
t_40 VCC:45V 140 V6g45V
rour
AIOUT:_:XLOO C1 :5OpF
f orrn( Ta:Z5'C)
1?0 120
N tPd
N ltnd
-:
F{
tpd( Ta:P5"C)
P 100 o 100
o
4J
80 80
io -20 ?0 40 A.r 100 -40 -20 0?040 100

Ta ("c) ra (")
Fig. 6-7 Fig. 6-8
(2) Tmeperature Characteristics of Propagation Delay Time
Fig. 6-8 shows temperature dependence of propagation delay
time. Solid line in this figure indicates standard temper-

ature dependence at Gate IC., At the time of designing,
therefore, use the broken line indicated as the worst case.
7. PREcAUTIONS IN HANDLING
7-L. Electric Static Discharge
CI"OS IC has very thin gate insulation oxide film. When high
voltage i-s applied to this gate electrode (input of CMOS IC),
oxide film directly under the gate causes dielectric breakdor^rn
sometimes. In TC74HC seriesr 6s shown in Fig. 7-L, resistnace
and diode are added to all input terminals in order to protect
CMOSgate from such high voltage. However, protecti-ve circuit
may not necessarily be effective against accidental high
voltage, care must'be ful1y taken in handling it.
78
Futher, 8s parastic diode is formed
between each termi-nals as indicated
vcc v cc -
in Fig. 7-L, thermal breakage and
Input
I1 Output
latch
may sometimes
voltage
up due to
exceeding
excessive
be caused when the

current
the ratings is
t1
* applied between each terminals.
ND GND -J
Therefore, care must fu11y be taken
at the ti-me.of assembling and
adj ustment.
Note) As input protective

Fig. 7-L Input Protective Circuit,
Output resistance, poly silicon
Equivalent Circuit
resistance of 20O to 400f1
is used.
(1) Electrostatic Discharge Test Method
Fig. 7-2 shows electrostatic discahrge test method In Fig.

7-2, test j-s conducted with
C = 200pF, R = 00. Table 7-L
Vnn
shows the results of electro-
static discharge test ap- Input
or
plied to a r.pr"""rrtaEive ^?f- Output
_ola
t y pe of T C 7 4 H Cs e ri e s .
| |
vt GND
I n- t he t es t o f th e a b o v e
TT
L t
m et hod s t an d a rd i z e d b y E IAJ ,
it is acknowledged that +200V
Fig. 7-2 Test Cireuit
will practically withstand an
ordinary service condition. As shown by Table 7-L Toshibats
TC74HC series has ample capacitance.
7g
In p u t Output
Name Impression of Impression of Im pressi on of Impression of
* voltage - voltage * voltage - voltagd
TC74HCOOP 300v -300v Above 1000V Above -1000V

TC74HC O4P 400v -350v Above 1000V Above -1000V
TC74HC 74P 300v -300v Above 1000V Above -1000V
TC74HC138P 450V -350v Above 1000V Above -1000V
TC74HC24OP 350V -350v Above 1000V Above -1000V
TC74HC373P 350V -350V Above 1000V Above -1000V
C = 200pF, R = 00, Impression frequency three times
Table 7-L Test Result
7-2. Precautions in Handling
(1) Transportation and Storage
As input and output terminals of unmounted CI'{OS IC are in the
state of high impedance, they are apt to receive induction
from the surroundipg chargep body, space electric field, and
human body. For this reason, it"is necessary in transporting
and storing them to use dielectric mat, metal case or alumi-
num foil box, so that each terminal of IC may become at same

potential.
As TC74HC series is inserted in a maga zine given no-charging
treatment at the time of shipment, do not take it out from
the maga zine unnecess arLLy. Especially, avoid to use plastic

or vinyl container which is apt to charge static electricity.
80
(2) Assembling
I^lhen installing C M O SI C o n t h e p r i n t e d board, it is necessary
to protect the electric equipment, working stand and operators

from static electricity by.making grounding. It is advisable
to ground the working stand by spreading metal plate or alumi-
num foil on the surface. Grounding of operators should be
made through the resistance of about l Mft so as to prevent an
electri-c shock. It j.s convenient to make grounding through
metallic ring or metallic watch band. Also, it is advlsable
not to wear working clothes make of chemical fiber. Further,
it is necessary to periodically check electri-c equipment to
insure absence of electric leakage.
When shaping the lead wire during the packaging of IC, 1t is

advi-sable to use pincet or similar jig, so that stress may
not be given to the root.
l,lhen stori-ng or transporting the completely assembled printed

board, short circuit the termi.nals of printed board or cover
the entire board with aluminum foil, so that input terminal

of IC may be opened.
(3) Soldering, washing
I,rlhen making so]deri-ng by using soldering lron and tank, carry

out the work at the temperature of 260"C or below within 10
seconds. It is confirmed that the reliability of TC74HC
series is never affected when subjected to a temperature

stress to the stopper of lead at 260"C for 10 seconds.
Use a soldering iron having no leak at its end. It is re-
commended to use A class iron having insulation resistance
exceeding 10 M0.
81
When using soldering tank, it is necessary to make grounding
so as to prevent the potential of soldering tank from becoming
unstable
After soldering IC on the printed board, cleaning i.s made to
remove flux, etc. For this cleaning is used flux removing
abluent or cleaning method utilizing ultrasonic wave. Care
must be ful1y taken for the selecti-on of this solvent so at
to prevent the effect given to the packagg and mark of CMOS IC.
In general, it is advisable to use Freon series.
In the case of ultra'sonic cleaning, it is necessary to prevent

the stress due to resonance from being imposed on IC or
printed board. For this purpose, it is needed to consider such
washing method that the main body becomes a shade against a
vibrator, and also a cleaning time of less than 30 seconds.
(4) Adjustment, Test
. lrlhen making adjustment and test af ter the completion of

printed circuit board, it is necessary to check absence of
soldering bridge or crack on the printed board before switch-
i-ng on supply power. As CMOSsystem requires only small
supply current, it is well to apply current limitation when

uraking test by using marketed constant voltage pohTer source.
Inlhen mounting and dismounting printed circuit board on and
from the socket, never fail to cut off power supply before-
hand.
82
lrlhen surveying each part of printed board with probe during
the test, care must be fully taken to prevent contact of tip
of probe with other si-gnal or poT^rer li-ne. when surveying
place is previously determined, it is advisable to erect a
special test pin.
When test is conducted under high temperature and low temper-

aturer it is necessary to take grounding of constant temper-
ature oven, and the inside set must be on or in the inhuctive
ma terial .
This item excepting one part, is also applicable when CMOSIC

single trnit is tested.
/
8. PREcAUTIoNSIN DESIGNING
cIRCUITS
8 -1 I nput P r oc e s s i n g
(1 ) P r oc es s in g o f u n n e c e s s a ry g a te
I nput of C MOSIC h a s s o h i g h i mp edance that l ogi cal l eve1

bec om es u n d e rfi n e d u n d e r o p e n c o ndi ti on. In thi s case, i f
input is at internediate level,
the transistors of both p-channel
and N-channel becorne continuity

state, and unnecessary supply
current flows.
Therefore, as shown in Fig. 8-1,

be sure to connect unnecessary
input line to VCC, GND or other
input and output whose logical
Fig. 8-1 Treatment of Input
1evel is decided
83
rn t he c as e of c M o s , i f s o l d e re d p a rt has bad contact, mul -
fu n c t ion of s y s te m o r i n c re a s e o f s u p pl y current will be
ca u s ed. T her e fo re , c a re mu s t b e ta k e n at the ti me of w i ri ng.
(2) Input processing of printed circuit board
trlhen input terminal of printed circuit board is connected

directly to CMOS input, CMOS input
is brought to electrically floated
condi-tion as in the case of IC
single unj-t when transported or
stored as a single uni.t of printed
board. It is advisable, therefore,
to connect previously to VCC or GND
through resi-stance in the printed
circuit boardr 3s indicated in F::lookf}
Fig. 8-2.
Fig. 8-2 Input processi ng
;of pri nted ci rcui t board
8- 2 D e sign of P ower S o u rc e
-srnall
trn general, cMos requires consumption current in com-
pari-son with other bipolar digital rc, and therefore it needs
only srnall capacity power supply. However, from its operational-
requirement, cMoS consumes poh/er in spike state, and therefore
it is necessary to keep high frequency impedance of 'pohrer
source at low level
rt is adviasable to make wiring of power source (v6g) line

and GND line thick and short, and to insertr eis high
frequency fliter, once 0.01 gF to 0.1 ttF capacitor between V6g
GND for each IC.
""a
84
Also, it is recommended to insert a condenser of about 10pF
to 100uF between power supply entrance and GND as low frequency
filter. As rRean supply current considerably differs depending
upon operating frequency of system, existence of condenser
load, risi-ng and falling of input signal
and supply voltage, attentj_on must be
specially given in the case of simple
poT^rer source by Zener diode, oE battery
driving. .tlhen there is overshooting
or urtdershooting during transient time
of supply pourer, use filter etc, so
Fig. 8-3 Example of
that the maximuri rating rnay not be
increase in driving capacity
exceeded.
8-3 On Output Short-circuit
rn Tc74Hc series, buffer is added to the output, and both

flow-out (IOH) and flow-in (IOf,) current driving are possible.
. For this reason, excessive current flows in C IvXCS
output when
f r 1 1 r rl e v e l frtrrf
output line is shorted with GND line or
level:output line is shorted with Vgg 1ine. particularly,
when the supply voltage is high, arlowable loss of package

is exceeded by this current, and therefore care must be taken
not.to cause output short circuit.
:
It i s of c our s e i m p o s s i b l e to d i re c tl y connect ordi nary outputs
to g e t her , but in th e c a s e o f rc w h i c h h as 3 state output,
wired OR ls pernitted provided that more than two outputs
d o n ot bec om e en a b l e s i mu l ta n e o u s l v .
85
Further, in order to improve driving capacity, it is possible
to connect the gates in the sane package as shown in Fig. E"'3.
8-4 Effect of Input of Slow Rise Time and Fall Time
When the waveform of slow rise
ti.me or fall time is im- F/Y I FA_Z
pressed to CMOSinput, it some-
times happens that output
tends to oscillation around VtU

(threshold voltage of circuit) CLOCK
of input waveform in the case
of gate IC. This is because CIJOCK
CMOSgate becomes linear ampli-

Qt
fier equivalently in the vicin- i-r
tl
ity of VtU, and minute power
(a) Normal operating waveform
source ripple and noise compo-
nent are amplified in the out-
put and appear. CLOCK V11C1
v11c2
nr
For the purpose of preventing
n,
the above, it is necessary to
insert high frequency filter (b) Malfunction waveform from

at the time of VthCl>Vs6C2
condenser between VCC and GND
of oscillating IC, or to use

CLOCK V 15C2
Schmitt trigger IC.
V15C1
In the case of TC74HC series, nt
excepting HCU type, Schmitt
n,
trigger IC, inpu.t rising and
falling time is regulated as (c) Malfunction waveform from

at the tire of VthCl <V16C2
shown in Table 8-1 in the
recommended operating condi-- Fig.8-4 Example of Malfunction

Eions. Please fo1low this condition.
86
Fig. 8-4 shows an example of malfunction when shift counter is
constituted by using type D flip-flop of another package.
In this case, malfunction is considered to be

caused by the difference of circuit threshold level of
respective D type flip f1op.
Now,let circuit threshold level of F/F-I be V56Cl, and that
of F/F-2 be VttrC2. Then, ds shown in Fig. 8-4, time dif ference

,\t is formed while the rising waveform of clock pulse cuts
the respective circuit threshold voltage, and thus malfunction

takes place.
The fo1 lowing c:ondition is required for insuring normal
operation:
ht < tpd (Cf - Q) + tset-up
In this case, there a possibility of malfunction even

ir
though input signal is within the standard value of Table 8-1.
Therefore, care must be speciallv taken for sequence circuit

clock input.
Table 8-1 Standard Value of Input Rising and Falting Time
I tem Symbol Limit Uni t
Q r , 1 0 0 0 ( V C C= 2 . 0 V )
Inp rrt Ri sing
tr, tf 0 ' \ , 5 0 0 ( V C C= 4 . 5 V ) NS
and Falling Time

0 t u 4 0 0 ( V C C= 6 . 0 V )
87
8-5 Precautions for hliring
(1) Output waveform distortion
As output impedance of TC74HC series is considerably low in

comparison with the conventional standard ql4OS IC, distortion
is sometimes caused in the output waveform depending upon L
component of wiring, when the wiring connected to output end
is long or when capacitance is connected between signal line
and VCC or between signal line and GND. Thereforer'when
designing the printed board, take care not to make signal
wiring length tbo 1ong. In the case of both side printed
board, it is ideal to limit signal wire length to 30cm or
less. Especially, in the clock signal line, distortion of
waveform causes malfunction
(2) Precautions for arrangement
Output of TC74HC series has quick rising and falling time,

and makes ful1 swing at VCC-GND, and so it becomes a noise
source of other signal,. Therefore, it is desirous to locate
it separately from a part which is sensitive to a noj-se of
analog circuit. Also, care must be taken for the reduction

of load number and curtailment of wiring length.
(3) Termination
From j-ts physical and electrical factors, TC74HCseries is

apt to cause overshooting and undershooting, and this leads
to malfunction of circuit or breakdown of passive IC. These

troubles can be prevented to some extent by terminati-ng the
end of signal line. Fig. 8-5 indicates examples of general
termination
88
T
t
(a) Termi-nation by C R (b) Termination by' Diode
Fig. 8-5 Examples of Termj-nation
8-6 Interface
(1) Input and output interface
When rhaking some processing with CMOS system, most systems

make exchange of signals with.external circuit or mechanism.
These input and output signal lines are naturally made long
in many cases, and have distributed inductance or reactance.

Therefore, if directly connected with CI'OS, they will give
rise to various troubles.
Conceivable serious troubles mav be the malfunction due to
induced noise, and the destruction of input/output element
due to surge. To cope with these problems, reduction of
signal line impedance (driving impedance) or inserti-on of
noise eliminating circuit on the receiving side is applied
for the fornrEr, while surge protective measures are taken
for the latter.
Fig. 8-6 illustrates an example of making noise . surge pro-
tection on the input side'.
89
(a) and (b) of this figure show an example of absorbing
noise by integrating lnput waveform by RC. (c) and (d)
indicate an example of protecting cl.os from input surge.
Fi g . 8- 7 giv es a n e x a mp l e o f o u tp u t i n te rface. These are

only one example, but in any case, some protection should be
given to an interface involving long signal line.
T
(a) uoise
7n
Ki11er I (u)
T
N o i e e Ki l-1er 2
vcc
vco
,\
G
(c) Surge Protection 1 Surge Proiection
tt Z
F ig. 8- 6 C M O S In p u t Pro te c ti v e C i rcui t
J_
(a) Surge Protection f

4i
(u) output Driver
\fl,iEi+
(") output Driver P (a) Surge Protection Z
Fig. B-7 Output Protection/Driving Circuit
90
(2) Interface of C MOS IC
In the case of mutual interface between CIOS IC, input im-

pedance of CMOS has so large value that limitation of fan out
may not be so large. However, there is actually need to
consider fall of propagation time due to adding effect of load
capacity and an increase of power consumption.
As input capacity of C M O Si s about 5 pF per input, if 10
fan outs are taken for example, load capacity of 50pF is given
by it, and further, line capacity on the printed board must
also be taken i-nto account. This shows that the processing
speed of system is controlled not only by circuit constituting
method but also bv fan out.
When constituting a system with CI"OS IC, it is recommended
to examine fan out by taking these points into cosideration.
(3) Interface between, different CMOS families
The problem to be considered between different CI,OS families
i-s difference of supply voltages between families. trlhen
different C MOS families are used with the same power source,
it is all right to pay attention to Ehe hazard due to the
propagation delay time di.fference, but in the case of dif-
ferent power source, the voltage level converting circuit is
needed
Fig. 8-8 shows an interface method from the standard C MOS
oprating at 6V^, 15V to 74HC. The npst popular method is to
use C MOS (4O4gB/40508) which-Ias level shift function as
shown in this figure.
91
4 0 4 98140508 has d i o d e o f GND side diode only, and is so
co ns t r uc t ed t ha t c u rre n t does not flow in the power source
(VCC) of 5V system even t h o u g h v o l t a g e of 15V is impressed.
On the otherhand, an interface from 74HC to standard C MOS

can be reali zed by using TC5020BP of level shift use IC, as
indicated in Fig. 8-9(a). Fgrther, it is also possible to
use discrete transistor as shown in Fig. 8-9(b). The circuit
employing discrete transistor can of course be used for power
inversion.
(4) Interface with TTL
When driving TII- with TC74HC series, input and output voltage
leve1 can be connected in that state. without trouble. Fan out
is decided by output current of CMOS IC and input current of
TTL. Its example is shown in Fig. 8-10..
61F"15V
4049P,,/50B'
l
i+
!Lt
I
t_
S t a n d ard C llOS
L___
Level
___J
thifter
L
Fig. 8-€ Standard C D'0S + 74HC Interface
92
5V 6V-15V
-l Ll
T C 5 O? O B P
14HC Standard C MOS
(a) Example of using level shifter IC.
6V- L5V
- - --.{
rl
LJ
,/ oHC Stand.ard C I1OS

Level conversion
by transi-stor
(b) , Example of using transistor
Fig. 8-9 7 4 H C .+ S t a n d a r d C MOS
vgc:5v
Fan Out Number
Standard TyPe Buffer Type
TTL 2 3
S TTL 2 3
LS TTL 10 15
ALS TTT, 20 30
Fi g . 8 -1 0 T C 7 4 H C+ TTL I n t e r f a c e
93
In this way, TC74HC series is capable of directly driving
various TTL devices.
On the other hand, when driving TC74HC series from TTL, it is

necessary to convert output voltage level of TTL to input
level of 74HC. Normally, in this case TCT4HCT series which
has same input level with LS TTL are used. Input current of
TCT4HCT series is very sma11 like that of TC74HC series, and
therefore no burden is imposed on the driving side 74L5, and
the speed also does not fa11 so much. Therefore it can be
said to be an effective method. Another npthod is to use
pul1 up resistance as shown in Fig. 8-11.
Rp:Pulfup Resistance
( z_loK())
Fig. 8-11 TTL + TC74HC Interface
(5 ) In te r f ac e wit h C P U
At present, as the peripheral supporting logic of micropro-

cessor of rnany NloS and cMoSr T4LS series is used universally.
As TC74H} series has the same speed with 74L5, it can naturally
be used as microporcessor peripheral logic.
94
As for an interface between C MOS CPU and 74HC seri-es, there
is no problem because both are CMOS. At present, however,
prio-rity of NI.OS CPU ls higher, and interface of NIOS to CMOS
must be taken into consideration.
Output of m o s t N M O SC P U d e f l - e c t s up to near VCC, but as shown
in Fig. 8-12, 8s outputs qf both driving MOS and load MOS
are.constituted with enhancement typer ro deflection takes
place until VCC. For this reason, in order to certainly
carry out the signal transfer from NMOS CPU to 74HC, it is
easy to use 74HCT series which has an input of TTT. l-evel .
When connecting 74HC series, pull up resistance is used as
indicated in Fig. 8-12.
Next, driving of NMOS CPU from 74HC series can be connected
without difficulty. This is because, normally input of NMOS
is of high impedance like C MOS, and DC fan out need not be
taken into consideration.
Rp:Po1]up Resistance
--
d
._l
Fig. 8-L2 NMOSCPU Interface
95
8-7 Latch-up
Ldtch up is a phenomenon peculiar to CMOS, and is also called

scR, (silicon controlled Rectifier) phenomenon. During the
normal operation time, if excessive voltage and current
caused by big noise or accidental surge are applied on the
input and output terminalr or supply source amplitude is
sud.denly fluctuated, abnorrnal current flows between Vcc and
GM, and this abnormal current continues to flow even.though
the'disturbance signal is cut off, and finally puncture is
caused. Latch-up is a name given to such phenomenon.
once the latch-up takes place, the former condition is not

restored unless the power supply is cut off or voltage is
lowered, and an overcurrent continues to flow be\ween vcc and
GND. rt this status is left a1one, destruction of element
such as melting of wirlng will take place.
(1) Cause of latch-up
Fig. 8-13 shows-.r, .Orrrvalent circuit due to parasitic

el.ement. NPN transistor Qz is formed in p-well of NMos
side while PNP transistor Qr is formed in N-substrate of
PMOSside, and parasitic resistance exists between terminals.
As is clear from the current path through the medium of
parasitic element indicates in this figure, these parasitic
elements constitute Thyristor.
96
OUT
Poly Srlicon
resistance
b00
I
L__ -+-
P-[te ]-1
N-SubBtrate
Fig. 8-13 Internal Equivalent Circuit of CMOS IC
For example, if current flows into the N-substrate frorn ex-
ternal causes, voltage drop takes place in resi.stance Rs of
the N-substrate, and this causes to turn on parasistic

transistor Ql, and current flows towards GND from Vcc through
the medium of resistance Rw of P-Well. When current flows
in Rw, voltage drop takes place at both ends of Rw, Q2 turns
oD, and further, supply current flows through Rs. As a re-
su1t, the voltage drop at both ends of Rs furthers increase,
Qf and QZ are left in the turn-on state, and the supply
current further increases.
In this way, if the voltage drop takes place in resistance
Rw of P-ldell and in resistance Rs of N-substrate, latch-up
occurs, and therefore, the following causes are considered.
97
@ To make input voltage higher than V66 + Vp
(Q S o f F i g . 8-13 turns on)
@ To rnake input voltage lower than GND - Vf

(Q S o f F i g . 8-13 turns on)
o To make output- voltage higher than Vgg + Vp

(QS of Fig. 8-13 rurns on)
@ To make output voltage lower than GND - Vp)
o To raise supply voltage VCC above the rated value and to

c aus e br eak d o u m , (T o d i re c tl y fl o w current i n R w or R s)
Here, VF is the forward voltage between base and emitter of

parasitic bipolar transistor Q3 - Q4.
(2) Latch. up strength measurement

'8-14
Fig. illustrates measurement er<ample of latch up strength.
As indicated in Fig. 8-14, latch-up is induced by flowing
current into input terminal (O injection) or flowing current
out of output terminal. (O Injection), and the current value
at that time is ueasured. Table 8-2 shows the,results of
Latch-up Strength Test of representative types of TC74HC
series. As indicated here, TC74HC series have ample margin
such as input of above + 70mA and output of above + 300mA

against the maximum rating of * 20mA.
98
Inn
-{>
rcc
( a) Me a su r ing c ir c uit of (E Injection (b ) Measuri ng ci rcui t of O Injection

strength of Input Terminal s trength of Input Terminal
vcc
IN OUT
GND
rcc
(c) Measuring circuit of @ Injection (d) Measuring circuit of e Injection

strength of Output Termirral strength of Output Terminal
Input condition to make measured, terminal "Htt level.

Input condition to m a k e m e a s u r e d t e r m i n a l "Lt'level.
Fig. 8-14 Latch-up Strength Measuring Circuit by
Current Feeding System
99
Table 8-2
Unit : mA
Type Class Input @ Input Q Output @ Output Q
74HCO2 NOR.GATE Above 70 Above 70 A'bove 300 Above 300

u04 INVERTER Above 70 Above 70 Above 300 Above 300
74 D-P/r Above 70 Above 70 Above 300 Above 300
138 LINE DECODER Above 70 Above 70 Above 300 Above 300
375 D-Latch Above 70 Above 70 Above 300 Above 300
(Note 1) As for thisexceedj-ng !On'A and the output exceeding

input
t300mAr Do measurement is made as t h e r e i s a p o s s i . b i l i t y of
br eak down o f e l e m e n t.
(3) Countermeasures
'is (2),
As ample rnargin provided for latch-up as explained in
there is no problem in using the unit within the standards.
However, for the interface part having the possibility of
receiving excessive surge., it is recommended to add the
'
protective circuit as indicated in Fig. 8-15.
Fig. 8-15 Example of Latch-up Preventive Method
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