Chapter 11

BUILT-IN SELF-TEST

The BIST Concept

Capability of a circuit (chip, board, or system) to test itself
On-line BIST: testing occurs within the normal operating
environment of the system
concurrent (information or modular redundancy)
non-concurrent: during idle states (diagnostic software or microcode)

Off-line BIST: testing occurs when the circuit is put in a test

mode
functional (diagnostic software or microcode)
structural (built-in hardware)

Chapter 11 - BIST
page 2 of 24

Copyright Miron Abramovici, 1997

December 1997

(Structural Off-line) BIST

TEST
PATTERN
GENERATOR
(TPG)

CIRCUIT
UNDER
TEST
(CUT)

OUTPUT
DATA
COMPRESSOR
(ODC)

Test Controller

Chapter 11 - BIST
page 3 of 24

Copyright Miron Abramovici, 1997

December 1997

Input Patterns for BIST

Stored patterns
hardware: ROM
limited applicability

Exhaustive patterns (2n for n-input combinational block)

hardware: counter or modified LFSR
complete
practical for n < 24

Pseudoexhaustive patterns
hardware: constant-weight counter, LFSR and XOR, LFSR and SR
circuit must be partitioned or segmented into exhaustively tested blocks
almost complete

Chapter 11 - BIST
page 4 of 24

Copyright Miron Abramovici, 1997

December 1997

Input Patterns for BIST...

Pseudorandom patterns
hardware: autonomous LFSR generating a maximal-length sequence
have properties similar to those of random sequences

Algorithmic patterns
hardware: finite state machines (sequencers)
used to test circuits with regular structures

Pseudo-deterministic patterns
hardware: modified LFSR to also generate specified vectors

Chapter 11 - BIST
page 5 of 24

Copyright Miron Abramovici, 1997

December 1997

Autonomous Linear Feedback Shift Register

external-XOR LFSR

internal-XOR LFSR

D
C

page 6 of 24

D
C

Copyright Miron Abramovici, 1997

December 1997

Using an LFSR as a TPG

An autonomous LFSR with characteristic polynomial P(x),
starting in the state 00...01, generates a periodic sequence given
by 1/P(x)
The maximum-length of an LFSR sequence is 2n-1 (all states
except 00...0)
The characteristic polynomial of an LFSR generating a
maximum-length sequence is a primitive polynomial
A maximum-length sequence is pseudorandom:
the number of 1s and the number of 0s differ by 1
it has the same number of runs (strings of identical bits) for 0s and 1s
1/2 of the runs have length 1
1/4 of the runs have length 2
...
Chapter 11 - BIST
page 7 of 24

Copyright Miron Abramovici, 1997

December 1997

Example

1
0
0
1
0
1
1
1

1
1
0
0
1
0
1
1

1
1
1
0
0
1
0
1

Characteristic polynomial P(x) = x3 + x + 1 is primitive

Chapter 11 - BIST
page 8 of 24

Copyright Miron Abramovici, 1997

December 1997

Problems in Testing with Pseudorandom Patterns

some faults are random-pattern resistant (low detection
probability)
detected by only by a few vectors
every such vector assigns many PIs

non-functional patterns applied to the CUT may be troublesome

how many vectors to apply?
have we reached the desired fault coverage?
Methods to reduce or eliminate random-pattern resistance:
weighted pseudorandom patterns (add filter between TPG and CUT)
insert additional control points
insert additional observation points via a parity tree

Chapter 11 - BIST
page 9 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST Design
1. Analyze the logic and partition the circuit
Unstructured (Random) logic
Regular structures (RAM, ROM, Register file, FIFO,...)

2. Select subcircuit-level BIST techniques (depending on structure

and fault models)
3. Select architectural features for BIST elements
embedded within the CUT or separate
centralized (shared) or distributed

4. Controller design
5. Integrate with boundary-scan (BIST controlled from the
boundary-scan bus)

Chapter 11 - BIST
page 10 of 24

Copyright Miron Abramovici, 1997

December 1997

Tasks of a BIST Controller

inhibit system clocks
control test clocks
seed registers
keep track of the number of test patterns
scan out (or compare) signatures
communicate with other test controllers

Chapter 11 - BIST
page 11 of 24

Copyright Miron Abramovici, 1997

December 1997

Centralized and Separate BIST Architecture

CUT1

TPG

D
I
S
T

D
I
S
T

ODC

CUTn

DIST = Distribution system

Test Controller

Embedded: TPG and ODC built from dual-use resources

page 12 of 24

Copyright Miron Abramovici, 1997

December 1997

Distributed and Separate BIST Architecture

TPG1

TPGn

CUT1

CUTn

ODC1

ODCn

Embedded: TPGs and ODCs built from dual-use resources

Chapter 11 - BIST
page 13 of 24

Copyright Miron Abramovici, 1997

December 1997

Factors Influencing BIST Architecture Selection

Test application time (degree of test parallelism)
Fault coverage
Cost
Performance degradation
Level of packaging
Complexity of replaceable (repairable) units
Repair strategy
factory
field

BIST Hierarchy
Chapter 11 - BIST
page 14 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST Hierarchy
System

TI
TI
IC

TI

...

IC

TI

ATE
or
Maintenance
Processor

Board

...
TI
IC

TI

...

IC

TI

Board
Chapter 11 - BIST
page 15 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST for Unstructured Logic

1. Exhaustive
2. Pseudoexhaustive
3. Pseudorandom
Priority: 1, 2, 3
May use a combination of techniques

Chapter 11 - BIST
page 16 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST for Modules with Regular Structure

General model for a regular structure:
two-dimensional array of identical
cells surrounded by dedicated blocks

...
Input Reg.

Operations:
Read/Write: RAM, FIFO, Register file,
CAM
Read only: ROM, PLA

Problem: interference between closely

packed cells leads to non-standard
fault models
Regular structures require very
specific test algorithms

.
.
.

D
e
c
o
d
e
r

Cell array

Output Reg.

...

page 17 of 24

Copyright Miron Abramovici, 1997

December 1997

Fault Models for Register File

Stuck fault: in cells and in the BIST logic
Transition fault: a cell fails to undergo a 01 or 01 transition
during a write operation
Retention fault: a cell fails to retain its value after a certain time
Destructive read fault: reading a cell changes the contents of a
different cell
Coupling fault: a transition in one cell changes the contents of
different cell during a write operation
Pattern-sensitive fault: the contents of a cell is affected by a certain
pattern in the contents (or in the changes) of other cells
Addressing fault: the address decoder selects
no address
a wrong address
multiple addresses
page 18 of 24

Copyright Miron Abramovici, 1997

December 1997

Example: Testing Coupling Faults

Static coupling: state of cell i forces a change in the state of cell j in
the same word
Principle: set any pair of neighboring cells to complementary values
0

0 ...

1 ...

Dynamic coupling: writing (or reading) cell i forces a change in the

state of cell j in a different word
Test

j
(good)

j
(faulty)

initially

write i 1

read j

Chapter 11 - BIST
page 19 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST for Testing Regular Structures

Chip-level:
add controller to generate required algorithms
use parametrized macrocells (megacells, cores) supporting BIST

Board-level:
use existing components supporting BIST
use a programmable chip able to implement different test algorithms

Reusable solutions are cheaper

Minimal implementation time (BIST logic predesigned)
Cost shared by several projects

Chapter 11 - BIST
page 20 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST Register File (Lucent Macrocell)

Parameters:
M address bits (1-7)
W words
N bits per word (3-32)

BIST interface:
BIST = start self-test
BC = BIST complete (done)
BF = BIST flag (GO/NOGO test
result)
BFC = BIST flag check (initiate
test to check that BF is not stuck at 0)
may be controlled by boundary scan

Chapter 11 - BIST
page 21 of 24

Copyright Miron Abramovici, 1997

December 1997

Register File Test

Notation
W0 = Write 0
W1 = Write 1
R0 = Read 0
R1 = Read 1
W0 = write walking 0
W1 = write walking 1
R0 = read walking 0
R1 = read walking 1
N = number of words
= access addresses 0N
= access addresses N0
= access one address

1. W0
2. (R0, W1, W0, W1)
3. (R1, W0, R0, W1)
4. (R1, W0, W1, W0)
5. (R0, W1, R1, W0)
6. (W0, R0)
7. (W1, R1)

Guaranteed 100% coverage for all the faults considered

Chapter 11 - BIST
page 22 of 24

Copyright Miron Abramovici, 1997

December 1997

Controlling BIST Macrocells by Boundary Scan

BIST Resource Interface
Controller (BSBRIC)

Functional inputs

mapped as a 2-bit boundaryscan user test data register

uses the boundary-scan protocol
to activate the BIST test and to
report the test result
uniform interface for macrocells

Functional outputs
BIST
Macrocell

BC
BF

BFC
BIST
1149.1
control inputs

BIST
Resource
Interface
Controller
(BSBRIC)

1149.1
control outputs

TCK

Chapter 11 - BIST
page 23 of 24

Copyright Miron Abramovici, 1997

December 1997

BIST Cost-Benefits Analysis

- All costs of full scan
- Area: 10-25%
- Fault simulation may be expensive
+ Short test application time
+ Eliminates/reduces the need for ATPG
+ High fault coverage (maximal for exhaustive and
pseudoexhaustive patterns)
+ High defect coverage
+ Good diagnosis (less than full scan)
+ May be applied hierarchically: chips boards system field
Chapter 11 - BIST
page 24 of 24

Copyright Miron Abramovici, 1997

December 1997