2 12presentation

Building a SystemVerilog
Universal Verification
Component with the
Incisive Plan-to-Closure
Methodology
Session 2.12
David Long, John Aynsley
and Jonathan Bromley,
Doulos
Slides 2006-7 Doulos Ltd. All rights reserved.
Building a SystemVerilog
Universal Verification Component
CONTENTS
Introduction
The Verification Plan
Assertions, Coverage and Constraints
SystemVerilog Testbench Architecture
SystemVerilog for Verification
SystemVerilog has verification features not found in VHDL or Verilog:
Assertions and a temporal sequence language

Functional coverage
Constrained random test vectors
Dynamic creation of transaction objects
Extensible classes for verification components and transactions
Features to avoid simulation races between test bench and DUT
But can be a steep learning curve for RTL/HDL designers
Some sort of framework for block-level test benches would help
Incisive Plan-to-Closure Methodology
URM (Universal Reuse Methodology) / Design Team Verification
Module-Based with Classes URM
SystemVerilog verification environment
Classes for transaction objects
Does not require expertise in OOP (polymorphism, virtual methods, etc)
Guidelines to create reusable Universal Verification Components (UVCs)
Our experience of actually getting this to work ...
System to be Verified
Bus-based sub-system with CPU

CPU, Serial IO and arbiter are RTL SystemVerilog
module
module
rom
rom
Bus
module
module
sram
sram
module
module
cpu
cpu
module
module
bus_arbiter
bus_arbiter
module
module
serial_io
serial_io
UVC used with Verification Plan
Identify key requirements and verification strategy for each

requirement before starting to develop testbench!
Assertion-Based Verification - uses SystemVerilog property to

continuously check design behaviour, e.g. interface protocol
Following
Following aa write
write there
there must
must not
not be
be aa read
read for
for at
at
least
least 11 clock
clock cycle.
cycle.
The
The
one
one
write
write
clock
clock
enables
enables should
should each
each stay
stay high
high for
for only
only
cycle
cycle
Coverage-Driven Verification - uses SystemVerilog covergroup

to record how many times a condition has been met
Forward
Forward and
and backward
backward jump
jump operations
operations for
for every
every step
step
in
in the
the range
range 11 to
to 15
15 should
should be
be exercised.
exercised.
The Verification Process

Specification
Specification
Verification
Verification Plan
Plan
Management (prioritisation, resource utilisation)
RTL
RTL Design
Design
Features
Features
Assertions
Assertions
Coverage
Coverage
Model
Model
Measure
Coverage-centric process
Tests
Tests
Verification
Verification
Environment
Environment
Run
Simulation
Simulation
Copyright
Slides2006-7
2006-7Doulos
DoulosLtd.
Ltd.AllAllrights
rightsreserved.
reserved.
Documents
Documents
Code
Code
From Features to Tests

Features
The
The NBG
NBG output
output
pin
will
reflect
pin will reflect the
the
status
status of
of the
the
internal
internal FAIL
FAIL
register
register bit
bit
A
checksum
A checksum
calculated
calculated using
using
the
the CCITT-16
CCITT-16
polynomial
polynomial is
is
appended
appended
Back-annotate
coverage
Tests
Coverage Model
program
program test1;
test1;
random_seed
random_seed == ...
...
verif_env(bus_if)
verif_env(bus_if)
covergroup
covergroup ...
...
covergroup...
covergroup...
covergroup...
covergroup...
covergroup
covergroup
cover
cover ...
...
cover
cover ...
...
Tests inspired
by features
program
program test2;
test2;
constraint
constraint {{ ...
... }}
verif_env(bus_if)
verif_env(bus_if)
5:
5: ifif (en)
(en)
5:
q
5: q <=
<= d;
d;
0:
0: else
else
Features grouped by specification, implementation, and functionality

Many-to-many mapping between features and coverage points
Coverage and tests implemented in verification language or scripts
Grade tests by coverage achieved, bugs found, run times etc
Copyright
Slides2006-7
2006-7Doulos
DoulosLtd.
Ltd.AllAllrights
rightsreserved.
reserved.
URM Testbench Structure

Top
Test program
initial
Test definition
Sequence task calls
env
Bus Slave UVC

Bus Master UVC
Master Agent
Sequence
driver
Config
Protocol check
Coverage
collector
Monitor
BFM interface
Environment contains
multiple UVC modules
Protocol-specific
"Interface UVCs" built
from 1 or more agents
Monitor
BFM module
Interface encapsulates
bus signals
DUT interface
DUT
Agent in SystemVerilog URM

Same architecture as eRM
Master Agent
Sequence
driver
Config
Module containing "standard" tasks

Class object
Protocol check
Coverage
collector
Monitor
BFM interface
Standardized task calls
Monitor
BFM module
DUT interface
DUT
Task calls, events
Sequence Pushes Transactions

module
module ex_seq_driver_m
ex_seq_driver_m
(( ex_bfm_if
ex_bfm_if bfm_if
bfm_if );
);
ex_bfm_trans_c
ex_bfm_trans_c cur_trans;
cur_trans;
Sequence
driver
BFM interface
BFM module
DUT interface
DUT
Template for new transactions

task
task simple
simple (( ...
... );
);
ex_bfm_trans_c
ex_bfm_trans_c trans;
trans;
trans
trans == new
new cur_trans;
cur_trans;
assert(trans.randomize());
bfm_if.put
bfm_if.put (( trans
trans );
);
endtask
Independent of
endtask :: simple
simple
BFM details
task
task scenario_x
scenario_x (( ...
... );
);
...
...
simple
simple (( ...
... );
);
Sequence built from
other sequences
...
...
Transaction Class
class
class ex_bfm_trans_c;
ex_bfm_trans_c;
rand
rand ex_bfm_trans_s
ex_bfm_trans_s tx;
tx;
Transaction data struct
ex_bfm_trans_c
ex_bfm_trans_c
tx
...
min_delay
max_delay
15
enable_
delay_
constraint
tx_delay_
range
...
int
int
int
int
bit
bit
min_delay;
min_delay;
max_delay;
max_delay;
enable_delay_constraint;
enable_delay_constraint;
Control
constraint
constraint tx_delay_range
tx_delay_range {{
Constraint
if
if (enable_delay_constraint)
(enable_delay_constraint)
tx.delay
tx.delay inside{[min_delay:max_delay]};
inside{[min_delay:max_delay]};
}}
function
function new();
new();
min_delay
min_delay == 1;
1;
...
...
endclass:
endclass: ex_bfm_trans_c
ex_bfm_trans_c
Constructor
Derived Transaction Class

class
class derived_trans_c
derived_trans_c extends
extends ex_bfm_trans_c;
ex_bfm_trans_c;
constraint
constraint tx_delay_odd
tx_delay_odd {{
if
if (enable_delay_constraint)
(enable_delay_constraint)
tx.delay[0]
tx.delay[0] ==
== 1;
1;
}}
function
function new();
new();
super.new();
super.new();
...
...
Additional constraint
Calls base class constructor
Handle can point to derived class

task
task simple
simple (( ...
... );
);
ex_bfm_trans_c
trans;
Shallow copy
trans
trans == new
new cur_trans;
cur_trans;
...
...
Includes derived class constraints
The BFM Interface

interface
interface ex_bfm_if;
ex_bfm_if;
ex_bfm_trans_s
ex_bfm_trans_s trans;
trans;
Sequence
driver
BFM interface
BFM module
Standardised access to any BFM

copied from URM library
task
task automatic
automatic put
put
(( input
input ex_bfm_trans_c
ex_bfm_trans_c TT );
);
...
endtask
endtask
task
task automatic
automatic get
get
(( output
output ex_bfm_trans_c
);
...
DUT interface
DUT
endtask
endtask
task
task automatic
automatic done
done
(( input
);
...
endtask
endtask
...
BFM Pulls Transactions
Sequence
driver
BFM interface
BFM module
DUT interface
DUT
module
module ex_bfm_m
ex_bfm_m ((
ex_bfm_if
ex_bfm_if bfm_if
bfm_if ,,
input
input wire
wire DUT_clk
DUT_clk ,,
...
... );
);
ex_bfm_trans_c
trans;
Interface
DUT signals
initial
initial
forever
forever begin
begin
Blocking
bfm_if.get(
bfm_if.get( trans
trans );
);
drive_transaction(
drive_transaction( trans
trans );
);
bfm_if.done(
bfm_if.done( trans
trans );
);
end
end
task
task drive_transaction
drive_transaction
(( input
);
...
...
Signal wiggles
Monitor Detects Bus Activity

module
module ex_bus_mon_m
ex_bus_mon_m ((
input
input wire
wire DUT_clk
DUT_clk ,,
Monitor
...
... );
);
mem_write:
mem_write: cover
cover property
property ((
@(posedge
@(posedge DUT_clk)
DUT_clk)
first_match(
first_match(
bus_if.wr
bus_if.wr
##1[1:$]
##1[1:$]
bus_if.wack
bus_if.wack ))
)) cover_mem_wr(bus_if.addr,
cover_mem_wr(bus_if.addr, ...);
...);
Called when sequence matches
DUT interface
DUT
property
property after_we;
after_we;
@(posedge
@(posedge bus_if.clk)
bus_if.clk) disable
disable iff
iff
(bus_if.reset)
(bus_if.reset)
bus_if.we
bus_if.we |=>
|=> ((
!bus_if.we
!bus_if.we &&
&& !bus_if.re);
!bus_if.re);
endproperty:
endproperty: after_we
after_we
assert
assert property
property (after_we);
(after_we);
Functional Coverage
Coverage points do not reveal how conditions are met

SystemVerilog covergroup can record sampled value occurrence
in bins and cross-coverage between coverpoint pairs to
measure Functional coverage
Performed by coverage collector module
Writing to Coverage Collector

module
module ex_bus_mon_m
ex_bus_mon_m ((
input
input wire
wire DUT_clk
DUT_clk ,,
...
... );
);
ex_trans_fifo
ex_trans_fifo tx();
tx();
Coverage
Collector
Interface "channel"
ex_cov_collector_m
ex_cov_collector_m c1(.trans(tx));
c1(.trans(tx));
Called when sequence matches
Monitor
DUT interface
function
function void
void cover_mem_wr(...);
cover_mem_wr(...);
mem_trans_t
mem_trans_t tdata;
tdata;
...
...
tx.put(tdata);
tx.put(tdata);
Call interface method
endfunction
endfunction
...
...
DUT
The Coverage Collector

module
module ex_cov_collector_m
ex_cov_collector_m ((
ex_trans_fifo
ex_trans_fifo trans);
trans);
addr_t
addr_t addr_cp;
addr_cp;
Mirror registers
mode_t
mode_t rw_cp;
rw_cp; ...
...
Coverage
Collector
Monitor
covergroup
covergroup cov_mem_acc;
cov_mem_acc;
mon_addr:
mon_addr: coverpoint
coverpoint addr_cp
addr_cp {{
bins
bins all[]
all[] == {{ [0:15]
[0:15] };
};
ignore_bins
ignore_bins bad
bad == {0,5,8};
{0,5,8}; }}
...
...
mem_w:
mem_w: cross
cross mon_addr,
mon_addr, mon_rw;
mon_rw;
endgroup
endgroup
cov_mem_acc
cov_mem_acc mem_c
mem_c == new;
new;
DUT interface
DUT
always
always
begin
begin ...
...
Blocking
trans.get(tx);
trans.get(tx);
addr
addr == tx.addr;
tx.addr; ...
...
mem_c.sample();
mem_c.sample();
Instance
program vs. module

SystemVerilog program-level code:
Test program
initial
program
Randomization, classes
Postponed sampling and updating
Dynamic creation of objects
Master Agent
Sequence
driver
Config
SystemVerilog module-level code:

Protocol check
Coverage
collector
Monitor
BFM interface
Monitor
BFM module
module, interface
Verilog simulation semantics
Static object hierarchy
DUT interface
DUT
Test Configuration and Control

program
program test_p();
test_p();
initial
initial
begin
begin
randcase
randcase
60:
60: begin
begin
derived_trans_c
Transaction template
derived_trans_c t;
t;
tt == new;
new;
env.master.a0.seq_inst.set_generated_trans(t);
env.master.a0.seq_inst.set_generated_trans(t);
end
end
Sequence generator
40:
40: begin
begin ...
...
endcase
endcase
start_test();
start_test();
...
...
#100;
#100;
end_test();
end_test();
Alternative test cases
URM Package methods
Conclusions
Testbench architecture consists of modules plus a program
Test program can pass randomized transactions to sequence driver

Does not require expertise in object-oriented programming
Test program is compact and easy to modify
DUT, BFM and sequence driver are independent
Classes used for transactions only
Coding style similar to Verilog and VHDL
Uses "standard" infrastructure provided by UVCs
Assertions check protocol throughout simulation

Coverage from properties and covergroups recorded in coverage database
Copyright
Slides2006-7
2006-7Doulos
DoulosLtd.
Ltd.AllAllrights
rightsreserved.
reserved.

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Building a SystemVerilog

The Verification Plan

Assertions, Coverage and Constraints

SystemVerilog Testbench Architecture

SystemVerilog for Verification

SystemVerilog has verification features not found in VHDL or Verilog:

Assertions and a temporal sequence language

But can be a steep learning curve for RTL/HDL designers

Some sort of framework for block-level test benches would help

Slides 2006-7 Doulos Ltd. All rights reserved.

Incisive Plan-to-Closure Methodology

URM (Universal Reuse Methodology) / Design Team Verification

Module-Based with Classes URM

SystemVerilog verification environment

Classes for transaction objects

Does not require expertise in OOP (polymorphism, virtual methods, etc)

Guidelines to create reusable Universal Verification Components (UVCs)

Our experience of actually getting this to work ...

Slides 2006-7 Doulos Ltd. All rights reserved.

Bus-based sub-system with CPU

Slides 2006-7 Doulos Ltd. All rights reserved.

UVC used with Verification Plan

Identify key requirements and verification strategy for each

Assertion-Based Verification - uses SystemVerilog property to

Coverage-Driven Verification - uses SystemVerilog covergroup

Slides 2006-7 Doulos Ltd. All rights reserved.

The Verification Process

From Features to Tests

Features grouped by specification, implementation, and functionality

URM Testbench Structure

Bus Slave UVC

Agent in SystemVerilog URM

Module containing "standard" tasks

Standardized task calls

Task calls, events

Sequence Pushes Transactions

Template for new transactions

Slides 2006-7 Doulos Ltd. All rights reserved.

Transaction data struct

Slides 2006-7 Doulos Ltd. All rights reserved.

Derived Transaction Class

Calls base class constructor

Handle can point to derived class

The BFM Interface

Standardised access to any BFM

BFM Pulls Transactions

Monitor Detects Bus Activity

Coverage points do not reveal how conditions are met

Performed by coverage collector module

Slides 2006-7 Doulos Ltd. All rights reserved.

Writing to Coverage Collector

Slides 2006-7 Doulos Ltd. All rights reserved.

The Coverage Collector

program vs. module

SystemVerilog module-level code:

Test Configuration and Control

Alternative test cases

URM Package methods

Slides 2006-7 Doulos Ltd. All rights reserved.

Testbench architecture consists of modules plus a program

Test program can pass randomized transactions to sequence driver

Test program is compact and easy to modify

DUT, BFM and sequence driver are independent