DSP Lab

Exercise Manual
for
Designing with DSP Builder Advanced

Blockset
Software and Hardware Requirements to Complete All Exercises

Software Requirements: Quartus II Development Tool, version 10.0;
Matlab, version 2009b; DSP Builder, version 10.0
Use the link below to download the design files for the exercises:
http://www.altera.com/customertraining/ILT/DSPBA_QII_v_10_0.zip
Exercises
Designing with DSP Builder Advanced Blockset
2
Copyright 2010 Altera Corporation
A-MNL-DSPBA-EX-10-0-v1
Exercises
Theoretical Background:
The objective of a communication system is to transport data between two or more points. At the
transmitter, the message bearing signal is usually superimposed on the carrier signal before the
actual transmission can occur. This is usually achieved by adjusting the characteristics (e.g.
amplitude, frequency, phase, or a combination of thereof) of the carrier wave. The process is
known as modulation. The signal is then transmitted over a noisy channel (to model after natural
interferences). Finally, at the receiver, the received signal is demodulated and the original
message bearing signal is recovered. The quality of the recovered message signal is affected by
the various factors (e.g. the amount of noise that exists in the channel).
Double-sideband (DSB) Modulation
The simplest modulation and demodulation scheme, which is also the topic of todays lab, is DSB
modulation and demodulation. In DSB modulation, the message signal is directly mixed together
with the carrier waveform; the resultant signal is transmitted directly without further modification.
More specifically, in DSB modulation, the transmitted signal, xc(t) is defined as follow:
xc (t ) = m(t ) cw (t ) = m(t ) Ac cos(2f c t + c )

where m(t) is the message signal and Ac, fc and c are the amplitude, frequency and phase of the
carrier sinusoid, cw(t). The band-limited message signalm(t), which we assume to have
amplitude of 1 and bandwidth of 2W, has the following frequency spectrum:
|M(f)|
-W
The carrier sinusoid (assuming c = 0) and the modulated signal, xc(t), have the following
frequency spectra:
|Cw(f)|
|Xc(f)|
-fc
fc
-fc
Frequency spectrum of carrier sinusoid
fc
Frequency spectrum of modulated signal
Noisy Channel
The modulator is usually the last component of the transmitter. The modulated signal, xc(t), is
then transmitted through some sort of channel, during which the signal is usually corrupted by
some sort of interferences. Typically, some sort of additive noise, n(t), is used to model this signal
degradation. More specifically, the received signal, xr(t), can be represented as:
xr (t ) = xc (t ) + n(t )
In order to keep the calculation simple, the noisy channel is often modeled as additive white
Gaussian noise. Additive Rayleigh fading noise is often used to model a more realistic channel
condition. Here, we limit our discussion to additive white Gaussian noise.
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Exercises
Coherent DSB Demodulation

We restrict our discussion to coherent demodulator, in which the phase of the carrier wave, c, is
known at the demodulator. (Note: the receiver can still be demodulated the signal without
knowing c. However, the demodulated signal strength would be weaker. This is typically referred
to as incoherent demodulation).
A typical coherent DSB demodulator works as follows:
Pre-detection
Band Pass
Filter
xr(t)
e2(t)
e3(t)
Post-detection
Low Pass
Filter
yD(t)
2 cos(2f c t + c )
The first part of the DSB demodulator is the pre-detection linear band pass filter. The filter is used
to filter out the unwanted noise, which was introduced by the noisy channel. Then the filtered
signal, e2(t), is mixed with the same carrier sinusoid (different amplitude is permitted). After the
mixer, which is nothing more than a multiplier, a post-detection liner low pass filter is used to
isolate the desired message signal. The frequency spectra of the two filters and the intermediate
signals along the way are shown below:
|HBPF (f)|
|E2(f)|
2W
2W
-fc
fc
2W
2W
-fc
fc
|E3 (f)|
|HLPF(f)|
f
-2fc
-W
2fc
f
-W
From the above frequency spectra, we notice that the DSB modulation and demodulation scheme
only works if the following is true (otherwise, the signals get corrupted by aliasing):
2 fc W W fc W
Note: Linear phase FIR filters are often used in DSB demodulator as the exact phase information
needs to be preserved throughout the demodulator.
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Exercises
Design Specifications:
You will build a two-channel DSB demodulator throughout the exercises today. The block
diagram of the DSB demodulator is shown below:
e2_f
x_r_f
HPF
Scaler
LPF1
pre_hfir
yd_f
yd
e3_f
Scaler
pre_lfir
Sync
e1
e1_f
e2
Scaler
Pre-detection BPF
LPF2
Scaler
pst_lfir
Sync and Mix
NCO
e3
Post-detection LPF
Figure 1: System diagram for the DSB demodulator

The major components of the DSB demodulator are described below:
- There are two test input signals are provided for the DSB demodulator:
1. A DSB modulated band-limited Gaussian random noise (with bandwidth of 0.1 f/fs)
2. A DSB modulated sound clip (sampling rate up converted to 96.0KHz from 11.025KHz)
- There is a numerically controlled oscillator (NCO) to generate the sinusoid waves (0.25 f/fs).
- Rather than implementing a BPF, the pre-detection BPF is the cascade of a HPF and a LPF:
1. HPF is a 31 tap FIR with cut off frequency of 0.33 f/fs and stop band attenuation of -50dB.
2. LPF1 is a 31 tap FIR with cut off frequency of 0.08 f/fs and stop band attenuation of -50dB.
- The sync and mix block is used to ensure the synchronicity of the outputs of the pre-detection
BPF and the NCO and to mix the two output signals.
- The post-detection LPF has the following parameters:
1. LPF2 is a 31 tap FIR with cut off frequency of 0.1 f/fs and stop band attenuation of -50dB.
- The scaler blocks are placed throughout to control the bit growth from input to output and to
compensate for various filter gains.
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Exercises
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Exercises
Exercise 1
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Exercises
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Exercises
Exercise 1- Algorithm Implementation using DSP Builder

Advanced Blockset
Objective:
The objective of this exercise is for you to gain experience implementing DSP algorithms
using DSP Builder Advanced Blockset. You will implement the DSB demodulator described in
the theoretical section of this exercise.
Design:
Use blocks from the DSP Builder Advanced blockset to implement the DSB demodulator. The
instructions are outlined in this section.
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Exercises
Step 1 Examine the Channel and Wire Structure of the DSB Demodulator
It is important to analyze the algorithm and understand how the channel and wire structure should
look before actual implementation can take place. Therefore, in this section, you will try to predict
the channel and wire structure throughout your DSB demodulator and verify the structure in your
MATLAB model.
1) Given the system clock rate, sample rate and channel count (see below), calculate the
channel and wire structure at all stages of the DSB demodulator:
System Clock Rate = Sample Rate
Channel Count
=2
Period (TDM Factor)
Channel Wire Count
Chan Cycle Count
2) Given the period, channel wire count and channel cycle count, please draw out the
wire/channel structure (add additional data wires if you need to):
clk
valid
channel
data
wire
The following sub-steps will help determine the validity of your wire/channel structure.
3) Open MATLAB, if it is not already opened. In the Current Directory window, set the path to
<exercise_install_directory>\Ex1\.
4) Open up lab_testbench.m. Take a moment to observe the MATLAB test bench. In this test
bench, MATLAB functions have been wrapped inside the interface that DSP Builder
Advanced Blockset expects. Ask your instructor if you need help understanding the test
bench.
5) Comment out lines 141 154 (if they have not been commented out already).
6) Make sure the MATLAB equivalent code is not commented out (lines 101 133).
7) Disable the sw_clip (line 5) and enable us_manual (line 9) flags and run the test bench.
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Exercises
8) Type the following commands in the MATLAB command prompt to plot the generated
channel, and valid signals:
>>
>>
>>
>>
>>
figure;
subplot(211)
plot(xr_c.signals.values);title('channel');
subplot(212)
plot(xr_v.signals.values);title('valid');
You should see the following figure:
This figure should match the channel/valid signals that you predicted in sub-step 2.
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Exercises
Step 2 Implementing the DSB Demodulator

Now that you have successfully predicted the channel/wire structure that DSP Builder Advanced
Blockset requires, you are ready to build the hardware in Simulink using Altera s DSP Builder
Advanced Blockset. In the interest of time, the majority of the blocks have been connected for
you. The instructions to completing the design are outlined below.
1) Click on the Simulink button
to open the Simulink Library Browser.
2) From the Simulink Library Browser, click on the

button (or alternatively File menu ->
Open) to open the partially completed lab_dsbdm.mdl file.
3) In the Library Browser, click on
to expand Altera DSP Builder Advanced Blockset.
4) From the Base Block library in the Altera DSP Builder Advanced Blockset, add Control,
Signals and Run Quartus II blocks to lab_dsbdm.mdl. (To add a block to the Simulink
model, simply drag and drop the block from the Simulink library browser to the model).
5) Double click on the Control block and configure it as follows:
Control
Hardware Destination Directory:
./rtl
Note: During the lab, only change the field specified by the lab instructions.
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Exercises
6) Double click on Signals block and configure it as follows:

Signals
Clock:
Clock Frequency (MHz):
clk
ClockRate
7) From the Sources library in the Simulink blockset, click and drag one From Workspace
block into lab_dsbdm.mdl. Duplicate the From Workspace block two more time to create
From Workspace1 and From Workspace2 blocks. Configure the three blocks as follows:
From Workspace:
Data:
Sample time:
xr_d
SampleTime
From Workspace1:
Data:
Sample time:
xr_v
SampleTime
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Exercises
From Workspace2:
Data:
Sample time:
xr_c
SampleTime
8) From the Sink library in the Simulink blockset, click and drag one To Workspace block into
lab_dsbdm.mdl. Duplicate the To Workspace block two more time to create To
Workspace1 and To Workspace2 blocks. Configure the three blocks as follows:
To Workspace:
Data:
fy_d
To Workspace1:
Data:
fy_v
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Exercises
To Workspace2:
Data:
9)
fy_c
From the Signal Attributes library in the Simulink blockset, click and drag one Data Type
Conversion block into lab_dsbdm.mdl. Duplicate the Data Type Conversion block two
more time to create Data Type Conversion1 and Data Type Conversion2 blocks. Configure
the three blocks as follows:
Data Type Conversion:
Output data type:
boolean
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Exercises
Data Type Conversion1:

Output data type:
uint8
Data Type Conversion2:

Output data type:
Note: To get fixdt(1,16,11), click on the
type drop down field. Then select/enter
Mode:
Sign:
Scaling:
Word length:
Fractional length:
fixdt(1,16,11)
button, right next to the output data
following for Data Type Assistant:
Fixed point
Signed
Binary point
16
11
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Exercises
10) Connect the blocks in lab_dsbdm.mdl together in the following fashion:

- From Workspace -> Data Type Conversion2 -> i_d port of DSB_Demod_chip
- From Workspace1 -> Data Type Conversion -> i_v port of DSB_Demod_chip
- From Workspace2 -> Data type Conversion1 -> i_o port of DSB_Demod_chip
- o_d port is connected to To Workspace block
- o_v port is connected to To Workspace1 block
- o_c port is connected to To Workspace2 block
Your lab_dsbdm.mdl should look like the following:
You are now ready to implementing the DSB_Demod_Chip subsystem:

11) Double-click on the DSB_Demod_Chip subsystem block to open up the subsystem.
12) From the Base Block library in the Altera DSP Builder Advanced Blockset, add Device
block to DSB_Demod_Chip subsystem. Double click on the Device block and configure it as
follows:
Device
Device Family:
Family Member:
Speed Grade:
Stratix II Device
Auto
-3
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Exercises
Your DSB_Demod_Chip subsystem should look like the following:
The Device block marks the DSB_Demod_Chip subsystem as the top level of the FPGA
design. All blocks in the subsystem below this level of hierarchy, become part of the RTL
design. All blocks above this level of hierarchy become part of test bench.
Now that you are done with the DSB_Demod_Chip subsystem, you are ready to start
building the DSB demodulator.
As shown in the system diagram (Figure 1 exercise 1), the DSB demodulator can be
separated into the following component:
-
Pre-detection BPF, which is built using the cascade of a high-pass and a low-pass
FIR filters.
NCO, which is used to generate the carrier sinusoids that we need to demodulate our
signals
A synchronizer, which is used to ensure data from the pre-detection BPF and the
NCO do indeed line up.
A multiplier that is used as a mixer
A post-detection LPF, which is used to isolate the demodulated signal
Scalers are placed throughout the demodulator to limit the bit-growths and thus,
making hardware implementation of the demodulator feasible
All the components, other than the customized synchronizer-and-mix block, NCO and postdetection LPF are created using ready-made ModelIP cores from DSP Bulder Advanced
Blockset and have been connected for you already. You will have instantiate the NCO and
post-detection LPF cores manually and build the customized synchronizer-and-mix block
using ModelPrim blocks from DSP Builder Advanced Blockset. Detail instructions to
completing the demodulator are listed below:
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Exercises
13) Double-click on the DSB_Demod subsystem block to open up the subsystem. You should
see the following:
14) Replace the Post Detection LPF Placeholder with one instance of SingleRateFIR block from
the Filters library in the Altera DSP Builder Advanced Blockset. Name and configure the
instance of SingleRateFIR block as follows:
PostDetectionLPF
Parameter GUI (simply double-click on the block):
Input Rate per Channel:
SampleRate
Number of Channels:
ChanCount
Coefficients:
fi(pst_lfir,1,w_fir,f_fir)
Base Address:
PST_LFIR_COEFS
Block Annotation tab in Block Properties GUI (right click -> block properties):
Enter text and token:
Added Latency: %<latency>
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Exercises
15) Replace the NCO Placeholder with one instance of NCO block from the Waveform
Synthesis library in the Altera DSP Builder Advanced Blockset. Name and configure the
instance of NCO block as follows:
NCO
Parameter GUI (simply double-click on the block):
Output Rate Per Channel:
Output Data Type:
Output scaling value:
Accumulator Bit Width:
Phase Increment and Inversion:
Phase Increment and Inversion Memory Map:
SampleRate
sfix(w_nco)
2^-f_nco
24
f_fs*2^24
NCO_PHASE_INCR
Block Annotation tab in Block Properties GUI (right click -> block properties):
Enter text and token:
Added Latency: %<latency>
Before the output of the pre-detection BPF can be mixed together with the carrier sinusoid
waves, you must make sure the two signals are aligned. (The Scale and NCO blocks have
different latencies, as noted by the annotation on the bottom). The most straight-forward way
to accomplish this is by simply delaying the Scale signals.
The aforementioned approach, although simple, is not the optimal approach; the delays
would be different with a different set of configurations (e.g. scaling factors). Rather than
delaying the signal, you will design a synchronizer that would work with different
configurations (e.g. different number of channels). Detailed instructions to completing the
customized synchronizer-and-mix block are listed below:
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Exercises
16) Double-click on the Sync_Mix subsystem block to open up the subsystem.

17) From the ModelPrim library in the Altera DSP Builder Advanced Blockset, add an
instance of SynthesisInfo block to Sync_Mix subsystem. Configure the SynthesisInfo block
as follows:
SynthesisInfo
Synthesis Style:
Scheduled
instance of ChannelIn block to Sync_Mix subsystem. Configure the ChannelIn block as
follows:
ChannelIn
Number of data signals:
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Exercises
instance of ChannelOut block to Sync_Mix subsystem. Configure the ChannelOut block as
follows:
ChannelOut
Number of data signals:
20) From the ModelPrim library in the Altera DSP Builder Advanced Blockset, add one
instance of Mult block to Sync_Mix subsystem, named Mult.
21) From the ModelPrim library in the Altera DSP Builder Advanced Blockset, add one
instance of DualMem block to Sync_Mix subsystem and configures as follows:
DualMem
Output data type mode:
Initial contents:
Use DONT CARE:
Inherit via internal rule

[zeros(16,1)]
checked
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Exercises
22) From the Sink library in the Simulink Blockset, add one instance of Terminator block to
Sync_Mix subsystem.
23) Connect the blocks in Sync_Mux subsystem together in the following fashion:
-
dV input port -> dv input port of ChannelIn block

dC input port -> dc input port of ChannelIn block
dIn input port -> d0 input port of ChannelIn block
cos input port -> d1 input port of ChannelIn block
ncoV input port -> d2 input port of ChannelIn block
ncoC input port -> d3 input port of ChannelIn block
qV output port of ChannelOut block -> OutV port
qC output port of ChannelOut block -> OutC port
q0 output port of ChannelOut block -> OutI port
qV output port of ChannelIn block -> dV input port of ChannelOut block

qC output port of ChannelIn block -> dC input port of ChannelOut block and a input
(the bottom one) port of DualMem block
q0 output port of ChannelIn block -> one of input ports of the Mult block
q1 output port of ChannelIn block -> d input port of the DualMem block
q2 output port of ChannelIn block -> w input port of the DualMem block
q3 output port of ChannelIn block -> a input (the top one) port of DualMem block
q1 output port of DualMem block -> the Terminator block

q2 output ports of DualMem block -> the other input port of Mult block
output port of Mult block -> d0 input port of ChannelOut block
Your DSB_Demod subsystem should look like the following (minus the annotation):
Note that this subsystem dynamically matches the NCO data stream with the data stream of the
pre-detection filter. The goal is to align the channel signals. This is achieved by storing NCO data
to a memory, and using the FIRs channel to read that data.
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Exercises
Step 3 Verifying the DSB Demodulator Implementation

Now that you have successfully built your DSB demodulator using the DSP Builder Advanced
Blockset, it is time to verify the implementation. The instructions to do so are outlined below.
1) Make sure the simulation time is set to EndTime.
2) Save and close the model, lab_dsbdm.mdl.
3) Comment out lines 101 133 of the lab_testbench.m (highlight the lines and press Ctrl +
R). Uncomment lines 141 - 154 (highlight the lines and press Ctrl + T).
4) Enable us_manual flag.
5) Save the MATLAB testbench.
6) Run lab_testbench.m. When the us_manual flag is enabled, the testbench will load the test
input data and automatically open up your Simulink model, lab_dsbm.mdl.
7) When the model opens, enable Port Data Types and Signal Dimensions (Format->Port->
Port/Signal Displays).
8) Press the Start Simulation button,
, to run the model. Look through the model and see
whether the signal types and dimensions agree with your theoretical Channel Wire Count.
9) Type the following in the MATLAB command prompt:
>> f_data = adspb_dechannelizer(fy_d, fy_c, fy_v);
This command will convert the output of the DSB demodulator from three separate MATLAB
structures into one MATLAB 2-D array.
10) Next type the following in the MATLAB command prompt:
>> plotSpectrum(f_data(1,:),1024,'|Y_D(f)|');
You should see the following frequency spectrum:
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Exercises
11) Close the lab_dsbm.mdl model. In the MATLAB testbench, lab_testbench.m, disable the
us_manual flag and enable the sw_clip flag. Re-run the MATLAB testbench.
With the us_manual flag on, the testbench will automatically open the lab_dsbm.mdl model and
simulate the model. Once the simulation is done, the model is closed automatically.
12) Next type the following in the MATLAB command prompt:
>> wavplay(f_data',fs);
What do you hear?
Summary Exercise 1
From this exercise, you have practiced:
-
Calculating theoretical the wire/channel structure of your DSP algorithm
Build your DSP algorithm using DSP Builder Advanced Blockset
25
Exercises
26
Exercises
Exercise 2
2A Device Selection and Performance Verification
(Optional) 2B Design Exploration Hardware Multiplier
Trade-Offs
27
Exercises
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Exercises
Exercise 2A Device Selection and Performance Verification

Objective:
The objective of this exercise is for you to gain experience selecting the proper device based
on your performance criteria and verifying your hardware performance in Quartus II

development tool. You will select the proper device based on hardware resource estimation
of your DSB demodulator. You will then verify the hardware resource utilization and timing
performance of your DSB demodulator using the compilation reports.
1) Copied the following files from <exercise_install_directory>\Ex1\ to
<exercise_install_directory>\Ex2\MATLAB_Files:
- lab_dsbdm.mdl
- lab_testbench.m
- adspb_channelizer.m
- adspb_dechannelizer.m
- in_data.mat
2) Open MATLAB, if not already open. In the Current Directory window, set the path to
<exercise_install_directory>\Ex2\MATLAB_File.
3) Open the MATLAB testbench and make the following changes to it:
a. Make sure that lines 101 133 are commented out and lines 145-149 uncommented.
b. Disable sw_clip flag.
c. Enable us_manual flag.
d. Change SampleRate from 1 to 200 (line 27).
4) Save the MATLAB testbench.
5) Run lab_testbench.m. With the us_manual flag enabled, the testbench will load the test
input data and automatically open up the Simulink model, lab_dsbm.mdl.
6) Once the lab_dsbm.mdl is brought up, make the following changes to your Simulink model:
a. Double click on the Control block. Once the Block Parameter GUI is opened,
change the following:
i. Hardware Destination Directory from rtl to ../HardwareFiles.
b. Click into the DSB_Demod_Chip subsystem. Double click on the Device block.
Once the Block Parameter GUI is opened, change the following:
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Exercises
i. the Device Family from Stratix II device to Cyclone III device

ii. the Speed Grade to -7.
Note: Given that Cyclone III device was chosen for your DSB demodulator project and
that the system clock has a 200MHz requirement. You can determine what speed grade
you should choose (even before you settle on a specific Cyclone III device). From the
Cyclone III embedded multiplier specification (shown below), you can determine that a
speed grade of 7 is needed to meet the 200MHz system clock requirement.
7) Save and simulate lab_dsbm.mdl.

8) Once the simulation is done, double click on the Run-Quartus II block,
. This will create
a Quartus II project in the design directory that contains the .mdl model. The generated
Quartus II project file (.qpf) and related files (settings file, .qsf, and ip file, .qip) are named
<Simulink model name>_< subsystem name> (the subsystem is referring to the one that
contains the Device block). In this case, the generated Quartus II project and associated files
are named lab_dsbm_DSB_Demod_Chip.
Now that you have settled on a device and a speed grade, you will need to settle on a
specific device. The following steps outline the procedures to do so.
9) Inside Quartus II development tool, make sure the Compilation flow is chosen for the Tasks
pane.
10) Double click on the Analysis & Synthesis task to perform the analysis and synthesis portion
of the compilation. This step would yield an approximate logic usage count for the DSB
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Exercises
demodulator. Notice the progress bar right next to the Analysis & Synthesis task. Upon
completion, the task will turn green and a green check mark will appear right next to it.
, to bring up the compilation report tab.
11) Click on the Compilation Report button,
12) Expand the Analysis & Synthesis folder and click on Summary. This will show you the
approximate resource count.
13) Copy down the Analysis & Synthesis Summary results.

Total logic element:
Total combinational function:
Dedicated logic registers:
Total registers:
Total pins:
Total memory bits:
Embedded Multiplier 9-bit elements*:
Note: Alternatively, you can also determine the estimated resource usage directly from your
Simulink model. Once a model has been simulated (and the optimized HDL has been generated),
you can right click on any ModelIP block and select Help to see the required resources for the
block. Also, you will be able to see the parameters, input and output data format and any
applicable memory interface for the specific block.
However, you will not be able to see the total pins of your design from your Simulink model. This
should not be a problem you are not using your Simulink design as the top level entity.
14) From the estimated logic elements and multipliers (keep in mind that 1 18x18 multiplier ~ 2
embedded multiplier 9-bit elements) usage requirement and from the Cyclone III FPGA
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Exercises
overview table (shown below), estimate what Cyclone III device would fit the resource
requirement of the DSB demodulator:
15) From the estimated total pin requirement and from the Cyclone III device package and
maximum user I/O data sheet (table shown below), you can determine the specific device
you should choose for your design. For this lab, we will use the Cyclone III EP3C40F324C7
device.
16) Close Quartus II. Now go back to the Simulink model, lab_dsbm.mdl, and enter
EP3C40F324C7 as our targeted device.
17) Save and re-simulate lab_dsbm.mdl. This will regenerate optimized HDL codes, targeting
our specific Cyclone III device.
18) Once the simulation is done, double-click on the Run Quartus II icon to bring up the Quartus
II project.
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Exercises
19) In Quartus II development tool, double click the Fitter (Place & Route) task under the Tasks
pane; the compiler will automatically run the analysis & synthesis and the place & route
portions of the compilation process.
20) Once the Fitter task is done, expand the Fitter folder and highlight Summary. Compare the
Fitter Summary report to the Analysis & Synthesis Summary report, which you copied
down earlier. Notice while the two correlate, they do not match. This is expected as the
resource summary from Analysis & Synthesis is merely an estimate.
21) Expand the Resource Section Folder (under the Fitter folder) and click on Resource
Utilization by Entity. As the report name indicates, you will be able to see the resource
utilization by all the entities in your design.
22) Notice how all the nodes are expanded in the compilation hierarchy node section. For our
benefit, collapse everything below the third node hierarchy.
23) From the Fitter Resource Utilization by Entity report, complete the following table:
Entity
Memory
Bits
M9K
DSP
18x18
Pins
LUTonly
LCs
RegisterOnly
LCs
LUT/
Register
LCs
NCO
PreDetectionHPF
PreDetectionLPF
PostDetectionLPF
Sync_Mix
Note: When applicable, copy the numbers outside the parentheses only; they indicate the total
number of resources of the given type used by the specific entity and all its sub-entities.
24) In Quartus II development tool, double click the TimeQuest Timing Analysis task under the
Tasks pane; the compiler will automatically perform static timing analysis on the design.
25) Expand the Slow 1200mV 85C Model folder and the Slow 1200 mV 0C Model folder (both
under the TimeQuest Timing Analyzer folder) and click on Fmax Summary for both.
Record the slower one in the table in step 27.
26) Collapse the Slow 1200mV 85C Model and the Slow 1200mV 0C Model folders. Click on
Multicorner Timing Analysis Summary. Complete the following table.
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Exercises
Fmax (MHz)
Worst-case setup slack (ns)
Worst-case hold slack (ns)
27) Close the Quartus II development tool window.
Summary
-
Selecting the proper device based on the estimated hardware usage
Verifying the hardware resource and timing performance using compilation results
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Exercises
Exercise 2B Design Explorations - Multiplier Trade-Offs

Objective:
The objective of this exercise is for you to gain experience changing your design by exploring
hardware multiplier trade-offs.
1) Open the DSB demodulator Simulink model, lab_dsbm.mdl, if it is not opened already.
2) Double-click on the Control block and change the Hard Multiplier Threshold to 300.
Note: With the Hard Multiplier Threshold, the designer has control over how the multipliers
should be implemented. By default (when threshold is set to -1), 18x18 multipliers are always
used. For example, a 24x18 multiplier would be implemented as the sum of two 18x18
multipliers.
Alternatively, the designer can use the threshold, which is the number of logic elements the
designer is willing to use to save a multiplier. For example, the value of 300 would enable
multiplications (smaller than 18x18) to be implemented in soft logic instead of dedicated
18x18 multipliers.
3) Save and simulate the DSB demodulator Simulink model, lab_dsbm.mdl.
4) Once the simulation is completed, bring up the Quartus II project and run up to the fitter stage
of the compilation.
5) Use the information from the Fitter Resource Utilization by Entity report to complete the
following table:
Entity
Memory
Bits
M9K
DSP
18x18
Pins
LUTonly
LCs
RegisterOnly
LCs
LUT/
Register
LCs
NCO
PreDetectionHPF
PreDetectionLPF
PostDetectionLPF
Sync_Mix
Note: Compare the resource utilization results to the ones obtained in exercise 3A. You
should notice that besides the three filters, everything else (with 16 bits resolutions) was built
out of logic cells. Hardware Multiplier Threshold can be used to limit the number of
hardware multipliers and thereby, saving multiplier resources.
Keep in mind that in hardware design, there is always a trade-off that you need to consider.
In this case, hardware multipliers can run at higher speed than soft logic cell based
multipliers. Hence, you should also check whether your design is still meeting timing or not.
6) Use the information from the TimeQuest Timing Analyzer section of the compilation report
to complete the following table:
Fmax (MHz)
Worst-case setup slack (ns)
Worst-case hold slack (ns)
35
Exercises
Note: Here you should see that you are no longer meeting the 200MHz Fmax requirement
and that you have a negative worst-case setup slack. Typically, you have several choices
here. You can:
-
use a faster device, possibly a different speed grade

explore different Hardware Multiplier Threshold
explore the paths that are failing timing and re-architect the design accordingly
Rather than debugging timing closure and re-architecting our DSB demodulator, we will
simply revert back the Hardware Multiplier Threshold to the default value of -1.
From the Control block, you can also influence how the memories are implemented in your
design, (similar to how you can influence your multiplier implementation).
7) Close Quartus II development tool window.
8) Inside the Simulink DSB demodulator model, lab_dsbm.mdl, change the Hardware
Multiplier Threshold back to default setting, -1.
9) Save and simulate the model. Upon completion of the simulation, close the model.
Summary Exercises 2A, 2B

-
Selecting the appropriate device based on estimated resource requirement
Verifying the hardware resource utilizations and timing performance using

compilation reports from Quartus II
Exploring the hardware multiplier trade-offs
36

DSP Lab

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Exercise Manual

Designing with DSP Builder Advanced

Software and Hardware Requirements to Complete All Exercises

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

xc (t ) = m(t ) cw (t ) = m(t ) Ac cos(2f c t + c )

Frequency spectrum of carrier sinusoid

Frequency spectrum of modulated signal

Designing with DSP Builder Advanced Blockset

Coherent DSB Demodulation

Designing with DSP Builder Advanced Blockset

Sync and Mix

Figure 1: System diagram for the DSB demodulator

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Exercise 1- Algorithm Implementation using DSP Builder

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

You should see the following figure:

Designing with DSP Builder Advanced Blockset

Step 2 Implementing the DSB Demodulator

to open the Simulink Library Browser.

2) From the Simulink Library Browser, click on the

to expand Altera DSP Builder Advanced Blockset.

Designing with DSP Builder Advanced Blockset

6) Double click on Signals block and configure it as follows:

Designing with DSP Builder Advanced Blockset

Copyright 2010 Altera Corporation

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Data Type Conversion1:

Data Type Conversion2:

Designing with DSP Builder Advanced Blockset

10) Connect the blocks in lab_dsbdm.mdl together in the following fashion:

You are now ready to implementing the DSB_Demod_Chip subsystem:

Designing with DSP Builder Advanced Blockset

Your DSB_Demod_Chip subsystem should look like the following:

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

16) Double-click on the Sync_Mix subsystem block to open up the subsystem.

Designing with DSP Builder Advanced Blockset

Inherit via internal rule

Designing with DSP Builder Advanced Blockset

dV input port -> dv input port of ChannelIn block

qV output port of ChannelIn block -> dV input port of ChannelOut block

q1 output port of DualMem block -> the Terminator block

output port of Mult block -> d0 input port of ChannelOut block

Designing with DSP Builder Advanced Blockset

Step 3 Verifying the DSB Demodulator Implementation

Designing with DSP Builder Advanced Blockset

Calculating theoretical the wire/channel structure of your DSP algorithm

Build your DSP algorithm using DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Designing with DSP Builder Advanced Blockset

Exercise 2A Device Selection and Performance Verification

on your performance criteria and verifying your hardware performance in Quartus II

Designing with DSP Builder Advanced Blockset

i. the Device Family from Stratix II device to Cyclone III device

7) Save and simulate lab_dsbm.mdl.