Advanced Computer Architecture

Digital Building Blocks-II

Sequential Building Block

Counters

Increments on each clock edge.

Used to cycle through numbers. For example,
000, 001, 010, 011, 100, 101, 110, 111, 000, 001
Example uses:
Digital clock displays
Program counter: keeps track of current instruction executing

S ym b o l

Im p lem en tatio n

C LK

C LK

Q
R eset

N
r

R eset

Excitation Table
Excitation table lists required inputs of flip-flops that will cause
necessary transition from present state to next state.

Present
State
Q(t)
0
0
1
1

Next
State
Q(t+1)
0
1
0
1

flip-flop

Input

JK

SR

J K

S R

0
1
X
X

0
1
0
X

X
X
1
0

X
0
1
0

0
1
0
1

T
0
1
1
0

Analysis of Combinational vs Sequential

Circuits
Combinational

Sequential

Boolean Equations
Truth Table

State Equations
State Table
State Diagram

Output as a function of
inputs

Output as a function of
input and current state
Next state as a function
of inputs and current
state.

State Equations

An algebraic expression assigning the next state of the flip-flop in

terms of the present state and input conditions of the machine is
referred to as a state equation. This equation is a Boolean
expression that specifies the present state and input conditions.

Fig shows a sequential circuit that has one full adder, one D flip-flip,
two inputs x, y and output S. This circuit is an implementation of
serial adder.
X

Full Adder

Y
C
Z
Q

D F/F
D

Next state equation: Q(t+1)=D(t)=C(t)

Sum (S) : S(t) = X(t) Y(t) Q(t)
Carry (C) output C(t)= X(t)Y(t) + X(t) Q(t) + Y(t)Q(t)

Clock Pulse

State Table
Time sequence of inputs, outputs, and internal states of
flip-flop can be described in a table called state table

Present
Z
0
1
0
1
0
1
0
1

Input
XY
00
00
01
01
10
10
11
11

Next State
Z
0
0
0
1
0
1
1
1

Output
S
0
1
1
0
1
0
0
1

Full Adder

Y
C
Z
Q

D F/F
D
Clock Pulse

State Table
Entries in the next state sections define the necessary
state transition of the circuit and also specify the next
value of the output Q(t+1) of the flip-flop. This table is
also called transition table

Present State
Z
0
1

Next state, Z
Output S
XY = 00 01 10 11 XY = 00
0
0

0
1

0 1
1 1

0
1

01

10

1
0

1
0

11
0
1

State Diagram

Inputs, outputs and flip-flop states can be represented

graphically in a directed graph. This graph is known as
state diagram or state graph.
A state is represented by a circle (also called as vertices)
State transition is indicated by directed lines or arcs
connecting the vertices.
Present State
Z

Next state, Z
Output S
XY = 00 01 10 11 XY = 00

0
1
00/0
01/1
10/1

0
0

0
1

0
1

1
1

11/0

1
00/1

01/0
10/0
11/1

0
1

01

10

11

1
0

1
0

0
1

STATE REDUCTION

State-reduction technique reduces number of states in a state

table while keeping the external input-output requirements
unchanged

m flip-flops produce 2m states and a reduction in the number of

states may or may not result in a reduction in number of flipflops

State reduction is the process to develop compact state

diagrams and avoid the introduction of redundant states

If two states x and y are equivalent, then state y is called as

redundant. Two states x and y of a finite state machine are
defined to be equivalent when the machine is started in these
states and the identical output sequences are generated from
every possible set of input sequences that can be applied

STATE REDUCTION
0/1
1/0

0/0
1/1

d
1/0 0/0

0/0

1/1

1/0
0/1

0/0

0/0

1/0
1/0
f
State Diagram

STATE REDUCTION

Present
State
a
b
c
d
e
f
g

State Table
Next State
X=0 X=1
b
c
d
e
g
f
a
a
a
a
a
a
a
a

Output
X=0 X=1
0
0
0
0
0
0
0
1
1
0
0
1
1
0

STATE REDUCTION
State table shows removal and replacement of the states
Present
State
a
b
c
d
e
f
g

Next State
X=0 X=1
b
c
d
e
g e f d
a
a
a
a
a
a
a
a

Output
X=0 X=1
0
0
0
0
0
0
0
1
1
0
0
1X
1
0X

STATE REDUCTION
Reduced State table
Present
State
a
b
c
d
e

Next State
X=0 X=1
b
c
d
e
e
d
a
a
a
a

Output
X=0 X=1
0
0
0
0
0
0
0
1
1
0

STATE REDUCTION
e
0/0
1/0
b

0/1
1/0
0/0

1/0

a
0/0

0/0
1/1
d

1/0

STATE REDUCTION

State

Assignment-I
Assignment-II
Assignment-III

000
001
000

001
011
010

010
101
100

011
100
110

100
111
111

STATE REDUCTION
Reduced State Table with Binary Assignment
Present
State
000
001
010
011
100

Next State
X=0 X=1
001 010
011 100
100 011
000 000
000 000

Output
X=0 X=1
0
0
0
0
0
0
0
1
1
0

DESIGN METHOD

Synchronous
sequential
combinational gates

circuit:-

flip-flops

and

Design of circuit includes selection of flip-flops and

finding of combinational gate structure

Number of states needed in the circuit determines the

number of flip-flops and combinational circuit is derived
from state table

After selection of type and number of flip-flops, the

techniques of combinational-circuit design can be applied to
design combinational circuit. A combinational circuit is
fully specified by a truth table, a sequential circuit requires
a state table for its specification

DESIGN METHOD
A sequential circuit has been described in state diagram. The
design uses D flip-flop. Circuit has four states. Binary values
have already been assigned to the states. From the state diagram,
it is seen that the circuit has one input variable and no output
variables because the directed lines are marked with a single digit
without a slash. Two D flip-flops (A and B) are needed to
represent four states. Input variable is designated x.

00

0
10

1
01
11

DESIGN METHOD
0

00

0
10

1
01
11

Present state
AB
00
01
10
11

Next State
X=0 X=1
AB AB
00
01
01
11
10
00
11
10

DESIGN METHOD

Table: Excitation of D flip-flop

D input
Present
State Input
AB X
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

State Transition
00 01 10 11
0
1
0 1

Next State
A B
0 0
0 1
0 1
1 1
1 0
0 0
1 1
1 0

F/F Inputs
DA DB
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
0

DESIGN METHOD
A

Bx Bx

Bx

Bx

DA=Ax + Bx

Bx Bx

Bx

Bx

DB=Ax + Bx

DESIGN METHOD
DA=Ax + Bx

DB=Ax + Bx

Combinational

DA

DB

DESIGN METHOD
Table: Excitation of JK flip-flop

J
K

State Transition
00
01
10
0
1
x
x
x
1

11
x
0

Excitation table of the sequential circuit

Present
State Input
AB X
00
0
00
1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

F/F Inputs
Next State A F/F B F/F
A B JA KA JB KB
0 0
0 x
0 x
0 1
0 x
1 x
0 1
0 x
x 0
1 1
1 x
x 0
1 0
x 0
0 x
0 0
x 1
0 x
1 1
x 0
x 0
1 0
x 0
x 1

DESIGN METHOD
A

Bx Bx Bx Bx

Bx Bx Bx Bx

JA=Bx
A

KA=Bx

Bx Bx Bx Bx A
0

JB=Ax

Bx Bx Bx Bx
x

KB=Ax

DESIGN METHOD
JA=Bx
JB=Ax

KA=Bx
KB=Ax
Combinational

JA

KA

A
A

JB
KB

Q
Q

B
B

DESIGN METHOD
Table: Excitation of T flip-flop

F/F Input
T
Present
State Input
AB X
00
0
00
1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

State Transition
00 01 10 11
0
1
1
0
Next State
A B
0 0
0 1
0 1
1 1
1 0
0 0
1 1
1 0

F/F Inputs
TA TB
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1

DESIGN METHOD

Bx Bx Bx Bx
0

TA= ABx + ABx

=(AB) x

Bx Bx Bx Bx
0

0
1

TB= A Bx+ABx
=(AB) x

DESIGN METHOD
Combinational
X

TA

TB

Q
Q

TA= ABx + ABx

=(AB) x

Clock

B
B

TB= A Bx+ABx
=(AB) x

DESIGN METHOD
Table: Excitation of SR flip-flop

J
K
Present
State Input
AB X
00
0
00
1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

State Transition
00 01 10 11
0
1
0
x
x
0
1
0
F/F Inputs
Next State A F/F B F/F
A B
SA RA SB RB
0 0
0 x
0 x
0 1
0 x
1 0
0 1
0 x
x 0
1 1
1 0
x 0
1 0
x 0
0 x
0 0
0 1
0 x
1 1
x 0
x 0
1 0
x 0
0 1

DESIGN METHOD
A

Bx

Bx Bx Bx

Bx

Bx

Bx Bx

X
SA=Bx
A

Bx Bx

RA=Bx
Bx Bx

Bx

Bx

Bx Bx

SB=Ax

RB=Ax

DESIGN METHOD
Combinational
A
X

SA

RA

SB

RB

SA=Bx
SB=Ax

Clock

RA=Bx
RB=Ax

Digital Counter Design

Digital Counter

used to record number of occurrences of input or to generate

the timing sequences to control operations in the digital
computers

Flip-flops are the main components for building a counter

Two categories; ripple or synchronous counter.

synchronous circuits are clocked i.e. work only on the arrival of

a signal pulse
ripple or asynchronous circuits are not clocked and do not need
a clock pulse to work i.e. the flip-flop output transition serves
as a source for triggering other flip-flop.

Digital Counter

Counters in which the output of one F/F drives another are

called ripple counter or asynchronous counter

Ripple counters are constructed by using T F/Fs or JK flip-flop

with J & K leads shorted

F/Fs are cascaded in series.

They are triggered asynchronously

Output of one F/F drives the input of the next F/F. As the
triggering pulse moves from one F/F to another F/F like a
ripple in water, these counters are called ripple counters.

Digital Counter

Counters are identified by their modulus abbreviated as MOD

Modulus of a counter is expressed by total number of counts

that can be made by that counter or total number of states
through which counter goes before resetting
A binary counter having n flip-flops has 2n total counts or states
and it has 2n modulus. It is termed as mod- 2n counter.
A mod-2 counter counts two states and uses one flip-flop, a
mod-4 counter uses two flip-flops and counts 4 pulses, a mod-8
counter uses 3 flip-flops and counts 8 states or pulses.
Counter, which counts states greater than 2n but less than 2n+1
requires n+1 number of flip-flop. For example, mod 5 counter
that counts 5 states from 0 to 4 uses (22 <count<23) uses 3 flipflops. Other three states are considered as unused states.

Digital Counter

Ripple counters are not state machines, although they use

sequential logic.

Synchronous counters are state machines. Synchronous

counters of any type can be designed using the state machine
design method.

Asynchronous counters suffer from the lower speed of

operation

Digital Counter
Ripple Counter

Ripple counter consists of cascaded JK F/Fs with JK lead

wired high

Output of each F/F is connected to CLK input of next F/F.

F/F generating least significant bit of count receives input

clock from clock generator

Mod-4 Ripple Counter

Mod-4 that counts through 4 different states. All J and K inputs
are connected to 1.
Bubbles in clock input of each F/F indicates that F/Fs changes
its state on a negative-going transition i.e. when a transition
from 1 in present to 0 in next state of a F/F occurs, the state of
next F/F will change.
Sequence of mod-4 ripple counter is 0->1->2->3->0

Mod-4 Ripple Counter

Mod-4 that counts through 4 different states. All J and K inputs
are connected to 1.
Bubbles in clock input of each F/F indicates that F/Fs changes
its state on a negative-going transition i.e. when a transition
from 1 in present to 0 in next state of a F/F occurs, the state of
next F/F will change.
Sequence of mod-4 ripple counter is 0->1->2->3->0

DESIGN METHOD
Table: Excitation of D flip-flop

State Transition
00 01 10 11
0
1
0 1

D input

Table: Excitation of JK flip-flop

State Transition
00
01
10
0
1
x
x
x
1

J
K

11
x
0

Table: Excitation of T flip-flop

F/F Input
T

State Transition
00 01 10 11
0
1
1
0

MOD-4 ripple counter

Sequence Table

Input Clock Pulse

1
J

K
A

Input clock

QB

QA

Timing Diagram of MOD-4 ripple counter

Count
Sequence
A B
0 0
0 1
1 0
1 1

Decimal

0
1
2
3

MOD-8 ripple counter

Input Clock Pulse
1
J

C
Q

B
Q

Input clock

QC

1 0

0 1

QB

0 1

0 0

QA

0 0

1 1

Count
Decimal
Sequence
A B C
0 0 0
0
0 0 1
1
0 1 0
2
0 1 1
3
1 0 0
4
1 0 1
5
1 1 0
6
1 1 1
7

MOD-16 ripple counter

Input Clock Pulse
1
J

D
Q

C
Q

J
A

B
Q

Input clock

QC

1 0

0 1

QB

0 1

0 0

QA

0 0

1 1

MOD-3 ripple counter

B
A B Reset
0 0
0
0 1
0
1 0
0
1 1
1

State Diagram

A
A

K-Map
Count
Sequence
A B
0 0
0 1
1 0
1 1

K
A

Input Clock
QB
0
QA
0

Reset=AB

Truth Table

1
0

0
1

Decimal

0
1
2
3

0
0

1
0

0
1

0
0

Reset
f) Timing

MOD-5 ripple counter

ABC
0

000
001
010
011
100
101
110
111

State Diagram

Reset
0
0
0
0
0
1
X
X

BC BC BC BC
A

Reset=AB

Truth Table

K-Map

Input Clock Pulse

1
J

C
Q

B
Q

K
A

MOD-10 Ripple Counter

ABCD

Reset

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11

Reset=AC

Reset = AC

MOD-10 Ripple Counter

Reset=AC

Reset = AC

Input Clock Pulse

1
J

D
Q

C
Q

K
A
Q

MOD-14 Ripple Counter

0

ABCD
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11

10

Reset
13

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X

12
2

11

Reset=ABC

Reset = ABC

MOD-14 Ripple Counter

Reset=ABC

Reset = ABC

Input Clock Pulse

1
J

D
Q

C
Q

K
A

Synchronous Counter
Normal synchronous state machines
Normally edge triggered D or JK flip-flops are used as memory
devices
All the flip-flops are triggered synchronously by input pulse
from a master clock generator
Ripple counter connects all CLK leads to an outputs of the
previous stage
Clock signals from a common clock source are applied to CLK
leads of all the flip-flops in synchronous counter at a time. For
this reason, this type of counter is often called a parallel counter.

Synchronous Counter

Combinational Logic

clock
J

1st F/F
Q
Q

2nd F/F
Q
Q

(n-1)th F/F
Q Q

nth F/F
Q Q

Mod-4 Synchronous Counter

0

Present Next
State
State
A B
A B

0
0
1
1

0
1
0
1

01
10
11
00

Flip-flops input
JA K A J B K B
0 X
1 X
X 0
X 1

1 X
X 1
1 X
X 1

1
X

X
1

JA=B
1

KA=B
X
X

JB=1

KB=1

1
1

Mod-4 Synchronous Counter

Clock
1
J

B
Q

CLR

K
A
Q

Mod-8 Synchronous Counter

0

State diagram
0

JA=BC

Flip-Flop Inputs
A F/F B F/F C F/F
J A K A JB K B J C K C

00 0
001
010
011
100
101
110
111

0
0
0
1
X
X
X
X

Present Next
State
State
ABC ABC
0
0
0
1
1
1
1
0

0 1
10
11
00
01
10
11
0 0

X
X
X
X
0
0
0
1

0 X
1 X
X 0
X 1
0 X
1 X
X 0
X 1

1 X
X 1
1 X
X 1
1 X
X 1
1 X
X 1

Excitation Table of the sequential circuit

1

KA=BC

Mod-8 Synchronous Counter

0

JB=C

1
1

KB=C

x
x

JC=1

x
x

1
1

x
x

KC=1

1
1

1
1

x
x

Mod-8 Synchronous Counter

JA=KA=BC

JB=KB=C

JC=KC=1

Clock
1
J

C
Q

CLR

B
Q

K
A

Mod-8 Synchronous Counter

7

Present Next
State
State
ABC ABC

Flip-Flop Inputs
A F/F B F/F C F/F
JA K A JB K B J C K C

111
110
101
100
011
010
001
000

X
X
X
X
0
0
0
1

1 1 0
1 0 1
1 00
01 1
01 0
00 1
000
111

0
0
0
1
X
X
X
X

X
X
0
1
X
X
0
1

JA=BC

KA=BC

0
1
X
X
0
1
X
X

X
1
X
1
X
1
X
1

1
X
1
X
1
X
1
X

Mod-8 Synchronous Down Counter

1
1

0
0

x
x

JB=C

x
x

0
0

1
1

KB=C

JC=1

KC=1

Mod-8 Synchronous Down Counter

Clock
1
J

C
Q

CLR

K
A
Q

MOD-5 synchronous counter

0

JA=BC

NS
F/F Inputs
A B C J A K A JB K B J C K C

000
001
010
011
100
000

PS
ABC

001
010
011
100
000

0X
0X
0X
1X
X1

0X
1X
X0
X1
0X

X
X

KA=1

X
X

1X
X1
1 X
X 1
0 X

MOD-5 synchronous counter

x
x

JB=C

x
x

0
x

KB=C

JC=A

1
x

KC=1

1
X

X
X

MOD-5 synchronous counter

Vcc
Clock
J

C
Q

CLR

B
Q

K
A

Shift Register
Shift a new value in on each clock edge
Shift a value out on each clock edge
Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)

Symbol:

Implementation:
CLK

Q
S in S o u t

S in

S out
Q0

Q1

Q2

Q N-1

Shift Register with Parallel Load

When Load = 1, acts as a normal N-bit register
When Load = 0, acts as a shift register
Now can act as a serial-to-parallel converter (Sin to Q0:N1) or a parallel-to-serial converter (D0:N-1 to Sout)

D0
Load
C lk
S in

D1

D2

D N -1

Q0

Q1

Q2

S out
Q N -1

Memory Arrays
Efficiently store large amounts of data
Three common types:
Dynamic random access memory (DRAM)
Static random access memory (SRAM)
Read only memory (ROM)
An M-bit data value can be read or written at each unique Nbit address.

Address

Array

Data

Memory Arrays
Two-dimensional array of bit cells
Each bit cell stores one bit
An array with N address bits and M data bits:
2N rows and M columns
Depth: number of rows (number of words)
Width: number of columns (size of word)
Array size: depth width = 2N M
Address Data
Address

Array

Data

Address

Array

Data

11

0 1 0

10

1 0 0

01

1 1 0

00

0 1 1
width

depth

Memory Array: Example

22 3-bit array
Number of words: 4
Word size: 3-bits
For example, the 3-bit word stored at address 10 is 100

Example:
Address

Address Data
2

Array

Data

11

0 1 0

10

1 0 0

01

1 1 0

00

0 1 1
width

depth

Memory Arrays

A d d re s s

10

1 0 2 4 -w o rd x
3 2 -b it
Arra y
32

D a ta

Memory Array Bit Cells

Example:

Memory Array Bit Cells

Example:
0

Memory Array

Wordline:
similar to an enable
allows a single row in the memory array to be read or written
corresponds to a unique address
only one wordline is HIGH at any given time
2:4
Decoder
11

Address

wordline3

10

01

00

bitline2

wordline2

wordline1

wordline0

bitline1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

Data2

Data1

bitline0

Data0

Types of Memory
Random access memory (RAM): volatile
Read only memory (ROM): nonvolatile

RAM: Random Access Memory

Volatile: loses its data when the power is turned off
Read and written quickly
Main memory in your computer is RAM (DRAM)

ROM: Read Only Memory

Nonvolatile: retains data when power is turned off
Read quickly, but writing is impossible or slow
Flash memory in cameras, thumb drives, and digital
cameras are all ROMs

Types of RAM
Two main types of RAM:
Dynamic random access memory (DRAM)
Static random access memory (SRAM)
Differ in how they store data:
DRAM uses a capacitor
SRAM uses cross-coupled inverters

Robert Dennard
Invented DRAM in 1966 at
IBM

By the mid-1970s DRAM

was
in
virtually
all
computers

DRAM

Data bits stored on a capacitor

Called dynamic because the value needs to be refreshed
(rewritten) periodically and after being read:
Charge leakage from the capacitor degrades the value
Reading destroys the stored value

b itlin e
w o rd lin e
s to re d
b it

DRAM
bitline
wordline
stored + +
bit = 1

bitline
wordline
stored
bit = 0

SRAM

b itlin e
w o rd lin e

b itlin e

Memory Arrays
2:4
Decoder
11
Address

wordline3

10

01

00

bitline2

wordline2

wordline1

wordline0

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

Data2

DRAM bit cell:

bitline1

Data1

bitline0

Data0

SRAM bit cell:

bitline

wordline

bitline
wordline

bitline

ROMs: DOT Notation

b itlin e
w o rd lin e
b it c e ll
c o n ta in in g 0
b itlin e
w o rd lin e
b it c e ll
c o n ta in in g 1

ROM Storage

A ddress D ata
11

0 1 0

10

1 0 0

01

1 1 0

00

0 1 1
width

depth

ROM Logic

Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0

Example: Logic with ROMs

Implement the following logic functions using a 22 3bit ROM:
X = AB
Y=A+B
Z = AB

Example: Logic with ROMs

Implement the following logic functions using a 22 3bit ROM:
X = AB
2:4
D ecod er
Y=A+B
11
Z=AB
2
A, B
10
01
00
X

Logic with Any Memory Array

2 :4
Decoder
11
A d d re s s

10

01

00

b itlin e 2

w o rd lin e 3

w o rd lin e 2

w o rd lin e 1

w o rd lin e 0

b itlin e 1

s to re d
b it = 0

s to re d
b it = 1

s to re d
b it = 0

s to re d
b it = 1

s to re d
b it = 0

s to re d
b it = 0

s to re d
b it = 1

s to re d
b it = 1

s to re d
b it = 0

s to re d
b it = 0

s to re d
b it = 1

s to re d
b it = 1

D a ta 2

Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0

D a ta 1

b itlin e 0

D a ta 0

Logic with Memory Arrays

Implement the following logic functions using a
22 3-bit memory array:
X = AB
Y=A+B
Z=AB

2:4
Decoder
11

A, B

wordline3

10

01

00

bitline2

wordline2

wordline1

wordline0

bitline1

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 0

stored
bit = 0

bitline0

Logic with Memory Arrays

Called lookup tables (LUTs): look up output at each
input combination (address)
4-w ord x 1-bit Array
2:4
Decoder
00

Truth
Table
A
0
0
1
1

B
0
1
0
1

Y
0
0
0
1

A1

A0

bitline
stored
bit = 0

01
stored
bit = 0
10
stored
bit = 0
11
stored
bit = 1

Multi-ported Memories
Port: address/data pair
3-ported memory
2 read ports (A1/RD1, A2/RD2)
1 write port (A3/WD3, WE3 enables writing)
Small multi-ported memories are called register files
CLK

N
N
N
M

A1
A2
A3
W D3

W E3

RD1
RD2

Arra y

M
M

Logic Arrays
Programmable logic arrays (PLAs)
AND array followed by OR array
Perform combinational logic only
Fixed internal connections
Field programmable gate arrays (FPGAs)
Array of configurable logic blocks (CLBs)
Perform combinational and sequential logic
Programmable internal connections

PLAs
X =ABC + ABC
Y = AB

Inputs
M

Im plicants

AN D
AR R AY

OR
AR R AY

O utputs
A

OR ARRAY

ABC

ABC

AB

AND ARRAY

PLAs: DOT Notation

Inputs
M

AND
ARRAY

Implicants

OR
ARRAY

Outputs

OR ARRAY

ABC
ABC
AB

AND ARRAY

FPGAs: Field Programmable Gate Arrays

Composed of:
CLBs (Configurable logic blocks): perform logic
IOBs (Input/output buffers): interface with outside
world
Programmable interconnection: connect CLBs and
IOBs
Some FPGAs include other building blocks such as
multipliers and RAMs

Xilinx Spartan 3 FPGA Schematic

CLBs: Configurable Logic Blocks

Composed of:
LUTs (lookup tables): perform combinational logic
Flip-flops: perform sequential functions
Multiplexers: connect LUTs and flip-flops

Xilinx Spartan CLB

Xilinx Spartan CLB

Spartan CLB has:
3 LUTs:
F-LUT (24 x 1-bit LUT)
G-LUT (24 x 1-bit LUT)
H-LUT (23 x 1-bit LUT)

2 registered outputs:
XQ
YQ

2 combinational outputs:
X
Y

CLB Configuration Example

Show how to configure the Spartan CLB to perform the
following functions:
X = ABC + ABC
Y = AB

CLB Configuration Example

Show how to configure the Spartan CLB to perform the
following functions:
X = ABC + ABC
Y = AB
F4
X
X
X
X
X
X
X
x

(A)

(B)

(C)

(X)

F3
0
0
0
0
1
1
1
1

F2
0
0
1
1
0
0
1
1

F1
0
1
0
1
0
1
0
1

F
0
1
0
0
0
0
1
0

(A)

(B)

(Y)

G4 G3 G2 G1
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1

G
0
0
1
0

0
0
A
B

G4
G3
G2
G1

0
A
B
C

F4
F3
F2
F1

FPGA Design Flow

A CAD tool (such as Xilinx Project Navigator) is used to
design and implement a digital system. It is usually an
iterative process.
The user enters the design using schematic entry or
an HDL.
The user simulates the design.
A synthesis tool converts the code into hardware and
maps it onto the FPGA.
The user uses the CAD tool to download the
configuration onto the FPGA
This configures the CLBs and the connections between
them and the IOBs.