Table of contents:

Part 1
Introduction - (2)
Multiplexers - .. (3)
Part 2
Fundamentals of package - .. ()
Basics of structural modeling - ()
Formation of 16:1 multiplexer - .. ()
Appendix (A):
VHDL code of 4:1 multiplexer using behavior modeling----Xilinx simulated output and modelsim waveforms -----------Appendix (B):
VHDL code of package declaration----------------------------------VHDL code of 4:1 multiplexer----------------------------------------VHDL code of 16:1v multiplexer using structural modeling------Xilinx simulated output and modelsim waveforms ------------------/

Part1:
Introduction:
Multiplexer:
A multiplexer is a device that selects between a numbers of input signals. In a simple
form, a multiplexer has two signal inputs, one control output and one output.
Normally multiplexers are used to build digital semiconductors such as CPUs and
graphics controllers. In this applications, the number of inputs is generally a multiple of 2
(2, 4,8,16, etc.), the number of outputs is either 1 or relatively small multiple of 2, and
number of control signals is related to the combined number of inputs and outputs. For
example, a 2-input, 1-output multiplexer requires only 1 control signal to select the input,
while a 16-input, 4-output multiplexer requires 4 control signals to select the input and 2
to select the output.

Basics of behavioral modeling:

The highest level of abstraction supported in VHDL is called behavioral level of
abstraction. While creating behavioral description of a circuit, we describe the circuit in
terms of its operation overtime. This concept of time is the critical distinction between
behavioral descriptions of circuits and low level description (data flow level of
description).
Writing behavior-level VHDL is almost similar like software programming. The only
difference between behavior-level and software programming language is the underlying
execution platform. In the case of software, it is the operating system running on a CPU
and in the case of VHDL; it is the simulator or synthesized hardware.

Description of the output:

Part 2:

Fundamentals of package:
A VHDL package declaration is identified by the package keyword, and is used to collect
commonly used declarations for use globally among different design units. the main
advantage is the item defined within a package can be made visible to any other design
unit in the complete VHDL design and this concept is used in the second task of the
assessment.

Basics of structural modeling:

This is the third level of abstraction and is used to describe a circuit in terms of its
components. this model can be used to create from low level to very high level of
abstraction the structural level of modeling features in VHDL are very useful for
managing complexity describe simply this model starts with entity followed up by
architecture which includes initializing the components and mapping the input and output
ports with a reserved word port map.

Formation of 16:1 multiplexer:

According to the question the required number of 4:1 muxes to form a 16:1 multiplexer is
5, since the 16 inputs are formed from 4 mux, but in order to have only single output
which requires one more 4:1mux which has the inputs from the first four mux outputs
this has been depicted in the logic diagram.

Description of the output:

The output of the 16:1 mux mainly depends on the select lines but not on the inputs. this
can be described simply with the help of an example, let x0 to x15 denotes the number of
inputs and s3 to s0 denotes the select lines, when s3, s2, s1, s0 =1 0 0 1 then the output
depends only one the x9 input of the multiplexer i.e. if the x9 is high then output remains
high irrespective of the all other inputs and vice versa, so the select lines decides the
output of the multiplexer and this example is best suitable for applications to transfer data
over a channel from multilines in telecommunications and networking in computers etc.

Appendix codes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.mux4to1_package.all;
entity mux16to1 is
Port ( d : in STD_LOGIC_vector(0 downto 15);
s : in STD_LOGIC_vector(3 downto 0 );
y : out STD_LOGIC);
end mux16to1;
architecture structure of mux16to1 is
signal m:std_logic_vector(0 downto 3);
begin
mux1:mux4to1 port map(d(3 downto 0),s(1 downto 0),m(0));
mux2:mux4to1 port map(d(7 downto 4),s(1 downto 0),m(1));
mux3:mux4to1 port map(d(11 downto 8),s(1 downto 0),m(2));
mux4:mux4to1 port map(d(15 downto 12),s(1 downto 0),m(3));
mux5:mux4to1 port map(m(3 downto 0),s(3 downto 2),y);
end structure;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sixteentoonemux is
Port ( d0,d1,d2,d3 : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC);
end sixteentoonemux;
architecture Behavioral of sixteentoonemux is
begin
with s select

y<= d0 when "00",

d1
when "01",
d2
when "10",
d3 when others;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package mux4to1_package is
component mux4to1
port(
d: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic);
end component;
end mux4to1_package;

Outputs: