A Top-Down Design Verification Based on Reuse

Modular and Parametric Behavioral Modeling for

Subranging Pipelined Analog-to-Digital Converter
J. Wang', L. Siek', R. Filippi2 and K.A. Ng2
Centre of Integrated Circuits and Systems (CICS)
'School of Electrical and Electronic Engineering, Nanyang Technological University
2Chartered Semiconductor Manufacturing Limited
Email: wangOl57@ntu.edu.sg
Abstract-This paper proposes a new approach to high
speed pipelined A/D converter design. This technique combines
a known subranging technique into pipelined architecture. A 8bit IOOMSample/s subranging pipelined analog-to-digital
converter (ADC) is implemented using this technique. The

calibration techniques used are namely digital error correction,

redundancy, and coarse and fine synchronization. To validate
the proposed ADC, a top-down design methodology based on
modular and parametric behavioral components is adopted. It
supports a design process where non-ideal effects are
incorporated in an incremental way, allowing easy
architectural selection with fast and accurate simulations. The
behavioral models are written in standard hardware
description language, Verilog-AMS.

I.
INTRODUCTION
Analog-to-digital converters (ADCs) are the key design
blocks in mixed-signal chip design since ADC is an interface
between the digital signal processing systems and the analog
world [1]. With the rapid scaling of CMOS process, more and
more signal-processing functions are implemented in the
digital domain for a lower cost, lower power consumption,
higher yield, and higher re-configurability.
Digital design methodology have proven to be successful
due to the fact that logic circuits may be accurately simulated
with a high degree of abstraction, and from that transistor
implementation may be automatically synthesized using a
library of leaf cells, which are placed and routed
automatically [2]. However, these advantages are difficult to
transfer to analog and mixed signal design. One of the main
reason is that analog design automation is far beyond the
digital one, due to the inherent complexity of analog systems
[3]. The general belief is that behavioral modeling overly
simplifies the complexities of analog circuit operation
thought to be necessary to validate its operation.
To increase innovation in analog and mixed-signal design,
very often, a new concept or architecture is needed to be
proven first at the early stage of the design process far before
the transistor implementation. High descriptive behavioral
models are required to reliably simulate and verify complex
analog systems, thus saving silicon iterations and make all
the difference in timely arrival to market.

To allow top-down design and bottom up verification, it is

important to be able to simulate a cascade of blocks, each
with a different view. That is, some blocks represented as
behavioral models others at the transistor level, yet others as
abstract logic cells. Hence, the aim of this work is to

absrat
incorporate

methe

ase on mor

and

Fig. 1 shows the traditional pipelined ADC architecture.

The 8-bit pipelined ADC consists of 6 succeeding 1.5 bit
stages and a 2-bit flash at the end [4]. A pipelined ADC is
inherently a multistep amplitude quantizer in which
digitization is performed by a cascade of many topologically
similar or identical stages of low-resolution analog-to-digital
encoders. The primary potential advantages of the pipelined
architecture are high throughput and low hardware cost [5].
Pipelining enables high conversion throughput by inserting
analog registers, i.e., sample-and-hold amplifiers (SHAs), in
between stages that allow a concurrent operation of all stages.
This is done at the cost of an increased latency [6]. In a
typical 1.5 bit pipelined stage as shown in Fig. 1, the signal
passed to the subsequent stage is the conversion residue of
the current stage created by a digital-to-analog converter
(DAC) and a subtraction circuit. The maximum swing of this
residue signal is often brought back to the full-scale reference
level with a precision amplifier, also shown in Fig. 1. This
keeps the signal level constant and allows the sharing of an
identical reference throughout the pipeline stages. Breaking a

378

1-4244-0797-4/07/$20.00 ( 2007 IEEE

reuse

a reuse methodology based on modular and

parametric behavioral modeling into the design of a novel 8bit IOOMSample/s subranging pipelined ADC. This proposed
ADC is based on subranging and pipelined topology. In this
work, subranging techniques are integrated into pipelined
ADC. Both analog and digital error correction are used to
achieve a resolution of 8 bits. To validate the proposed
architecture, the behavioral description of the system is done
in Verilog-AMS.
Section II of this paper reviews the architecture of a
traditional pipelined ADC and explains the principle of the
proposed architecture design techniques. Section III presents
the simulation results, followed by a conclusion in Section
IV.
II. ARCHITECTURE DESIGN
A.
PipelinedADCArchitecture

high-resolution conversion into multiple steps greatly reduces

the total number of comparators in contrast to a flash
converter. A 1.5-bit/stage pipelined ADC only needs 2
comparators to resolve a 2-bit word as opposed to 22
comparators required by a 2-bit flash ADC. The large
accumulative interstage gain also relaxes the impact of later
stage circuit nonidealities on the overall conversion accuracy.
For medium- to high-resolution Nyquist applications,
pipelined ADCs have been demonstrated to achieve the
lowest power consumption at high conversion rates [7-10].

Proposed Subranging PipelinedADC Architecture

This paper describes a new architecture that makes use of a
coarse quantizer and a fine quantizer at the front-end of the
ADC as illustrated in Fig 2. The block diagram of the
proposed ADC, which is based on the conventional parallel,
feed-forward ADC is depicted in Figure 3. The proposed
ADC consists of an input sample-and-hold amplifier (SHA),
a 3-bit flash ADC which acts as the coarse quantizer and a
six-stage 1.5-bit/stage pipelined converter which acts as the
fine quantizer. The new architecture topology is described as
follow. The coarse quantizer (3-bit flash ADC) does a coarse
A/D conversion and passes selected reference voltage to the
fine quantizer for fine conversion that increases the precision
of the previous result, hence making the final result much
more precise [11]. The 3-bit flash ADC quickly compares the
sampled signal from the output ofthe SHA with the reference
taps derive from the full-scale reference voltage (VFS) in one
clock cycle to estimate and generate the first 3 most
significant bits (MSBs). These 3-bit MSBs are then used to
select the resistor segment from the reference ladder for fine
conversion.
The overlapping conversion ranges of the coarse and fine
quantizers and the corresponding digital correction algorithm
are described. One bit of redundancy, or overlap, is used in
this architecture to enable the fine quantizer to correct for the
out-of-range errors in the coarse quantizer, thereby relaxing
the precision required for the comparators of the coarse
quantizer [12]. One bit of overlap between this coarse
quantizer and fine quantizer provides for the correction of
offsets as large as 1/2 LSB of a 3-bit flash ADC, ie. 1/2
62.5mV where Vref
IV in the coarse
(Vref/23)
comparators, thereby simplifying their design.
The fine quantizer digitizes the same sampled input signal
as the coarse quantizer to encode the 6 least significant bits of
the entire 8-bit ADC. In this way, a total of 8-bit output is
achieved which represents the input voltage relative to the
full-scale reference voltage. Each of the six stages has a lowresolution sub-ADC with two-bit output and a multiplying
DAC (MDAC). The stage utilizes two nonoverlapping clock
phases: (DI and 02.

siii

2xRe'due

--

Aip1if;

D/A

MDAC

_______
1.5b

B.

Analog

Input SEA

Stage

Stage 6
2bitFlash

/1.5b

2b

Digital Eror CoecioDigital

8b Output
Fig 1. 8-bit Pipelined ADC architecture.
Coarse
Quantizer
Vin HashADC

Vin

Fine

Quantizer

Coarse Quantizer
F3i

DC
AnAog \
.HA--- 1-------

-/L

FneQuantilzr
StagI- Stag22
.5b

3b

A Stage6

/l.b

DigitalEfofCoffioig
Dit t D EllDrD[fsbbOll

8z

ltpl t

Fig 3. Proposed 8-bit Subranging Pipelined ADC.

2007 IEEE International Symposium on Integrated Circuits (ISIC-2007)

379

Conceptually, the comparators in the fine quantizer are

designed to resolve inputs as small as 1 LSB (1V/28
3.91mV) of the entire 8-bit ADC. However, with the use of
1.5-bit/stage pipelined architecture [13], the requirement for
the comparators are relaxed greatly to +/- Vref/16 (IV/16 =
62.5mV). In this way, the maximum allowable overall system
offset for the full 8-bit ADC corresponds to 16LSB. The
hardware complexity is thus reduced. If we choose to use a
single stage 6-bit flash ADC, 64 comparators are required.
However, a six-stage pipelined ADC will only use 2*6 12
comparators.
The final stage reused the sub-ADC of the previous stage
as compare to traditional pipelined ADC which consists of
only a 2-bit flash ADC at the final stage. In this way, the
design time is reduced and the same block can be reused. The
resulting 1.5 bits are delayed accordingly and combined with
digital correction to yield an 8-bit at the output of the ADC.
To design a traditional 8-bit pipelined ADC architecture, 8
stages are required. This results in a latency delay of 8 clock
cycles. However in this proposed architecture, by employing
parallelism, the coarse ADC (3-bit flash ADC) can be
designed to synchronize with the fine ADC (stage 1 of
pipelined architecture). Hence, effectively there is only 6latency delay for 6 stages instead of 8. The main advantages
of this architecture are the reduced in latency delay compared
to traditional pipelined ADC, relaxed analog circuit
requirements and the potential to extend to higher resolution
without compromising in area to achieve high speed.
=

+Vref
R

Coarse

__$ >

<>

R;

R' ,
R

'R

Quantizr

Reference
Ladder_

Comparator
outputs

the behavioral description of the complete system model is

in Verilog-AMS using Cadence AMS Designer.

_described
System level simulations verity the usefulness of the

>

Logic

Block

1\
_v

proposed 8-bit ADC achieved a DNL of +/- 0.2 LSB as

The dynamic linearity of the ADC was
characterized analyzing a fast Fourier transform (FFT) of
the output code with respect to a pure sinusoid wave [14].
Shown in Fig. 6, the measured peak SNDR reaches 46.5 dB
with
0 a 0.46-MHz input, equivalent to 7.43 effective number
1/ofbits (ENOB). Under the same condition, the peak SFDR is
69.9 dB. As can be seen, the architecture worked according
to the design demonstrating that subranging techniques can
be integrated into pipelined ADC.

shown in Fig. 5.
3-bi
MSBschrtezd
by

Corection

Fine Quantizer (1 Stage of Fine ADC)

bit-sync, Q
Dig a

Encoder

ROM

Fig 4. Synchronization between coarse and fine bits.

380

III. SIMULATION RESULTS

In this section, the technical aspects related to the
developed subranging pipelined ADC are analyzed, namely
the static and dynamic performance of the ADC. The
proposed architecture is partitioned into smaller blocks and
non-ideal
effects
such To
as offset
andthe
mismatch
arearchitecture,
added in an
incremental
manner.
validate
proposed

proposed architecture and the simulation results are shown as

follow. The differential nonlinearity (DNL), was measured
using a code-density test with a slow input ramp. The

-Vref
From

Synchronization between the coarse andfine bits

Unlike a two-step ADC, the fine and coarse bits are
generated synchronously. This allows the pipelined
architecture to have speed comparable to flash ADC.
However, perforing the operations in parallel introduces
timing challenges, since the coarse bits reach the output
before the fine pipelined bits do. To correct this, a correction
logic block is used after the coarse ADC. The coarse ADC is
designed to resolve the three most significant bits as
illustrated in Fig 4. Voltage comparators are used as in a
traditional flash architecture. The correction logic block
resolves timing differences that occur between the output of
the fine and coarse bits. In this work, a bit-synchronization
scheme is proposed to correct the errors caused by the delay
difference between the coarse and fine quantizer paths. The
bit-sync from the 2-bit fine flash ADC and the 3-bit from the
coarse flash ADC is fed into the synchronization block to
generate the final 3 MSBs, which will be latched. In this way,
the three most significant bits are not derived directly from
the coarse quantizer; instead, they are determined by the bitsync signal, which comes from the fine quantizer, thus the
offsets of the coarse quantizer comparators are not critical.
C.

Fig 5. DNL versus ADC output codes.

2007 IEEE International Symposium on Integrated Circuits (ISIC-2007)

IIn=0.46MHz[1]

20

fs=lOOMHz
O

(SNDR= 7.43-146.56dB

Aln

EENOB =

2nd Harmonic 72.9dB

-20
N

SFDR=69.9dB

z -40-

z-60

+ -60

-80

'\I
U)

-100

lo'

l120

105

10,
Frequency[Hz]

107

lo

Fig 6. FFT Spectrum of proposed ADC.

IV.

CONCLUSION

This

paper has presented a top-down design verification

based on modular and parametric behavioral modeling to

feasibility of
test the thefeasibility
of a novel
novel 8-bit
8-bit IOOMSample/s
1OOMSample/s
subranging pipelined ADC before circuit design is carried.
test

The modularity and the high degree of parameterization of

the models increase their reusability. The working principle

REFERENCES
T. N. Andersen, B. Hernes, A. Briskemyr, F. Telsto, J. Bjornsen, T.

E. Bonnerud, and 0. Moldsvor, "A cost-efficient high-speed 12-bit

pipeline ADC in 0.18-/spl mu/m digital CMOS, IEEE Journal of
Solid-State Circuits, vol. 40, pp. 1506-1513, 2005.
[2]
A. A. Abidi, "Behavioral modeling of analog and mixed signalIC's:
r
ccase studies of analog circuit simulation beyond SPICE,"
Proceedings of the IEEE Custom Integrated Circuits Conference,
pp, 443-450, 2001.
[3] A. J. Gines, E. Peralias, A. Rueda, N. M. Madrid, and R. Seepold,
"A mixed-signal design reuse methodology based on parametric
behavioural models with non-ideal effects," Proceedings of Design,
Automation and Test Europe Conference and Exhibition, 2002.
R. Wang, K. Martin, D. Johns, and G. Burra, "A 3.3 mW 12 MS/s
~~~~~~~~~~~~~~~~[4]
lOb pipelined ADC in 90 nm digital CMOS," ISSCC Dig. Tech.
Papers, Interational Solid-State Circuits Conference, vol. 1, pp.
278-279, Feb. 2005.
S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog[5]
to-digital converter," IEEE Journal of Solid-State Circuits, vol. 22,
pp. 954-961, 1987.
Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS
[6]
pipeline ADC with over 100-dB SFDR," IEEE Journal of SolidState Circuits, vol. 39, pp. 2139-2151, 2004.
[7]
D. Kurose, T. Ito, T. Ueno, T. Yamaji, and T. Itakura, "55-mW 200MSPS 10-bit pipeline ADCs for wireless receivers," IEEE Journal
ofSolid-State Circuits, vol. 41, pp. 1589-1595, 2006.
[8] H. Ishii, K. Tanabe, and T. lida, "A 1.0 V 40mW 10b lOOMS/s
pipeline ADC in 90nm CMOS," Proceedings of the IEEE Custom
Integrated Circuits Conference, pp. 395-398, 2005.
J. Arias, V. Boccuzzi, L. Quintanilla, L. Enriquez, D. Bisbal, M.
[9]
Banu, and J. Barbolla, "Low-power pipeline ADC for wireless
LANs," IEEE Journal of Solid-State Circuits, vol. 39, pp. 13381340,2004.
[10] T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline

A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp.

1995.
of166-172,
[11] J. Doernberg, P. R. Gray, andD. A. Hodges, "A 10-bit 5-Msample/s

of a surangin
pipelied ADCwas
Of a subranging
ADC was disussed.The
discussed. The abiity
ability of
pipelinRed

integrating subranging techniques into pipelined architecture

presented. By using Verilog-AMS, a standard hardware

CMOS two-step flash ADC," IEEE Journal of Solid-State Circuits,

vol. 24, pp. 241-249, 1989.

was

description language, the models can be easily exchanged

and simulated instandard electronic design automation
and simulated
in standard electronic design automation
(EDA) tools. The simulation is very fast and produces very
accurate results, with the inclusion of non-ideal effects in
models. The AMS simulations show that a new concept can
be stuiedand
an verified
verifed in the
he eary
deign cyle.
be studied
early stag
stage of design
cycle. It
verifies the usefulness of system simulation to circuit design.

[12]
[13]

B. Razavi and B. A. Wooley, "A 12-b 5-Msample/s two-step

CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol.
27, pp. 1667-1678, 1992.
S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran,
and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital

converter," IEEE Journal of Solid-State Circuits, vol. 27, pp. 351-

1992.
It358,
[14] J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of

Further work is being developed in the transistor-level

design.

A/D converters," IEEE Journal of Solid-State Circuits, vol. 19, pp.

820-827,1984

ACKNOWLEDGMENT

The authors would like to thank Chartered Semiconductor

Manufacturing for sponsoring this research work. J. Wang
acknowledges the Joint Industry Graduate Scholarship from
Nanyang Technological University of Singapore, Economic
Development Board (EDB) and Chartered Semiconductor
Manufacturing, Singapore. J. Wang thanks Chee Piew Yong
from A-STAR, Institute for Infocomm Research for sharing
his insights and experience.

2007 IEEE International Symposium on Integrated Circuits (ISIC-2007)

381