IC TECHNOLOGY

TERM PAPER
SILICON-ON-INSULATOR

BY: AKSHAT SINGH

B.TECH ECE
11004367

What is SOI?
With Silicon-On-Insulator (SOI) wafers, transistors are formed in thin layers of silicon
that are isolated from the main body of the wafer by a layer of electrical insulator,
usually silicon dioxide. The silicon layer thickness ranges from several microns for
electrical power switching devices to less than 500 for high-performance
microprocessors.
Isolating the active transistor from the rest of the silicon substrate reduces the electrical
current leakage that would otherwise degrade the performance of the transistor. Since
the area of electrically active silicon is limited to the immediate region around the
transistor, switching speeds are increased and sensitivity to "soft errors", a major
concern for large-scale data storage and high-volume servers, is greatly reduced.

SOI Fundamentals
Silicon-On-Insulator (SOI) is a new way of starting the chip making process, by
replacing the bulk silicon wafers (approximately 0.75 mm thick) with wafers which have
three layers; a thin surface layer of silicon (from a few hundred Angstrom to several
microns thick) where the transistors are formed, an underlying layer of insulating
material and a support or "handle" silicon wafer. The insulating layer usually made of
silicon dioxide and referred to as the "buried oxide" or "BOX", is usually a few thousand
Angstroms thick. When transistors are built within the thin top silicon layer, they switch
signals faster, run a lower voltages and much less vulnerable to signal noise from
background cosmic ray particles. Since on an SOI wafer each transistor is isolated from
its neighbor by a complete layer of silicon dioxide, they an immune to "latch-up"
problems and can spaced closer together than transistors built on bulk silicon wafers.
Building circuits on SOI allows for more compact chip designs, resulting in smaller IC
devices (with higher production yield) and more chips per wafer (increasing fab
productivity).

Why is SOI important?

SOI enables increased chip functionality without the cost of major process equipment
changes (such as higher resolution lithography tools). The advantages of IC devices
built on SOI wafers (mainly faster circuit operation and lower operating voltages) have
produced a powerful surge in the performance of high-speed network servers and new
designs for hand-held computing and communication devices with longer battery life.
Advanced circuits, using multiple layers if SOI-type device silicon, can led the way to a
coupling of electrical and optical signal processing into a single chip resulting in a
dramatic broadening of communication bandwidth with new applications such as global
ranging, direct-link entertainment and communication to hand-held devices. Some types
of SOI devices, using radiation-resistant buried insulators, will increase the reliability
and functionality of communication satellites and other orbiting and deep-space
systems. SOI devices also extend the operating range of silicon devices to high
temperature environments such as built in diagnostics and controls for automotive and
other combustion engines.

Technology Issues
Silicon-on-Insulator (SOI) wafers consist of three layers: a thin (200 A to several
microns, depending on the application) layer of single-crystal silicon on a thick (1000 to
4000 A) silicon dioxide layer that is bonded to a conventional "handle" wafer. The entire
transistor is located in the thin top layer of silicon and electrically isolated from the bulk
wafer by the buried oxide (BOX) layer.

Figure 1: Sketch of metal-oxide-semiconductor (MOS) transistors on a bulk silicon

wafer (left) and silicon on- insulator (SOI) wafer (right).
The essential operation of an MOS transistor is the controlled flow of electrical current
from a source junction to a drain junction (as indicated by the arrow) when the voltage
on the gate is switched beyond the threshold or "turn-on" voltage. For an MOS
transistor formed on bulk silicon wafer the region around the source and drain junctions
need to be depleted of local charge during signal switching. This slows the switching
process down. In an MOS transistor formed on an SOI wafer, the entire transistor is in a
thin (usually less than 0.2 um thick) silicon layer insulated from the bulk of the silicon
"handle" wafer by a thick (usually 0.1 to 0.4 um) oxide. The smaller volume of silicon
that is depleted during switching of an SOI transistor increases the speed of signal

processing and allows operation at lower drive voltages. The core circuit of CMOS ICs
is an inverter, consisting of a linked pair of complementary transistors. On a bulk silicon
wafer, the transistors are formed in a pair of doped "wells". On an SOI wafer, the
transistors are formed in a thin silicon layer insulated by a thick buried oxide (or "BOX").
Because of the increased efficiency of the SOI device isolation the surface area of the
circuit can reduce, allowing for smaller die size and increased device count per wafer.

Figure 2: CMOS inverter transistors on bulk silicon and SOI wafers sketched with the
same gate size (critical dimensions). The smaller size of the SOI inverter is due to the
more efficient isolation of SOI transistors.

The principal advantages of electrical devices fabricated in SOI wafers are:

A 20% to 50% increase in switching speed compared to similar circuits built on

conventional "bulk" silicon wafers.
The ability to operate at lower voltages (less battery power drain and chip
heating).
Events from cosmic ray particle showers (reducing the need for error correction
operations in high-speed data flow servers and memory arrays).
Increased circuit packing due to simplification of the lateral and vertical isolation
structures, increasing chip yield and die count per wafer.

Even though the widespread use of SOI materials is relatively recent, the range of
applications and types of SOI wafers is extensive. The thickness of the top Si layer
ranges from several microns for MEMS (Micro Mechanical- Electrical Systems) and
sensors to a few hundred Angstroms for fully-depleted CMOS transistors. BOX
thickness range from 500 Angstroms to several microns. The thickness of the SOI
layers is determined by voltage isolation and device scale requirements.

Figure 3: SOI layer thickness for various applications.

Types of SOI-CMOS transistors are characterized by the thickness of the Si-SOI layer.
For partially-depleted SOICMOS, the device Si layer is thicker than the depletion layer
under the channel, in the range of 100 to 200 nm. As CMOS gates are scaled to 5-65
nm and smaller, CMOS devices will be formed in thin Si layers which are fully depleted
in the channel region between the sources and drain junctions. For fully-depleted
CMOS, the Si device layer is of the order of 50 nm and shrinking towards 10 nm, or the
"nano-SOI" regime. Fully-depleted CMOS devices will take advantage of the ability of
advanced SOI fabrication processes (such as NanoCleave) to provide wafers capable
of forming dual-gate transistors, with control gates both above and below the thin
channel.

On a more fundamental level, SOI wafers provide the most viable path for extension of
CMOS-VLSI transistor circuits beyond the "end of the roadmap" barriers detailed in the
ITRS99 (International Technology Roadmap for Semiconductors-1999) for planar
CMOS on bulk silicon wafers. The large numbers of basic problems with continuing
scaling of conventional CMOS on bulk wafers are expected to become limiting factors
for gate sizes less than 65 nm, zanticipated to be the scale of leading product by 2006.
By using thin (less than 500 A) silicon SOI layers, research

CMOS transistors have already been fabricated with excellent performance with 25 nm
gates. According to the ITRS schedule, CMOS gates of 25 nm are expected to be
characteristic of advanced technology circuits by 2014.

Figure 5: The International Technology Roadmap for Semiconductors (ITRS99)

projects a steady decrease in gate size and CMOS junction depths with time. The
limitations of planar CMOS transistors are projected to reach crisis proportions at and
below a gate size of 65 nm in 2006-2008. After this time (and transistor scale), most
advanced transistors are expected to use fully-depleted, dual-gate architectures on SOI
wafers.
The principal technology advances needed for the migration of CMOS devices to SOI
wafers are:

Fabrication techniques for high quality SOI wafers; and

Modification of transistor designs to take account of the special characteristics of
SOI layers.

The requirements for circuit modification for SOI are minimized by using a "partially
depleted" SOI transistor on relatively thick (1000 to 2000 A) device silicon, such as the
production conditions used by IBM. Many circuit development groups are working on
"fully depleted" CMOS, where the full circuit advantages of SOI are realized, with
production introductions scheduled in 2001 through 2005. After the "end of roadmap"

scaling to sub-65 nm gates, the majority of advanced technology CMOS transistors will
be fully depleted SOI. The successful fabrication of high quality SOI wafers depends on
development of second-generation technologies, such as SiGen's NanoCleave process.
Full adoption of SOI technologies will follow with the expansion of SOI wafer fabrication
capacity and the resulting reductions in wafer cost and increased range of available SOI
wafer types.

Advantages of SOI technology

Ionizing mediums
Insulation
Elimination of parasitic thyristor
Reduction of drain /source junction
Operating in high temperature
Three-dimensional integration
Reduction of short channel effects
Saturation current is high than MOS/Si Transistor
Reduction of carriers effects
Reduction of substrate polarization effect.

II. Fabrication of SOI wafers

Many techniques have been developed for producing a film of single-crystal silicon on
top of insulator. Some of them are based on the epitaxial growth of silicon on either a
silicon wafer covered with an insulator (homo-epitaxial techniques) or on a crystalline
insulator (hetroepitaxial techniques). Other techniques are based on recrystallization of
thin silicon layer from the melt (laser recrystallization, e beam recrystallization and zonemelting recrystallization). Silicon-on-insulator can also be produced from a bulk silicon
wafer by isolating a thin silicon layer from the substrate through the formation and
oxidation of porous silicon (FIPOS) or through the ion beam synthesis of a buried
insulator layer(SIMOX, SIMNI and SIMON). Finally, SOI material can be obtained by
thinning a silicon wafer boned to an insulator and mechanical substrate (wafer bonding
BESOI). Every approach has its advantages and its pitfall, and the type of application to
which the SOI materials is destined, dictates the material to be used in each particular
case. SIMOX and UNIBOND are seems to be the ideal candidates for VLSI CMOS
application, while wafer bonding is more adapted to bipolar and power applications.
Now well review some of the techniques have been used in producing the SOI
materials.
Hetro-epitaxial Techniques: Hetro-epitaxial Silicon-on-insulator films are obtained by
epitaxially growing a silicon layer on a single crystal insulator (see figure 6). The films
are grown using silane or dichlorosilane at temperatures around 10000C. All the
insulating substrates have thermal coefficients which are 2- 3 times higher than that of

silicon which generated lot of stresses at interface. Therefore, thermal mismatch is the
single most important factor determining the physical and electrical properties of silicon
films grown on bulk insulators. Silicon-on-sapphire (SOS) is one of single most mature
of all Hetro-epitaxial materials used. SOS is fabricated by epitaxial growth of a Si film on
Al2O3. The electrical properties may suffer from lateral stress, in-depth in homogeneity
of the film, and defective transition layer at the interface. Good quality 100 nm thick
films, on 6 in. SOS wafers are now available.
Homo-epitaxial techniques: Epitaxial lateral overgrowth, method consists of growing a
single crystal Si film, from the substrate (i.e. the seed) through and above the SiO2
layer. ELO process requires a post-epitaxy thinning of the Si film, which can for example
be achieved by using a patterned oxide, the silicon film in excess is removed leaving an
isolated Si island (dotted line) in the BOX. The main application of ELO technique is the
integration of 3-D stacked circuits.

Figure 6: ELO technique. A) Growth from seeding window B) Coalescence of adjacent

crystals C) Self-planarization of the surface.
Recrystallization Techniques: MOS transistor can be fabricated on large grained
polysilicon deposited on oxidized silicon substrate. But the presence of grain boundaries
brings about low surface mobility and high thershould voltages. Mobility and thershould
voltages values can be improved by passivating the dandling silicon bond via hydrogen

plasma treatment. High performance ICs however require much better device
properties, and grain boundaries must be eliminated from the deposited silicon film. This
is the goal of all recrystallization techniques such as Laser beam, E-Beam, zone melt
recrystallization. Laser and e-beam both are relatively slow processes (uses a pointed
energy source) compared to zone melting method in which incoherent light or near IR
source is used.
FIPOS: In Full isolation by oxidized porous silicon anodic reaction is used to convert a
particular region (predefined by p-type doping) of the Si wafer into porous silicon. During
subsequent oxidation, the porous Si transforms very rapidly and selectively in a BOX.
FIPOS may be able, in the future, to combine SOI circuits with electroluminescent
porous Si devices.
SIMOX: In the last decade, the dominant SOI technology was SIMOX, which is
synthesized by internal oxidation during the deep implantation of oxygen ions into a Si
wafer. Annealing at high temperature restores the crystalline quality of the film. SIMOX
8 in. wafers have good thickness uniformity, low defect density (except threading
dislocations: 104106 cm-2), sharp SiSiO2 interface, robust BOX, and high carrier
mobility. Some basic processes of SIMOX are described in figure 7 and figure 8.

Figure 7: The principal of SIMOX: a heavy dose oxygen implantation into silicon
followed by an annealing step produces a buried layer of silicon dioxide below a thin
single crystal silicon overlayer.

Figure 8: Evolution of the structure of the SIMOX structure as function of postannealing temperature (implant dose= 1.5 1018 cm-2, energy = 200 keV). A) As
implanted, B) 2-hr. annealing at 11500C, C) 6 hour annealing at 11850C, D) 6 Hr.
Annealing 13000.
Wafer bonding (WB): Wafer bonding and etch back is another mature SOI technology.
An oxidized Si wafer is mated to a second Si wafer. When two flat, hydrophilic surfaces
such as oxidized surfaces are placed against one another, bonding naturally occurs,
even at room temperature, which forms the hydrogen bonds across the gap between
two surfaces. After bonding, upper wafer is thinned down from 600microns to few
microns to reach the target thickness of the silicon film. The thinning is usually done
grinding followed by chemical polishing or grinding followed by etch-back process
(preferred). In etch-back process a P+ layer is formed at the surface near the oxide
where the etching is required and using proper etchant the bare Si surface above the
bonded SiO2 is obtained with approximately 12nm surface tolerance.
UNIBOND: This material again belongs to the family of wafer bonding structures. But
unlike the wafer bonding method, in UNIBOND, the etch back process is avoided. The
revolutionary Smart- Cut mechanism uses the deep implantation of hydrogen (dotted
line in figure 9) to generate micro cavities. After bonding and annealing, the wafers
separate naturally at a depth defined by the location of hydrogen micro cavities which
have eventually coalesced. The UNIBOND wafer is finished by touch polishing. The
smart-cut approach has several outstanding advantages: no etch-back step, with much
better uniformity of surface (0.15nm) the prime-quality wafer A is fully recyclable and
UNIBOND reduces to a single wafer process, only conventional equipment is needed
for mass production, relatively inexpensive wafers are manufacturable, and unlimited
combinations of BOX and film thicknesses can be achieved in order to match most
device configurations (ultra-thin CMOS or thick-film power transistors and sensors). The
defect density in the film is very low, the electrical properties are excellent, and the BOX
quality is comparable with that of the original thermal oxide. It is worth noting that the
two interfaces of the BOX are ideally organized: the top interface (filmBOX) has the

high quality expected from thermal oxidation whereas the bonded interface, of poorer
quality, is located underneath the BOX and has little influence on the SOI device
performance. A fascinating aspect is that the smart-cut process is adaptable to a variety
of materials: SiC or IIIV compounds on insulator, silicon on diamond or glass, etc. The
possibility to enroll, in the SOI-based microelectronics, these materials with large band
gap, photonic, or high-temperature capabilities opens exciting prospects for the
integration of totally new types of devices.

Figure 9: UNIBOND Process flow, created by 'Michel BRUEL from LETI