Digital Functions

Lab Session 4
3
Finite State Machine

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

Overview
R/W

Microprocessor

Address
N-bit

DRAM

DATA

Address

MUX

N/2-bit

MUX
/RAS
MEMREQ

DRAM
Controller

/CAS

BUSY

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

MUX

Overview
Multiplexing High/Low order addresses

/RAS=1
High Order
Address Latch

N-bit HOA

2N-bit Address Bus

N-bit LOA

M
U
X

N-bit

/CAS=0
Low Order
Address Latch

/MUX

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

DRAM Controller
(TOP Level)

DRAM Controller
What do we need?
TOP Level Design

REFREQ Unit (Schematic)

Arbiter (FSM in StateCAD)
RAS_CAS Generator (FSM in StateCAD)
Swapper (Schematic)

Arbiter

RAS_CAS
Generator

REFREQ
Unit

Introduction

Logics

Universal Counter Modulo Counter

Swapper

DRAM Controller

Shifting LED

Digital Functions
Functions
&
Micropro
cessors
Microprocessors

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

DRAM Controller

REFREQ Unit

REFREQ Unit
Why do we need a refresh request unit?
Because DRAM is forgetful, it has to be refreshed every 2 - 16 ms

How to refresh?
Use an 8-bit counter, count from 0 to 28 (256 clock pulses), the carry bit is
used as REFREQ_EX
In simulation, 256 clock pulses is too long
use external triggered
refresh signal as REFREQ_EX
8-bit
counter
REFREQ_EX (To arbiter)
EXT_TRIG_REF

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

RAS_CAS

DRAM Controller
RAS_CAS

Generate row address strobe and column address strobe signals

Inputs: MEMREQ and REFREQ
Outputs: /RAS, /CAS, /MUX and BUSY

/RAS before /CAS:

Memory Access Process

/CAS before /RAS:

Memory Refresh Process

2
2

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

Swapper

DRAM Controller
Swapper
alternate /RAS and /CAS
Thus alternate /RAS and /CAS pattern between
Memory Access Process and Refresh Access Process.

/RAS before /CAS:

Memory Access Process

/CAS before /RAS:

Memory Refresh Process

2
2

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
TOP level
REFREQ Unit
RAS_CAS
Swapper
Arbiter

Arbiter

DRAM Controller
Arbiter
Inputs
MEMREQ_EX:
REFREQ_EX:
BUSY:

External input from Microprocessor

Internal signal to generate refresh signal
Tell the Arbiter if there is already a memory access

Outputs
MEMREQ:
REFREQ:
SWAP:

To RAS_CAS, memory request

To RAS_CAS, refresh request
To tell Swapper (not) to swap /RAS and /CAS

MEMREQ_EX
REFREQ_EX

MEMREQ

Arbiter

BUSY

Introduction

Logics

Universal Counter Modulo Counter

REFREQ
SWAP

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
Arbiter
RAS_CAS
REFREQ
Swapper

Arbiter

DRAM Controller
Arbiter

Suspended

Introduction

Logics

Universal Counter Modulo Counter

DRAM Controller

Shifting LED

Digital Functions
Functions

DRAM
Finite State
Machine

DRAM Controller
Overview
Arbiter
RAS_CAS
REFREQ
Swapper

Arbiter
MEMORY REQUEST

No request

If (No requests) then

Stay at State 0

If (Memory request = 1) then

MEMREQ = 1
If (REFREQ_EX = 1) then

Refresh related
States

Logics

Suspend REFREQ_EX
MEMREQ = 0
REFREQ = 0
SWAP = 0

State 0
MEMREQ=0
REFREQ=0
SWAP = 0

MEMREQ_EX = 1
and
REFREQ_EX = 0

State 1
MEMREQ=1
REFREQ=0
SWAP =0

BUSY = 0
and
MEMREQ_EX = 0

REFREQ_EX = 0

REFREQ_EX = 1

If (REFREQ_EX = 0) then

Introduction

Arbiter

DRAM Controller

......

MEMREQ = 0
REFREQ = 0
SWAP = 0

State 2
MEMREQ=0
REFREQ=0
SWAP =0

REFREQ_EX = 1

REFREQ_EX = 0 and (BUSY = 1 OR

(BUSY =0 and MEMREQ_EX = 1))

Universal Counter Modulo Counter

DRAM Controller

State 3
MEMREQ=0
REFREQ=0
SWAP =0
BUSY = 1
or
MEMREQ = 1

Shifting LED