designfeature By S Meiyappan, K Jaramillo, and P Chambers, VLSI Technology Inc

YOUR ABILITY TO REUSE BLOCKS EXPRESSED IN AN HDL IS

CRITICAL TO DESIGNING SYSTEMS ON CHIPS. HERE ARE
SOME TIPS YOU CAN USE TO GENERATE VHDL-BASED
BLOCKS THAT YOUAND OTHERSCAN REUSE
IN SUBSEQUENT CHIP DESIGNS.

10 tips for generating

reusable VHDL

esign reuse is the process of migrating high-quality intellectual property (IP) from one ASIC design to another. With the tremendous advances in semiconductor
technology, it is increasingly difficult to bridge the
productivity gap between what technology offers and
what silicon productivity allows. Designing full-custom ASICs to occupy as much silicon area as possible is becoming increasingly challenging. To achieve
the highest level of silicon efficiency, designing semicustom ASICs with highly reusable design entities
has become todays challenge.
The use of predesigned and preverified design
blocks to achieve a high level of design reuse is the
most promising technique for bridging the gap between available gate count and designer productivity. Designing a complex chip requires an HDLbased design. Effective HDL generation with design
reuse in mind will help you create
IP cores that are usable in
multiple chip designs.
Figure 1
EN
THE DESIGN-REUSE CHALLENGE
Designing for reuse poses new
and innovative challenges to a designer. Before being reusable, a
design must be usable, which
means design using good design
practices. A reusable design must
be designed with the mindset of
solving a general problem; wellcoded, commented, and documented; verified to a high level of
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confidence; and independent of technology, design

tools, and applications.
Because of mounting time-to-market pressures,
designers often bypass some or all of these guidelines, rendering a design virtually nonreusable. However, following these guidelines speeds designing,
verifying, and debugging a project by reducing iterations throughout the coding and verification loops.
The efficient use and reuse of designs play a vital role
in the creation of large ASICs with aggressive design
schedules.
Although chip designers have used HDLs for
some time, most designs today do not use the builtin design-reuse features of the languages. In other
words, designers do not thoroughly understand the
purpose of the HDLs and misuse or underuse their
features. On an average, only 20% of the designs in
the industry are reusable. With an increasing need

CLK

COUNT (1:8)

RESET_N

In this up-counter, count is disabled, and bit width equals 2.

August 19, 1999 | edn 49

designfeature Generating reusable VHDL

for design reuse, the emphasis on coding
techniques for design reuse is on
Figure 2
the rise. This article covers developing reusable designs using the nativeEN
language features of VHDL and designreuse techniques pertaining to synCLK
thesizable VHDL. Unless stated otherwise, the VHDL discussed complies with
the VHDL-87 standard.
RESET_N

D
EN
D
EN
COUNT (1:8)

VHDL FEATURES PROMOTING REUSABILITY

Chip designers have used VHDL for
more than a decade. One of the primary In this enabled up-counter, bit width equals 2.
intents of developing designs in VHDL
is reusability, although, designers, until
EN
recently, have not effectively employed
this technique. You can exploit the
Figure 3
feature-rich VHDL for reuse techniques. VHDL features include generics,
D
packages of constants, generate stateD
ments, unconstrained arrays, VHDL attributes, block statements for inline-design partitioning, record data types for
data bundling, configuration specificaCLK
tions, the ability to tie ports off to known
RESET_N
constants, the ability to leave unused
output ports open and unconnected, array aggregates, functions, and proce- Simple changes to the HDL code produce a down-counter with no enable.
dures.
TIP 1: GENERICS

ZERO

A
B

COUNT (1:8)

ZERO

Figure 4
You use generics to write parameterized models of varying structure
and behavior (Reference 1). Listing 1
(a)
(b)
provides a simple example of a synchronous counter with modifiable structure A double AND-gate segment of combinatorial logic (a) and the same AND-gate logic with one input
and behavior. You accomplish this mod- of the first AND gate tied low (b) show the value of tying off ports to reduce synthesized logic. This
ification through the use of VHDL technique effectively eliminates both logic gates.
generics. This example illustrates the use
of generics for modifying structure and sign may require two counters: one that
Lines 3 to 14 instantiate the counter
behavior using the languages features for counts to 1024 and another that counts as a 10-bit up-counter with the count-ensimulation and synthesis. You can enable to eight. Designing two separate coun- able-logic turned on.
and disable selective features by turning tersone that is 10 bits wide and one
The TenBit counter instantiation
generics on and off. For example, if you that is 3 bits widehas drawbacks of un- uses named association for its generics
set the COUNT_ENABLE generic to necessary investment in design, verifica- and ports.
FALSE in line 8, then none of the logic tion, and synthesis time.
Unmapped generic values in the indescribed in lines 32 to 38 is elaborated
If you use the generic approach to de- stantiation assume default values.
or synthesized, but the parent design can sign a counter with reuse in mind, you
Lines 18 to 30 instantiate the same
still have a count enable. Using different save a great deal of design, synthesis, and counter as a 3-bit down counter with
values for OutDelay and DOWN_ verification time. The use of generics for count-enable-logic turned off.
COUNT changes the counters behavior parameterizing structure and behavior is
The ThreeBit counter instantiation
(although synthesis ignores the OutDe- essential for design reuse-applications. uses positional association for its generlay), and changing BIT_WIDTH or The following examples illustrate the in- ics and ports. In general, it is not advisCOUNT_ENABLE modifies the struc- stantiation of the counter in Listing 1 in able to use positional association because
ture of the design. Creating designs with an application that requires a 10-bit up- changing a parameter or port in the
generics enables design reuse in various counter and a 3-bit down-counter
reusable design requires the same modicircumstances where you need different
The example in Listing 2 illustrates the fication in all instances of that design.
structure or behavior. For example, a de- following points:
The use of generics can help greatly

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designfeature Generating reusable VHDL

in resources and time when you
BMSB
need multiple instances of the
BMSB-N-1
BMSB-1
Figure 5
same design.
BLSB
BMSB
BINARY
BMSB-1
BMSB-2
The use of generics to parameterize
designs helps not only to create reusable
XOR
XOR
XOR
design blocks, but also to remove unnecessary logic or to modify useful logic during synthesis. Some synthesis tools help
G-LSB
G-MSB-1
G-MSB-2
GRAY
G-MSB
create macros and templates when you
(a)
parameterize designs through generics.
1
0
You can use the feature thus created as a
XOR
XOR
library element in subsequent designs for
1
0
0
BINARY
simulations or synthesis. Parameterizing
bus and register widths through generics
is a simple example of the use of generGRAY
1
1
0
ics.
(b)
Consider the example of the counter
in Listing 1 with the following generic
This binary-code to gray-code algorithm (a) does conversions, such as binary 100 to its gray-code
values:
equivalent of 110 (b).
BIT_WIDTH => 2
COUNT_ENABLE => true
DOWN_COUNT => true
various features on and off. This tech- adder; register address; power-on-reset
OutDelay => 3 ns
nique lets you use only the features that value for a register; supported and reWhen synthesis elaborates this design, apply to your current project.You can use served bits in a register; clock-divide rathe synthesis tool ignores the generic for generics to specify such features as FIFO tio for a clock-divider circuit; and numOutDelay because the tool cannot han- depths; bus interface, such as PCI or ber of buffers in a clock tree.
dle time-delay elements in mapping log- ARM System Bus; architecture, such as
If you make the design somewhat
ic. The synthesis tool creates a 2-bit up/down counter, flip-flop-based regis- generic, others can more easily reuse it.
down-counter with the count_enable ter versus latched-based register, and rip- One drawback of the generic approach
logic, as the following examples illustrate. ple-carry adder versus carry-look-ahead occurs when you use generics in a hierConsider another case of
archy. To apply the generics to
the same counter with the
the lowest level of the hierarLISTING 1 SYNCHRONOUS COUNTER DESIGNED WITH GENERICS
following generics:
chy, the generics must pass
BIT_WIDTH => 8
down through the hierarchy.
COUNT_ENABLE =>
This passing down may infalse
volve generics having to go
DOWN_COUNT
=>
through blocks that do not
false
use the value of the generics.
This code creates an 8-bit
Another drawback of using
up-counter without the
generics is that, as the list of
count-enable logic. If gate
generics grows, it becomes
count is an important pamore cumbersome to carry
rameter, you can efficiently
them around at each point in
optimize unused logic using
the hierarchy. A third drawthis method. You can modback is that some synthesis
ify the structure (changing
tools have limited support for
the BIT_ WIDTH) or begenerics. For example, a synhavior (up-or down-countthesis tool may require all
er, count_ enable disabled
generics to be of type integer.
or enabled) during design,
An efficient way to avoid these
synthesis, and simulation
problems is to use a package
using this elegant approach
of constants.
to parameterization.
TIP 2: CONSTANTS
Generics are excellent for
specifying widths of counA VHDL package is a simters, buses, shift registers,
ple way of grouping a collecand other designs, but as
tion of related declarations
Listing 2 shows, you can
that serve a common puralso use generics to turn
pose. You can make the pack-

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designfeature Generating reusable VHDL

age visible to the appropriate
parts of a model. Some nonsynLISTING 2COUNTER INSTANTIATION FROM LISTING 1
design blocks by using library
thesizeable constructs in generstatements. Using library stateic definitions, such as enumerments means that adding or
ated data types, become
changing a parameter requires
synthesizeable when you use
you to modify only one package
them in a package. The package
file. Also, some synthesis tools
may contain other constants
do not allow the use of Boolean,
and information that you may
string, enumerated, or array
use for parameterization, yet the
types for generics. In such casdesign may still use this infores, using library statements almation. The package serves as a
lows you to use a constant in a
common place-holder for this
package. Most synthesis tools
type of shared information. Furallow most data types, and usthermore, a package of paraming library statements lets packeters provides better code strucages use TYPE statements for
ture, provides efficient organenumerated data types. A packization, and is self-documentage of constants also lets you
ing.
use the same package for design
Figure 1 shows the parameand simulation in designterized counter for different valaware testbenches.
the design, you have to change only the ues of generics and constants. The countAs an example of the use of a package parameter value in the package, and you er was synthesized using Synopsys
of constants, consider changing the can see the change in all the units refer- (www.synopsys.com) Design Compiler
counter in Listing 2 to use such a pack- encing the parameter. A package of con- with a 0.2-mm standard-cell library with
age. Also, assume that the package resides stants can also use subtypes and enu- the BIT_WIDTH parameter set to 2 in all
in the pkgs VHDL library (Listing 3). merated data types to reference the synthesis tests.
This counter example shows that using parameters for reusability and readabiliIn the counter of Figure 1,
a package of constants is similar to using ty, and a central package can serve as a COUNT_ENABLE is false (unconnected
generics for parameterization. In addi- package of parameters to parameterize en enable signal), BIT_WIDTH is 2, and
tion, using a package of constants allows an entire design. Further, using a package DOWN_ COUNT is false (a convenany design entity to reference the pa- makes it relatively simple to use arrays tional up-counter). In the counter of Figrameters in the package without any and other composite data types for pa- ure 2, an up-counter with count enable,
overhead. Also, to change the structure of rameterization.
COUNT_ENABLE is true (connected en
You can work on a enable signal), BIT_WIDTH is 2, and
package separately as a DOWN_COUNT is false. Also in the
LISTING 3COUNTER DESIGNED USING A PACKAGE OF CONSTANTS
design unit, create the counter of Figure 3, a down-counter
package independently with no enable, COUNT_ENABLE is
of the design, and reuse false (unconnected en enable signal),
the package in different BIT_WIDTH is 2, and DOWN_
LISTING 4COUNTER USING DEFERRED-CONSTANTS-PARAMETER PACKAGE

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designfeature Generating reusable VHDL

COUNT is true. These three
design. For example, a memLISTING 5PAD-CELL INSTANTIATION
examples show how you can
ory-controller design that
modify counter structure
translates host/CPU cycles
and behavior by using difinto memory cycles is unlikeferent values of generics and
ly to be instantiated multiple
constants while eliminating
times in a design. Such deunnecessary gates.
signs should use a package of
A deferred constant is one
constants. You should use
in which you declare but do
generics for designs such as
not initialize the constants
bus interfaces, counters,
in a package. Instead, you
adders, and linear-feedback
initialize the deferred conshift registers.
stants in the design that uses
TIP 3: GENERATE STATEMENTS
the constants. In other
words, you defer the bindYou can implement many
ing of the constants. You
digital systems, such as memmust bound deferred conories, as regular iterative comstants before you reference
positions of subsystems. For
them so that any change to
example, memories comprise
the package does not rerectangular arrays of storage
quire design-counter recells. Designers prefer such
compilation or resynthesis
implementations, because
LISTING 6REGISTER DESIGNED USING GENERATE STATEMENTS
(Listing 4).
they make it easier to produce
WITH ITERATIVE STRUCTURES
Using a package of concompact, proven, area-effistants has the same effect as
cient layouts, thus reducing
using generics modify struccost. If you can express a deture or behavior during synsign as a repetition of some
thesis. The package of consubsystem, you should be able
stants also allows you to
to describe the subsystem
effectively use composite
once and then describe how it
data types for readability
is to be repeatedly instantiatand still preserve design syned, rather than describe each
thesizability. Furthermore, it is easier to
instantiation individually (Reference 2).
synthesize a design that uses a package of
You can use generate statements to efLISTING 7SYNCHRONOUS OR COMBIconstants than one that uses generics. In
fectively produce iterative structures of
NATORIAL OUTPUT USING CONDITIONother words, it is easier for an engineer to
a design. Generate statements are conAL GENERATE STATEMENTS
learn how to get the synthesis tool to use
current VHDL constructs that may conthe package of constants than to use a detain further concurrent statements for
sign that uses generics. Some synthesis
replication. When you use generate Statetools have longer runtimes for designs
ments in conjunction with generics or
with composite data types.
constants, they can efficiently generate
You can use a package of constants in
repetitive structures. Consider a situation
much the same way that you use generin which you need to drive a 32-bit offics. Packages of constants are easier to use
chip data bus from on-chip using eight
than are generics if a lot of parameters
output enables through an output pad
are involved. Packages also typically have
(Listing 5). This example instantiates 32
better support of synthesis tools than do
pad cells for the data bus. Note the use
generics. However, using a package of
of the range and length attributes.
constants means that you cannot use
These attributes also promote reuse in
multiple instances of a design with dif- constants requires you to maintain a sep- that they use the previously defined bus
ferent parameters in a single design unit. arate file or library.
widths for the data bus. Also note the use
Instead, you need a unique entity and a
Compare using a package of constants of i/4 in the assignment of the outputunique package for each recurring design with using generics for parameterization enable signals to the pad cell. The synunit. Also, a change in a package that uses after considering the intended scope of thesis tool should be intelligent enough
nondeferred constants causes recompila- an application. As a general practice, use to truncate the division to an integer valtion or resynthesis of the designs refer- a package of constants for designs that ue to give to proper assignment of
ring the package even if a parameter does have many parameters and are not in- dataoe(3) to data(31:24), dataoe(2) to
not affect the design. Also, a package of stantiated multiple times within a large data(23:16), and so on.

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designfeature Generating reusable VHDL

Listing 6 illustrates the use of
generate statements with iterative
structures of concurrent statements to create a register from a
flip-flop. You can also use generate statements to conditionally
create, modify, or remove structures. This technique involves
code-level optimization, which
removes unwanted structures
during elaboration time. With
the use of generics or packages of
constants, this technique can be
useful in creating a reusable design.
Using conditional generate
statements, you can enable or disable logic that implements certain features instead of manually
removing the code or optimizing
via synthesis. As an example of
conditional code inclusion and
exclusion, you can synchronize
an output to the clock or combinatorially set it with the constant
CONSTANT SYNC_OUTPUTS :
BOOLEAN : TRUE; This technique lets you generate a synchronous or a combinatorial output (Listing 7).
The generate statement is a
powerful tool to control the inclusion or exclusion of logic. It is
useful for designs that repeatedly
use blocks of logic, such as flipflops, in an iterative structure.
These blocks form registers, pad
cells, and many other structures.
Many designers use generate
statements to instantiate cells, as
the pads example illustrates, but
you can also use generate statements to conditionally create,
modify, or remove sections of
VHDL code. Generate statements
are powerful tools promoting design reuse. A few more examples
that show the application of generate statements are choosing implementation of a latch-based or
flip-flop-based register; including
fixed, round-robin, or another
arbitration scheme in a bus-arbiter design; and including only
those bits of an interrupt controller that you know you are going to use. Consider the case in
which registered interrupts are
entering the interrupt controller.

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LISTING 8COUNTER WITH UNCONSTRAINED ARRAYS

FOR THE COUNT OUTPUT

LISTING 9INSTANTIATING THE COUNTER OF LISTING 8

IN A TOP-LEVEL ENTITY

LISTING 10BIT-WIDTH-INDEPENDENT IMPLEMENTATION

OF BINARY-CODE-TO-GRAY-CODE CONVERTER

LISTING 11CONVERTER WITH BUFFERED-COUNTER OUTPUTS

If these inputs go through a substantial amount of combinatorial

logic before being routed to other
registers, then the use of generate
statements to include only the
necessary flip-flops will help a
synthesis tool to significantly reduce the gate count. Be aware that
some synthesis tools cannot optimize across flip-flops. In these cases, even if we know that an input,
such as an unused interrupt, is always tied high, the synthesis tool
cant use this information to reduce the gate count of the synthesized design.
TIP 4: PORTS
In many instances, you can selectively disable logic by tying off
certain ports to default values.
When synthesized with a topdown approach, the synthesis tool
uses optimization by constant
propagationoptimizing that
path and taking into consideration that tied-off value. You can
later remove the tied-off ports
from the entity. Consider a threeAND-gate design (Figure 4a). If
you tie one of the inputs to a zero
(Figure 4b), then the resulting
logic eliminates all the AND gates
and the output, F, is always at logic 0.
a1: and3 port map (
a => a,
b => 0, Valid in
VHDL 93, Tied off to vss <=
0 in 87
c => c,
zo => zo
);
The same situation is true for
port outputs. By leaving unused
port outputs open (zo => open),
you can eliminate the logic that
creates these outputs when you
adopt a top-down synthesis approach.
TIP 5: UNCONSTRAINED ARRAYS
Using unconstrained arrays is a
helpful method of reusing designs
for variable-width implementations. You should be careful when
using attributes such as range
and length in the design to avoid
runtime and elaboration-time erwww.ednmag.com

designfeature Generating reusable VHDL

rors. Unconstrained arrays are
using unconstrained arrays to
LISTING 12TWO COUNTER INSTANCES INSTANTIATED
particularly suitable for adsupport efficient reuse.
IN A TOP-LEVEL ENTITY
dress, data, and register
TIP 6: VHDL ATTRIBUTES
widths. You can use these arrays for formal parameters in
A few attributes of composfunctions and procedures as
ite types are useful in creating
well as for entity ports.
reusable designs. The attribVHDL allows the use of unutes left, right, range,
constrained-array types that
length, low, and high are
let you indicate the type of insynthesizable and make the
dex values without specifying
code independent of data type.
the index bounds. UnconRefer to the examples using
strained arrays are useful for
unconstrained arrays (listings
making designs that you can
8 and 9), where the function
reuse in different applications
Gray2bin and the entity
just by modifying their bit
counter use the range attribwidths. The previous counter
ute to promote reusability.
example uses unconstrained
TIP 7: CONFIGURATION SPECS
arrays for the count output
(Listing 8). This technique
You use configuration speclets you connect the counter
ifications to bind component
entity to array signals of any
instances to design entities.
size or with any range of index
You can also use these configvalues. Note the use of the
urations to pass parameters
VHDL attribute range to
such as generics at the topLISTING 13COUNTER CONFIGURATION IN A TOP-LEVEL ENTITY
create a signal of the same
most level in a testbench, to sewidth and range specification
lect an architecture for an enas the port count. You cannot
tity, or to override port
synthesize this design by itself,
mappings in an instantiation.
and you have to instantiate it
Some synthesis tools do not
in a top-level entity to bind
support configuration specifithe array values to a finite
cations.
range (Listing 9). You must
Consider the previous
synthesize the code in Listing
counter example that illus9 in a top-down manner so
trates the use of generics for
that you can synthesize the
parameterization. Listing 11
counter along with the rest of
illustrates the same counter
the design.
with another architecture that
Another use of unconbuffers the counter outputs
strained arrays occurs in functions and makes efficient reuse possible. Listing 10 with a generate statement. The counter is
procedures. You should write functions is a bit-width-independent implementa- now instantiated in a top-level design usand procedures that you design for syn- tion for the binary-code-to-gray-code ing two instances of the counter (Listing
thesis as generically as possible, inde- converter. As another example, consider 12). A configuration specification conpendently of bit widths. Consider an ex- the functions and procedures in the IEEE figures the counter in the entity top, as
ample of a binary-code-to-gray-code std_logic libraries. Most of these func- shown in Listing 13. Configuration specconverter. To create a gray code from a bi- tions and procedures are implemented ifications let you configure various levnary code, use the algorithm in Figure
els of the designs hierarchy.
TABLE 1GRAY CODES CORRESPONDING
5a. Figure 5b is an example of how to
TIP 8: BLOCK STATEMENTS
TO 3-BIT BINARY CODES
convert binary 100 to its gray-code
Binary
Gray
Block statements are VHDL constructs
equivalent of 110. Table 1 shows the gray
000
000
that allow inline design partitioning. For
codes for the 3-bit binary values that the
001
001
example, if you partition a design such
algorithm of Figure 5a creates. You hard010
011
that the datapath exists in a separate
code and optimize this algorithm for a 3011
010
VHDL entity, then you can partition the
bit case. When the design has to accom100
110
architecture for that entity using block
modate more counts, the function has to
101
111
statements. Block statements are a
change, requiring you to revalidate all the
110
101
method of grouping related logic. Block
logic. Writing a generic function that is
111
100
statements also provide the ability to deindependent of the bit-vector lengths

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designfeature Generating reusable VHDL

clare signals within the blocks and, if you
remove the block, unnecessary signals do
not remain unconnected in the code. You
can combine a generate statement with
the block statement to selectively include
or exclude blocks.
TIP 9: UNUSED PORTS
In a hierarchical design, if you do not
use certain ports in an entity, then the
usual practice is to connect them to a
dummy signal. From a top-down synthesis approach, this scenario makes the
synthesizer assume that youve connected the signal to a net. You can avoid this
problem by leaving the port unconnected or by specifying with the VHDL keyword open.
TIP 10: PREPROCESSORS
In many situations, designers cannot
accomplish what they want using the
available features. In some cases, it is desirable to see only the code that is relevant to the design. In such cases, you can
use a preprocessor to add, eliminate, or

modify code for a specific application,

through the use of preprocessor directives.
References
1. Meiyappan, Subbu, and Peter
Chambers, Design Reuse Using Scripting Methodologies, DesignCon98, OnChip System Design Conference, pg 629.
2. Ashenden, PJ, The Designers Guide
to VHDL, Morgan Kaufman Publishers,
San Francisco, CA, 1996.
3. Smith, Douglas J, HDL Chip Design,
Doone Publications, Madison, AL, 1996,
ISBN 0-9651934-3-8.
Authors bio graphies
Subbu Meiyappan is a senior design engineer at VLSI Technology. He has worked
for the company for nearly three years, designing, developing, synthesizing,simulating, and validating high-performance IP
blocks for PCI, ARM-ASB-based devices,
and high-performance ASICs. He has a BE
from Annamalai University (Annamalai
Nagar, India) and an MS from Tennessee

Technological University (Cookeville, TN).

His interests include computer architecture, design automation, volleyball, and
travel.
Ken Jaramillo is a staff engineer at VLSI
Technology. In his three years with the
company, he has worked on high-speed
networking designs, such as fiber-distributed data interfaces, Firewire, and highspeed satellite modems. He has a BSEE
from the University of Missouri (Kansas
City, MO) and a BSCoE from the University of Missouri (Columbia, MO). His hobbies include basketball, rock climbing, and
travel.
Peter Chambers is an engineering fellow at
VLSI Technology, where he has worked for
six years developing many PCI-based designs, ASICs, chip sets, and reusable IP
cores. He has a BS from the University of
Exeter (UK) and an MS from Arizona
State University (Tempe, AZ). He is a
member of both IEE and IEEE.

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