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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm


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ISSN 2321-5984

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Volume 2, Issue 10, October 2014

Design of XNOR Gate Using SET based Linear


Threshold Gate
N. Basanta Singh
Department of Electronics and Communication Engineering,
Manipur Institute of Technology, Imphal-795004, India

ABSTRACT
Single electron devices have ultra-low power consumption and high integration density, which make them promising
candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits. In this paper, the design of twoinput XNOR gate using single-electron tunneling based linear threshold gate is presented for the first time. The logic operation
of the gate is simulated and verified using Monte Carlo simulation. Free energy history and stability analysis have verified the
correct functioning of the gate.

Keywords: Single electron tunneling, Threshold logic gate, Tunnel Junction, XNOR gate

1. INTRODUCTION
There have been reports suggesting that the CMOS transistor cannot shrunk beyond certain limits dictated by its
operating principle [1,2]. Over recent years this realization has led to exploration of possible successor technologies
with greater scaling potential such as quantum and single electronics for the next generation VLSI/ULSI circuits. The
Single Electron Tunneling (SET) technology is one of the most promising future technologies to meet the required
increase in density, performance and decrease in power dissipation [3]-[8]. The ultimate limit in the operation of an
electronic device is the manipulation of a single charge. Such a limit can be achieved in single-electron tunnelling
devices. While the prospect of CMOS devices being completely replaced by SET devices remains to be seen, SET
devices and circuits have received tremendous attention in the research community. Traditional digital logic circuits
have been implemented by representing Boolean functions as a network of AND, OR and NOT logic gates. The
performance of Boolean implementation might be severely affected by a large circuit depth and alternative solutions are
required. A potential alternative to Boolean Logic is the Threshold Logic [6]. For example, each of the Boolean
functions ab(c+d)+cd(a+b) and a(b+c+d)+b(c+d) + cd, can be realized by a single threshold gate. Thus a Boolean
function, if realized as a network of threshold gates, can result in significantly fewer nodes and smaller network depth.
A number of investigations have been reported regarding the possibilities of threshold logic gate (TLG) based design
and implementations of useful Boolean functions [9]-[14]. In this work, design and simulation of XNOR gate using
SET based threshold logic gate is presented. The logic operation of the gate is simulated and verified using SIMON
which is a single-electron circuit simulator based on Monte Carlo method. Free energy history diagram and stability
analysis have been conducted to verify the correct functioning of the gate.

2.

THEORY

The tunnel junction which is the basic component of single electron tunnelling technology can be considered as two
conductors separated by a thin layer of insulating material. A tunnel junction and its schematic diagram are shown in
Fig. 1. It is characterised by a resistance Rj and a capacitance Cj, each of which depends on the physical size of the
tunnel junction and the thickness of the insulator.

Fig. 1 Schematic Structure and Symbol of Tunnel Junction

The fundamental principle of SET devices and circuits is the Coulomb blockade, which was first observed and studied
by Gorter [15]. The transport of electron through a tunnel junction is called tunnelling. Electrons are considered to

Volume 2, Issue 10, October 2014

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IPASJ International Journal of Electronics & Communication (IIJEC)


Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
Email: editoriijec@ipasj.org
ISSN 2321-5984

A Publisher for Research Motivation........

Volume 2, Issue 10, October 2014

tunnel through a tunnel junction one after another [7], [8], [16]. Even only one electron tunneling may produce a
voltage e/C across the tunnel junction (where C is total capacitance and e = electronics charge = 1.602 x 10-19 C).
According to orthodox theory [17], [18] the critical voltage Vc, which is the minimum voltage across the tunnel
junction to make an electron tunnel possible can be calculated as

Vc

e
2(Ce C j )

(1)

Where e=1.602x10-19C, Cj is the tunnel junction capacitance and Ce is the equivalent capacitance for remainder circuit
as viewed from the tunnel junctions perspective. Tunnel event will occur across the tunnel junction if and only if the
voltage Vj across the tunnel junction is greater than or equal to Vc i.e Vj Vc, otherwise the tunnel event cannot occur.
This phenomenon is also called Coulomb blockade. The circuit will be in stable state if Vj Vc.
2.1 Threshold Logic Gate
A threshold logic gate is a device which is able to compute any linearly separable Boolean function given by

0 if F ( X ) 0
Y sgn{ F ( X )}
(2)
1 if F ( X ) 0
n
where F ( X ) i 1 wi xi T , xi are the n Boolean inputs and i are the corresponding n integer weights.

Fig. 2 TLG symbol

The gate symbol of the threshold logic gate is shown in Fig. 2. The TLG performs a comparison between the weighted
sum of inputs

i 1 wi xi

and the threshold value T. If the weighted sum of inputs is greater than or equal to the

threshold, the gate produces logic 1 at the output; otherwise output is logic 0. A generic SET-based threshold logic gate
proposed by C. Lageweg et al [8] is shown in Fig. 3.

Fig. 3 Generic SET-based TLG

The input voltages Vp weighted by their input capacitances Cp are added to Vj and the input voltages Vn weighted by
their input capacitances Cn are subtracted from Vj. The critical voltage Vc of the tunnel junction which can be adjusted
by the bias voltage Vb weighted by Cb acts as the threshold value. The function F(X)/ for the circuit is given by [ 8, 19]

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IPASJ International Journal of Electronics & Communication (IIJEC)


Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
Email: editoriijec@ipasj.org
ISSN 2321-5984

A Publisher for Research Motivation........

Volume 2, Issue 10, October 2014


r

F ( X ) / C n k 1 C KP V KP C P l 1 C lnVl n T /

(3)

where
T/

1
(C p C n ) C n C bV b
2
r

C p C b k 1 C kp

(4)
(5)

C n C o l 1 C ln

(6)

Detailed derivation of the above equations can be found in [20]. This gate is able to implement certain Boolean
function if the involved parameters are chosen properly. It was proposed that [8], [19] a SET buffer/inverter depicted
in Fig. 4 should follow the threshold logic structure to provide enough driving ability and stability. Since the
buffer/inverter inverts the output of the original threshold logic, we need to reverse the positively and negatively
weighted inputs in the logic function accordingly. When combining a logic gate with buffer/inverter with circuit
parameters given in [8], the buffer adds an additional capacitive load to the logic gates output node. The buffers
supply voltage and output voltage change the logic gates biasing due to a feedback effect. This effect is accounted for
n
by considering an additional negatively weighted input Vbuff
capacitively coupled to the threshold gate with an input
n
n
n
capacitance C buff
and the threshold value of each threshold gates must be adjusted by Vbuff
C buff
C p .

Fig. 4 SET Buffer/Inverter

3. DESIGN OF XNOR GATE


In Boolean logic, the logic function of two-input XNOR can be expressed as

Y A B AB
(7)
A Boolean gate-based implementation of XNOR gate costs five gates and would result in a logic network with a depth
of three. The XNOR gate can be realized using only two threshold logic gates and a network depth of two as shown in
Fig 5. The threshold equations for the XNOR gate can be written as
Y / sgn{ A B 0.5}
(8)
and
Y sgn{ A B 2Y / 1.5}

(9)

Fig. 5 XNOR Gate using TLG

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IPASJ International Journal of Electronics & Communication (IIJEC)


A Publisher for Research Motivation........

Volume 2, Issue 10, October 2014

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Email: editoriijec@ipasj.org
ISSN 2321-5984

A buffered version of the SET-based threshold logic XNOR gate implementation which consists of two buffered TLG is
shown in Fig. 6. Threshold logic expression for the buffered version can be written as
Y / sgn{ A B 0.5}
(10)
and
Y sgn{ A B 2Y / 1.5}

(11)

SET based TLG circuit to implement (10) and (11) is shown in Fig. 7.

Fig. 6 XNOR Gate using buffered TLG

Fig. 7 2-input XNOR Gate using SET- based TLG

To determine the parameter values of TLG1 and TLG2, we assume the following voltage levels: Logic 0=0 V, Logic 1=
0.1e/C=16 mV, Rj=100K and Cj=0.1C, where C=1aF is used as a unit of capacitance. For the buffer/inverter, circuit
parameters values are taken from [8]. Comparing (3) and (10), we obtained the following relation for the weights of
TLG1:
C n C1p C n C 2p

(12)

Given the choice of logic level 1, we want the change in output voltage due to transport of an electron to be equal to
0.1e/C. The change in output voltage due to transport of an electron in the arrows direction in the generic SET-based
TLG is given by [20]

dV0 eCp C

(13)

C C p C n C p C j C n C j

(14)

where
We assume C j C p and C j C n to ensure that a large percentage of the input voltages are applied over the
tunnel junction due to capacitive division and (14) reduces to

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IPASJ International Journal of Electronics & Communication (IIJEC)


Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
Email: editoriijec@ipasj.org
ISSN 2321-5984

A Publisher for Research Motivation........

Volume 2, Issue 10, October 2014


C Cp C n
dV0

eC p

C e

For a buffered

C n

0.1e C

TLG1, C n

(15)
C n

10C

C0 1C , therefore C 0 9C . We also assume input capacitors which are small compared to

C n in order to limit the capacitive division effect of the inputs on the output.

By choosing C1p C2p 0.5C and

Vb 16mV , we now have Cb to be the only parameter to be determined with its value depending on the specific
threshold logic expression. From the threshold equation of TLG1 it is clear that when A is at logic 1, it contributes 1 to
the weighted sum of the gate inputs. The same is true for input B. If we now apply logic 1 (i.e 0.1e/C V) to both the
inputs of the TLG1, (3) becomes
r

F ( X ) / C n k 1 C KP V KP C P l 1 C ln V l n T

10C[0.5C 0.1e / C 0.5C 0.1e / C T / ]

0.5eC 0.5eC T / T /
Applying logic 1 to any of the inputs of TLG1 translate into a contribution of =0.5eC. Therefore act as a scaling
factor and T should also be scaled by i.e T / T 0.5.0.5eC 0.25eC . With adjustment for buffered TLG, the new
threshold value is given by 0.25eC 0.046eC p and substituting this value in (4), we get
0.25eC 0.046eC p e(C n C p ) 2 C n C bVb

(16)

From (16), the value of Cb is obtained as 11.7C. Following the same procedure, the following parameters are obtained
for the buffered TLG2: C1n 1C , C 2n C 3n 0.5C , Vb 16mV , C b 13.19C , C 0 7C , R j 100 K and
C j 0.1C .

4. SIMULATION RESULTS AND ANALYSIS


The performance of the proposed two-input XNOR gate is simulated using Monte Carlo simulation software SIMON2
[18], [21]. Fig. 8 shows the XNOR circuit simulated using SIMON. All the possible combination of the inputs (A and
B) and the output (Y) of the gate is depicted in Fig. 9. The results obtained from the simulation are found to be
satisfactory. The stability of a single-electron circuit is studied by constructing its free energy history diagrams and its
stability plots. Fig. 10 shows the free energy history when electron is transported from the output node N2 to Vs through
J1 and J2, leaving a positive charge in N2 and changing the value of the output from 0 to 1. Initially there is no charge
in N2 and the free energy is zero. During the second time step, an electron is transported from island N2 to island N1
through J2 and the free energy increases. During the third time step, the electron is transported from island N1 to Vs
through J1 and there is significant decrease in free energy. At this point the output N2 is positively charged and we
have a transition from 0 to 1. Both logic 0 and logic 1 states correspond to energy minima. This is a strong indication
of gate stability.

Fig. 8 XNOR Gate simulation using SIMON

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IPASJ International Journal of Electronics & Communication (IIJEC)


A Publisher for Research Motivation........

Volume 2, Issue 10, October 2014

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm


Email: editoriijec@ipasj.org
ISSN 2321-5984

Fig. 9 Simulation results of XNOR gate

Fig. 10 Free energy history diagram

To confirm the stable operation of the single-electron circuit, its stability plots have been constructed using SIMON2
and shown in Fig. 11. White regions in the figure are stable regions and black regions correspond to completely
unstable gate operation. The gray regions correspond to less unstable regions. Points a d correspond to input vectors
[0 0], [0 1], [1 0] and [1 1], respectively. All the 4 possible combinations of the inputs are located into stable regions,
i.e. in white, which are stable enough to allow the desired operation of the XNOR circuit.

Fig. 11 Stability plot

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IPASJ International Journal of Electronics & Communication (IIJEC)


A Publisher for Research Motivation........

Volume 2, Issue 10, October 2014

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm


Email: editoriijec@ipasj.org
ISSN 2321-5984

5. CONCLUSION
The design, simulation and stability analysis XNOR gate using SET-based TLG is presented. The performance of the
proposed gate is verified by simulation using SIMON 2. The free energy history diagram and stability plot of the gate
shows that the circuit presented in this paper operates in the stable regions thereby establishing the scope for using the
proposed circuit in future ultra-dense VLSI/ULSI circuits.

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