VLSI TESTING

Presented by,
Sriram Sundar S
Assistant Professor, Department of E.C.E

VERY LARGE SCALE INTEGRATION

Who invented the First integrated Circuit?
In 1958, Jack Kilby built the first integrated circuit flip-flop with
two transistors at Texas Instruments.
Very-large-scale-integration (VLSI) is defined as a technology
that allows the construction and interconnection of large
numbers (more than millions) of transistors on a single
integrated circuit.

PRIMARY CONSTRAINTS FOR

DESIGNING AN INTEGRATED CIRCUIT
1. Area
2. Speed
3. Power Consumption
First monolithic IC
Intel 4004 invented in 1971. It contains 2,300 pMOS
transistors. The Intel 4004 had a feature size of 10m,
CPU speed of 740KHz
The Core 2 Duo had a feature size of 45nm, CPU speed of
1.06 GHz to 3.5 GHz and Maximum TDP of 130W.
In 2008, Intels Itanium microprocessor contained more
than 2 billion transistors and a 16Gb Flash memory
contained more than 4 billion transistors.
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NUMBER OF TRANSISTORS IN INTEL

MICROPROCESSORS

PROCESS GENERATIONS IN INTEL

MICROPROCESSORS

DEVELOPMENT OF INTEGRATION
TECHNOLOGY
Moores Law: (Gordon Moore -1965)
The number of transistors per chip would doubled for
every 18 to 24 months.
Does Moores law exists?
Dennard scaling: (Robert Dennard - 1974)
If there was a reduction in a transistors linear size by 2, the
power it used fell by 4 (with voltage and current both
halving).
The end of Dennard scaling
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VLSI DESIGN FLOW

VERIFICATION VS. TESTING

Design Verication:
Predictive analysis to ensure that the synthesized design, when manufactured, will
perform the given I/O function.

Test:
A process that ensures that the physical device, manufactured from the synthesized
design, has no manufacturing defects.
Verification

Testing

Verifies correctness of design.

Verifies correctness of manufactured

hardware

Performed by simulation, hardware

emulation, or formal methods.

Electrical tests applied to hardware

Performed once prior to manufacturing.

Test application performed on every

manufactured device.

Responsible for quality of design.

Responsible for quality of devices.

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PHILOSOPHY OF TESTING
Murphy's Law
If anything can go wrong, it will
To ensure that only fault free systems are delivered,
before deploying any system in the field or shipping a product to
a customer, it needs to be Tested.

NEED FOR TESTING

2000 International Technology Roadmap for Semiconductors (by
the Semiconductor Industry Association - SEMATECH) predicts
by 2014:
Test machines will cost more than $20M each!!!
It will cost more to test a transistor than to manufacture it!!!

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TESTING COST
Costs increase dramatically as faulty components find their way
into higher levels of integration
$10.00 to find and replace bad IC on a PC board
$100.00 to find bad PC board in a system
$1000.00 to find bad component in fielded system

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TYPES OF TESTING
Prototype test
Testing to check for design faults during the
development phase. Diagnosis is required for this test.

system

Production test
Testing of individual product to check whether faults are
introduced during the manufacturing phase. It is assumed that
the design is correct.
System test
Testing of the product in the environment where it is operating
to ensure that it works correctly when interconnected with other
components.
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CASE STUDY FOR A POOR TESTING

Pentium FDIV bug
A bug in the Intel P5 Pentium floating point unit (FPU)
In June 1994, Intel discovered the flaw in floating-point math
subsection. Under certain data-dependent conditions, the loworder bits of the result of a floating-point division would be
incorrect.
In October 1994, Dr. Thomas Nicely, Professor of Mathematics at
Lynchburg College, independently discovered the bug.
Intel offered to replace every chip, in a $500 million charge
against Intel's 1994 revenue.
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IS FUNCTIONALITY TESTING
ENOUGH?
Example: Testing an electric iron in 220V AC
Test for heating is just verifying its functionality, that too
partially.
1. Safety
2. Detailed Functionality
3. Performance
Mechanical parameters

Testing a system comprises subjecting it to inputs and

checking its outputs to verify whether it behaves as per the
specifications targeted during design.
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TESTING OF A NAND GATE

Digital Functionality
Delay Test
Fan-out capability
Power consumption of the gate
Static power
Dynamic power
Threshold Level
Switching noise

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TESTING OF A NAND GATE

TRANSISTOR LEVEL

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TESTING OF A NMOS TRANSISTOR

Output Characteristics
a set of IDS vs VDS curves for different constant values of
VGS
Transfer characteristics
a set of IDS vs VGS curves for different constant values of
VDS
Threshold Voltage Test
Threshold Voltage obtained in test, matches the
specifications

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ROLE OF TESTING
If you design a product, fabricate, and test it, and it fails
the test, then there must be a cause for the failure
1.
2.
3.
4.

Test was wrong

The fabrication process was faulty
The design was incorrect
The specification problem

The role of testing is to detect whether something went

wrong and the role of diagnosis is to determine exactly
what went wrong

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HOW TO TEST CHIPS?

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FAULTS AND FAILURE

Failure
a logic circuit or system if it deviates from its specified
behaviour.
Fault
a physical defect in a circuit

However, a fault does not always cause an error; in that case,

the fault is considered to be hidden.

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TYPES OF FAULTS
The nature of a fault can be classified as logical or nonlogical.
A logical fault causes the logic value at a point in a circuit to
become opposite to the specified value. Nonlogical faults
include the rest of the faults such as the malfunction of the
clock signal, power failure, etc.

Stuck-At Fault
Stuck Open Fault
Bridging Faults
Delay Faults

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STUCK-AT FAULT

It assumes that a fault in a logic gate results in one of its

inputs or the output is Fixed at either a logic 0 (stuck-at-0) or
at logic 1 (stuck-at-1). Stuck-at-0 and stuck-at-l faults are often
abbreviated to s-a-0 and s-a-1, respectively.

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STUCK-AT FAULT (CONT..)

If A=0 and B=1, Z=?

Fault is detectable for this input combination
If A=0 and B=0, Z=?
Fault is hidden

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STUCK-OPEN FAULT
A single physical line in the circuit is broken is called stuckopen fault.
The resulting unconnected node is not tied to either Vcc or
Ground
VDD
A

B
Line Break

VSS

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BRIDGING FAULTS
When two or more signal lines in a circuit are accidentally
connected together.
Bridging faults has been classified into two types:
Input bridging
Feedback bridging.
An input bridging fault corresponds to the shorting of a
certain number of primary input lines.
A feedback bridging fault results if there is a short between an
output and input line. A feedback bridging fault may cause a
circuit to oscillate, or it may convert it into a sequential circuit.

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BRIDGING FAULTS (CONT..)

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DELAY FAULTS
The logic function of the circuit-under-test is error free. Some
physical defect, such as process variations, etc., makes some
delays in the circuit-under-test greater than some defined
bounds.
Two types of delay faults
Gate delay fault
Path delay fault.

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BASIC CONCEPTS OF FAULT

DETECTION
Fault detection in a logic circuit is carried out by applying a
sequence of tests and observing the resulting outputs. If the
observed response is different from the expected response, a
fault is present in the circuit

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CONTROLLABILITY
This ability to apply input patterns to the primary inputs of a
circuit to set up appropriate logic value at desired locations of
a circuit is known as controllability.

In the presence of a stuck-at-0 fault, the location of the fault

must be set to logic 1 via the primary inputs; this is known as
1-controllability.
Similarly, for a stuck-at-1 fault, the location of the fault must
be set to logic 0 via the primary; this is known as 0controllability

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OBSERVABILITY

The effect of the stuck-at-1 fault can observed at output Z if

input d is set at 1; if d is set to 0, the output will be 0 and the
effect of the fault will be masked (i.e., the fault will not be
detected).
The ability to observe the response of a fault on an internal
node via the primary outputs of a circuit is denoted as
observability.
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DESIGN FOR TESTABILITY (DFT)

Design for testability refers to how a circuit is either designed
or modified, so that the testing of the circuit is simplified.

DFT can be categorized into :

Ad hoc
Structured or Scan-path Design
The ad hoc approaches simplify the testing problem for a
specific design and cannot be generalized to all designs.
On the other hand, the structured techniques are generally
applicable to all designs.
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DFT (CONT..)
Ad hoc technique
One of the simplest ways of improving the testability of a
circuit is to provide more tests and control points.
Test points are, in general, used to observe the response at a
node inside the circuit.
Control points are utilized to control the value of an internal
node to any desired value, 0 or 1.
Scan-path Design
The testing of sequential circuits is complicated because of the
difficulties in setting and checking the states of the memory
elements.
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TEST PATTERN GENERATION

Manual Stimulus test patterns
Very expensive.
Intel Pentium microprocessor took 50 man years
An Automated Test Pattern Generation (ATPG) tool
automatically generates test patterns by using a model of the
gates and the interconnection of the gates and a model of the
potential faults.

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TEST PATTERN GENERATION

TECHNIQUES
Exhaustive generation
Pseudoexhaustive generation
Deterministic generation
Pseudorandom pattern generation

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EXHAUSTIVE GENERATION
All possible input patterns are applied to the circuit under test.
Thus n-input combinational logic circuit, all possible 2*n
patterns need to be applied.
The test patterns are generated by binary counters or complete
LFSR.

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PSEUDOEXHAUSTIVE
GENERATION
A combinational
circuit
with
n
inputs
can
be
pseudoexhaustively tested with 2*n or fewer binary patters if
none of the circuit is a function of more than w out of n inputs.
In general, the pseudo-exhaustive patterns needed to test an n
input and m output combinational circuit are derived by using
one of the following methods.

Constant weight counter

Linear feedback shift register/shift register

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PSEUDORANDOM GENERATION
Pseudorandom patterns are sufficiently random in nature to
replace truly random sequence. LFSRs are widely used to for
generating test patterns for combinational circuits because an
LFSR is easy to implement.

The Pseudorandom generation can be applied in two different

methods:
Weighted method
Adaptive method

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PSEUDORANDOM GENERATION
(CONT..)

Drawbacks
Low fault coverage
Area overhead and Additional delay
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AUTOMATIC TEST EQUIPMENT

External Testing Methodology
Control processor
Timing module
Power module

ADVENTEST Model T6682 ATE

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ATE TEST OPERATION

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DRAWBACKS OF EXTERNAL
TESTING
ATE are expensive (typically several million US$)
Increase of test application time
Increase of test data volume

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BUILT-IN SELF-TEST
BIST is a design technique in which parts of a circuit are used to
test the circuit itself.
Built-in self-test (BIST) significantly reduces off-chip
communication by accommodating test
generation and
response evaluation hardware on the chip.

Test Generator

BIST
Controller

Circuit Under Test

(CUT)

Response Analyzer
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BIST TECHNIQUES
Off-Line BIST (Test Mode)
On-Line BIST (Normal Operation mode)
Concurrent
Nonconcurrent

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BIST BENEFITS AND DRAWBACKS

BIST benefits
Reduced testing and maintenance cost
Reduced storage/maintenance of test patterns

Simpler and less expensive ATE

Drawbacks of BIST
Additional pins and silicon area needed
Performance impact due to additional circuitry

Additional design time and cost

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MEMORY TEST
Developments in semiconductor memories is increasing the
density of memory chips. The number of bits per chip

quadrupled every 3.1 years.

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TESTING ALGORITHMS FOR RAM

GALPAT (Galloping 0s and 1s )
Walking 0s and 1s
March Test

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GALPAT
The cells are Initialize to 0 and reference address is selected
and is content is changed from 0 to 1.
Next another location is accessed and to check if its content is
0.
Read and verification operation is continued for all locations.
Reference is location is accessed again and write to 0 and
other locations are changed to 1.

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WALKING 0s AND 1s

Initialize all memory location to 0.

1 is written in selected reference node.
All other locations verified in sequence manner for 0.
0 is written in selected reference cell and 1 in another
location as reference

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MARCH TEST

Initialize the memory location to 0.

Check all the Cells if it contains 0s in ascending order.
Initialize the memory location to 1.
Check all the Cells if it contains 1s in descending order.

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TAXONOMY OF DIGITAL TESTING

TAXONOMY OF DIGITAL
TESTING

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THANKS

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