Vol. 34, No.

Journal of Semiconductors

May 2013

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical

Gaussian-like doping profile
Sarvesh Dubey1 , Pramod Kumar Tiwari2 , and S. Jit1;
1 Department
2 Department

of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi-221005, India

of Electronics and Communication Engineering, National Institute of Technology Rourkela-769008, India

Abstract: An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a
Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and saturation regions of device operation. The drain current variation with various device parameters has been demonstrated.
The model is made more physical by incorporating the channel length modulation effect. Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been
formulated. The model results are validated by numerical simulation results obtained by using the commercially
available ATLASTM , a two dimensional device simulator from SILVACO.
Key words: drain current; DG MOSFET; transconductance; drain conductance
DOI: 10.1088/1674-4926/34/5/054001
EEACC: 2570

1. Introduction
The relentless advancements of electronics, information
technology (IT) and communications have been driven primarily by the exponential improvement in the CMOS technology1 . As CMOS scaling is approaching the limit imposed
by the severe presence of unavoidable short-channel effects
(SCEs), an alternative structure of the conventional MOSFET
is being sought. Double-gate (DG) MOSFETs are found to be
amenable to scaling compared with the conventional MOSFETs because of their capability to be scaled up to the very
shortest channel length possible for a given gate-oxide thickness2; 3 . In addition to the inherent property of suppressing
SCEs and steep subthreshold slope, DG MOSFETs offer high
drive current and transconductance attributed to the two channel property of the symmetrical DG device. Thus modeling the
drain current of the DG MOSFET becomes requisite because
it provides the fundamental skeleton for a circuit simulator and
also it is essential to get the physical insight4 .
Drain current models have been developed for undoped5 11 and doped short-channel DG MOSFETs13 18 .
Suzuki et al.5 proposed a lightly doped nC pC DG SOI
MOSFET having two threshold voltages related to nC and pC
polysilicon for the back and front gates respectively. Considering charge-sheet approximation, they5 derived a drain current
model in strong inversion and demonstrated high speed operation of the device. The current model5 neglected the shortchannel effects and regarded the device as long-channel even
for 0.1 m gate length. Taur et al.6 presented a continuous
analytic current model for undoped long-channel DG MOSFETs. They6 derived the currentvoltage (I V / characteristics in all the regimes of device operation from closed-form solutions of the Poissons equation and current continuity equation without the charge-sheet approximation. Hariharan et al.7
presented a drain current model for a short-channel symmetric
DG MOSFET. The channel region was kept undoped/lightly

doped. The inversion-charge density was used for modeling

the drain current in a strong inversion region under the drift
diffusion transport mechanism. The variation of transconductance and drain conductance has also been shown against gateto-source and drain-to-source voltages respectively. Reyboz et
al.8 reported a continuous and compact current model of an
undoped independent DG MOSFET. In addition, they8 also
reported an empirical model for mobility degradation owing to
transverse electric field and a velocity saturation model as well.
Their8 model was valid for long-channel as well as shortchannel devices. At the gate length of 30 nm, a good match was
observed between numerical simulation results and model results of drain current, transconductance and drain conductance.
Mohammadi et al.9 have presented a semi-analytical model
for the I V characteristics of nanoscale undoped symmetric
DG MOSFETs. The model employed a parabolic potential approximation for estimating the body potential normal to the interfaces in all the regions of device operation. The inversioncharge density approach in addition to the carrier confinement
phenomenon was taken into account. Ioannidis et al.10 gave
an analytical model for the transconductance to current ratio
.gm /ID / of a nanoscale DG MOSFET with lightly doped channel. The model incorporated the surface roughness scattering
and velocity saturation effects and was valid from weak inversion to saturation region of device operation. In terms of
device parameters, there was good agreement between model
results and numerical simulation results. Recently, Papathanasiou et al.11 have presented an explicit charge-based unified
compact drain current model for lightly doped or undoped DG
MOSFETs. The model has taken into account the short-channel
effects, the subthreshold slope degradation, the drain-induced
barrier lowering and the channel length modulation effects in
all regimes of device operation. The mobile charge density is
described by a unified Lambert W function which is valid from
weak to strong inversion. An average error of about 3% is reported between the model results of transfer and output charac-

Corresponding author. Email: sjit.ece@itbhu.ac.in

Received 4 October 2012, revised manuscript received 14 November 2012

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J. Semicond. 2013, 34(5)

Sarvesh Dubey et al.

teristics with simulation results. The gm /ID ratio has also been
examined from the modeled transfer characteristics in order to
give an insight into the efficiency of the proposed structure.
The models discussed so far are valid for undoped DG MOSFETs. It should be noted that without using the body doping as
a tool for adjusting the threshold voltage, undoped DG MOSFETs need to rely on gate work function for achieving multiple threshold voltages on a chip, which imposes a technological
hurdle12 . Besides this, memory cell applications in DG MOSFETs require a doped body13 . From this viewpoint a number
of authors have proposed a drain current model for doped DG
MOSFETs13 18 . Kranti et al.14 presented an analytical drain
current model for long-channel graded channel (GC) DG SOI
MOSFETs. Their analysis was based on charge-sheet approximation. Based on their14 modeling, 2D simulation and experimental results, they showed that DG MOSFETs with laterally asymmetric channel engineering can achieve high values
of saturation drain current. They also compared their results
of GC DG MOSFETs with experimental and simulated data
of uniformly doped DG and single gate (SG) SOI MOSFETs.
The analysis took into account the effect of length and doping
of the high and low doped regions to develop a compact model
suitable for device design. Moldovan et al.15 presented an analytical and continuous model for a highly doped long-channel
DG SOI MOSFET. Valid from below to well above threshold, a unified charge control model was derived. The channel current was expressed as an explicit function of the applied
voltages targeting baseband analog circuits. However, the dependency of drain current on channel doping was not demonstrated. Cerderia et al.16 derived a compact current model of
symmetric short-channel DG MOSFETs. The channel doping
was considered in the range of concentrations between 1014
and 3  1018 cm 3 . The mobile charge density was calculated
using the difference of potentials at the surface and at the center of the Si doped channel. They16 performed the variation
of the transfer and output characteristics as a function of channel doping and other device parameters in linear and saturation
regions. Choi et al.17 presented a drain current model of fully
depleted (FD) short-channel symmetric DG MOSFETs with
doped silicon body. The model furnished a continuous simple
closed-form expression of drain current in all operational regions. The parabolic approximation was used to estimate the
channel potential. The drain current modeling was divided into
subthreshold current and strong inversion current. In strong inversion, the drift current of doped DG MOSFETs was modeled
by considering inversion-layer capacitance based on chargesheet approximation. However, the model used a fitting parameter () providing nearly analytic results. The channel doping
concentration was considered up to 1  1019 cm 3 . The surface potential based continuous drain current model for doped
DG MOSFETs was reported by Jin et al.13 . They13 considered a wide range of doping concentration. The total current
model consisting of both drift and diffusion components was
compared with simulation results and showed very good agreement in subthreshold, linear and saturation regions at different
body doping concentrations. An equivalent thickness concept
based model depending on channel doping concentration of
doped DG MOSFET was proposed by Sallese et al.18 . Valid
for relatively high doping, equivalent thickness is further used
to calculate the mobile charge density and drain current of the

Fig. 1. Schematic diagram of a DG MOSFET. L, tsi and tox are the

channel length, channel thickness and oxide thickness, respectively.

device for all operation regions. However, maintaining uniformity of dopants throughout the channel region is not an easy
task because, during many of the fabrication stages like diffusion and threshold adjust implantation, the doping profile becomes nonuniform in the practical MOS devices12 . Further,
the ion implantation provides a Gaussian profile for the doping
distribution in the doping region of any device12 . Therefore,
a drain current model for Gaussian doped DG MOSFET especially in linear and saturation regions of device operation is
needed.
In the present work, for the first time, an analytical drain
current model for short-channel DG MOSFETs with Gaussianlike doping profile in the vertical direction of the channel has
been presented. The drain currents in linear and saturation region are obtained by calculating the charge densities in the
channel region. The analysis has been extended to obtain the
expressions for transconductance and drain conductance. It
should be noted that to make the model fully analytical in nature, the actual Gaussian function has been replaced by an approximate Gaussian-like function19 . The present work may
be seen as the continuation of our previous works12; 20; 21 on
Gaussian doped DG MOSFETs. A 2D device simulator, ATLASTM , has been used to validate the model results22 .

2. Model formulation
The schematic structure of the DG MOSFET used for the
drain current and simulation is shown in Fig. 1 where, the notations L, tsi and tox are the channel length, silicon film thickness
and gate oxide thickness of the device, respectively. The x- and
y-axes of the 2D structure are taken along the source-channel
interface and center of the channel respectively, as shown in
the figure. The Gaussian-like doping profile19 , say Nb .x/, is
considered in the vertical direction of the channel:
h
i


Nb .x/ D Np c .a C 2bX/2 2b exp aX bX 2 ;
(1)
x Rp
p
where X D
, Rp is the projected range, p being the strag2p

gle of the Gaussian profile; Np is the peak doping concentration

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J. Semicond. 2013, 34(5)

Sarvesh Dubey et al.

at x D Rp ; a, b and c are the fitting constants having values

a D 1:786, b D 0:646 and c D 0:56; D C1 for x > 0 and
1 for x < 0, involved in the Gaussian-like function.
2.1. IV formulation
In the above-threshold regime of device operation, the
currentvoltage characteristics are mainly dominated by drift
phenomenon. For gate-to-source voltages (VGS / larger than
threshold voltage, DG MOSFETs operate in the linear or saturation region depending on drain bias (VDS /. First we will consider the formulation of drain current for the linear region and
then in the saturation region. For small VDS , the drain current
in the linear region can be written as23
ID D Weff . Qinv /

dV .y/
;
dy

(2)

where W is the channel width, V .y/ represents the quasi-Fermi

potential along the channel, Qinv is the inversion charge, eff
is the field dependent mobility defined as14
eff D

n0
dV .y/
1 C .0 =2vSat /
dy

(3)

where vSat is the saturation velocity of carriers. The denominator in Eq. (3) signifies that the mobility is degraded due to
the velocity saturation effect. It may be noted that, in shortchannel devices, the lateral electric field along the channel
becomes comparable to the electric field at the velocity saturation point (ESat D 2vSat =n0 /, and hence the drain current starts to be affected by velocity saturation. In the present
on-current model for short-channel DG MOSFETs, the value
of saturation velocity is taken as (11.4)  107 cm/s7; 24 ;
n0 D 0 =1 C  .VGS Vth /,  a fitting parameter ranging
from 0.01 to 0.1; Vth is the threshold voltage of the device12
and 0 is the low field mobility. In our analysis, the Arora
model for low field mobility has been taken into account for
electron mobility as a function of temperature and doping concentration25 :

 2:33
T

 0:57
1252
T
300
0 D 88
C
:
Nb .x/
300
1C


T 2:546
1:432  1017
300
(4)
In charge-sheet approximation, the inversion charge Qinv ,
seen in Eq. (2), is assumed to be located at the silicon surface
like a very thin sheet of charge and is the difference of the total
silicon body charge (QTotal / and depletion charge (QBulk / as17
i.e.,
Qinv D QTotal QBulk :
(5)

front and back SiSiO2 interfaces, respectively, which can be

defined as


Eg
kT
Nbf
Vfbf D M
s C
C
ln
;
(7)
2q
q
ni

Cox 2VGS

Vfbf

Vfbb

f .y/

b .y/ ;

(8)

where M , s and Eg are the metal work function, electron

affinity and band gap of the silicon, respectively; Nbf D
Nb .x/jxD tsi and Nbb D Nb .x/jxD tsi are the acceptor den2
2
sities at the front and back SiSiO2 interfaces, respectively.
In particular, for symmetric DG MOSFETs, Vfbf D Vfbb D
Vfb and f .y/ D b .y/ D s .y/, hence the total density of
charge in the silicon body will become
QTotal D

2Cox VGS

Vfb

s .y/ :

(9)

It may be mentioned that, at threshold, f .b/ .y/ D 2f .b/

and after inversion gets pinned at 2f .b/ CV .y/ where f .b/ is
the Fermi potential23 . Therefore Equation (6) may be written
as
QTotal D

Cox 2VGS

2.f C b C V .y// :
(10)
Further, as the channel region is assumed to be fully depleted, the depletion charges QBulk can be obtained as

Vfbf

QBulk D

Vfbb

tsi
2
tsi
2

Nb .x/dx;

(11)

which on solving yields

QBulk D


2p qcNP .2bXf

.a C 2bXb / exp

a/ exp aXf


aXb bXb2 ;

bXf2

(12)

where,
Xf D X jxD

tsi
2

Xb D X jxD tsi D
2

tsi C 2Rp
;
p
2 2p
tsi

2Rp
;
p
2 2p

(13)

(14)

with the help of Eqs. (10) and (12), Equation (5) can be written
as
Qinv D

The total silicon body charge can be written as

QTotal D



Eg
kT
Nbb
s C
C
ln
;
2q
q
ni

Vfbb D M

(6)

Cox f2VGS Vfbf Vfbb 2.f C b C V .y/g

p


C q 2p cNP .2bXf a/ exp aXf bXf2


.a C 2bXb / exp aXb bXb2 :

(15)

where Cox D "ox =tox is gate oxide capacitance, "ox being the
permittivity of the SiO2 , f .y/ and b .y/ are the front and
back surface potentials at x D tsi =2 and x D tsi =2 respectively12 ; Vfbf and Vfbb are the flat band voltages related to the

Plugging Eqs. (3) and (15) into Eq. (2) and integrating on
both sides from source to drain gives the following expression
of drain current in the linear region as

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J. Semicond. 2013, 34(5)

Sarvesh Dubey et al.

Wn0


n0 VDS
L 1C
2vSat L



VDS
Cox 2VGS Vfbf Vfbb 2 f C b C
VDS
2
n p



q 2p cNP .2bXf a/ exp aXf bXf2
!

 o
2
.a C 2bXb / exp aXb bXb
VDS
(16)

ID D

or,
ID D

Cox Wn0

 .2VGS
0 VDS
L 1C
2Sat L

Vt

VDS / VDS ;

(17)

where
Vt D Vfbf C Vfbb C 2f C 2b
p



C q 2p cNP .2bXf a/ exp aXf bXf2


.a C 2bXb / exp aXb bXb2 =Cox ;

pinch-off area corresponds to a reduction of the channel length.

This length goes from L to L0 D L L. Consequently, L
has to be estimated. The voltage drop .VDS VDSat / across the
region between pinch-off point and the drain is given as17; 23
(18)

or,
ID D

ID0
;
n0 VDS
1C
2vSat L

(19)

where ID0 is the drain current without velocity saturation given

as
Cox Wn0
ID0 D
.2VGS Vt VDS / VDS :
(20)
L
Clearly, if the lateral field along the channel, VDS =L, is
much less than ESat D 2vSat =n0 , the drain current is hardly
affected by velocity saturation. The effect of velocity saturation
in Eq. (19) is to reduce ID by a factor of 1 C 2vn0SatVDS
.
L
The saturation current occurs when VDS > VGS Vth and
can be given as
IDSat D W vSat QInvSat ;

Fig. 2. Variation of drain current (ID / against drain-to-source voltage

(VDS / for different gate-to-source voltages (VGS /.

(21)

where QInvSat D Cox .2VGS Vt VDS /jVDS DVDSat is the inversion charge density at saturation and VDSat is drain saturation voltage and can be obtained as follows.
At VDSat , the surface channel collapses near the drain end
and the drain current becomes zero or pinched-off. Hence,

@ID
D 0:
(22)
@VDS VDS DVDSat
Now utilizing Eq. (17) in Eq. (22), we get the following
expression of drain saturation voltage as
q
K1 K12 4K2 K3
VDSat D
;
(23)
2K2
where K1 D Cox , K2 D 0 Cox =Sat L and K3 D
K1 .2VGS Vt /. Further, as the drain voltage (VDS / exceeds
the saturation voltage (VDSat /, the pinch-off point at the drain
end starts to shift gradually towards the source end. Thus, the

VDS D VDSat C lSat ESat sinh .L=lSat / ;

(24)

where lSat is the characteristic length of the saturated region

defined as23
r
"si tsi
lSat D
tox :
(25)
"ox 2
ESat is the lateral electric field at saturation point given
by23
ESat D 2vSat =n0 ;
(26)
and L is referred to as the amount of channel length modulation (CLM) by the drain voltage given as17; 23
2
3
s

2
VDS VDSat
VDS VDSat
L D lSat ln 4
C
C 15 :
lSat ESat
lSat ESat
(27)
The total channel length (L/ is then replaced by L to L0 D
L L in Eq. (23). The saturation current can, then, eventually
be found by putting the expressions of VDSat from Eq. (23) into
Eq. (21).
To get the smooth transition from linear to saturation region a smoothing function called VDT has been used as14; 26


VDT D VDSat 1
where K D 1

VDS
VDSat


ln .1 C exp K/
;
ln .1 C exp /

(28)

and is a fitting parameter.

2.2. Transconductance and drain conductance formulation

Transconductance quantifies the drain current variation
with gate-to-source voltage (VGS /. It can be given, in general,
as

@ID
gm D
:
(29)
@VGS VDS

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Sarvesh Dubey et al.

Hence, transconductance in the linear region can be obtained by using Eqs. (17) and (29) as:
gml D

Cox Wn0

L

 
n0 VDS
1C
2
2vSat L
C

.2VGS Vt
1 C  .VGS


.2VGS Vt VDS / 
1 C  .VGS Vth /


VDS / n0 VDS
n0 VDS
1C
2Sat L
Vth / 2vSat L

 VDS :

(30)

In the same way, gm can be calculated in the saturation

region as
2
0
13
6
gmSat D 2W vSat Cox 41

B
@ q

Cox

K12

4K2 K3

C7
A5 :

(31)

In addition, transconductance-to-drain current ratio

.gm =ID / may also be estimated which is a measure of the
efficiency with which the current is transformed into transconductance. Therefore, high efficiency of a MOS device should
be attributed to high .gm =ID / ratio9; 11; 27 .
On the other hand, for the assessment of analog circuit
performance of DG MOSFETs, the drain conductance, gd , is
an important parameter which signifies the drain influence and
can be calculated in the linear region as

@ID
gd D
:
(32)
@VDS VGS
Combining Equations (17) and (32) gives,
gdl D

W Cox 0
L
 .1 C n0 VDS =2vSat L/ .2VGS
.n0 =2vSat L/ .2VGS

Vt

 .1 C n0 VDS =2vSat L/

Vt

Fig. 3. Variation of drain current (ID / along device channel lengths

(L/ for different silicon film thicknesses (tsi /.

2VDS /

VDS / VDS
(33)

In the similar fashion, gdSat may be calculated for the DG

MOSFETs in the saturation region of operation, however, numerically because of some implicit terms in Eqs. (23) and (27).

3. Results and discussion

In this section, some theoretical results on drain current,
transconductance and drain conductance of Gaussian doped
DG MOSFET calculated from our proposed model are demonstrated. The model results, valid in linear and saturation regions, are compared with the numerical simulation results obtained by the 2D device simulation software ATLASTM . Modeling has been done under the assumption of identical front and
back gate structures with the same gate oxide thicknesses and
tungsten (with work function Mf D Mb D 4.7 eV) as the gate
material for both of the gates of the device and doping concentration of the source/drain contact regions ND D 1  1020

cm 3 . The driftdiffusion (DD) model has been used instead

of the energy-balance (EB) model because the DD model can
predict I V characteristics of short-geometry devices more realistically than the EB model12 . The CaugheyThomas [ATLAS, 2008] high field mobility model has been implemented
in the ATLASTM along with the suitable modification in the
saturation velocity of the electron (vsat.n)28 . The modified
saturation velocity is well suited for the device lengths. In DG
MOSFETs, for silicon thickness >10 nm the quantum shift in
the threshold voltage is less than the thermal voltage29 and,
therefore, quantum mechanical effects are not considered in the
analysis. Figure 2 shows the variation of drain current as the
function of drain-to-source voltage VDS for different gate-tosource voltages, VGS . As is apparent from the figure, in both
linear and saturation regions, the model is in very good agreement with the simulation results. Figure 3 plots the drain current variation against device channel length (L/ for different
silicon film thicknesses, tSi . It is observed that the drain current
decreases very rapidly with the increase in the channel length.
Also, for a fixed channel length (say, 40 nm), the drain current is higher for the higher silicon film thickness. This may
be attributed to the fact that an increase in silicon film thickness reduces the channel barrier height which results in more
drain current30 . Figure 4 deals with the effect of symmetric
and asymmetric natures of DG MOSFET upon drain current.
Note that, in our device, asymmetry is acquired by changing the
peak doping position only and all other device parameters are
left untouched. The ID VDS characteristics for different projected ranges, Rp , clearly reveal that by placing the peak of
the doping position at any other location (say, front surface,
x D tSi =2/ except at the center .x D 0/ causes a noticeable
increase in drain current. This is because heavy doping near
one surface (i.e., x D tSi =2/ results in overall reduction in
threshold voltage12 of the DG MOSFET thereby elevating the
drain current. The effect of various device parameters on the
transconductance .gm / has been investigated in Figs. 57. The
variation of transconductance (gm / as a function of gate bias
(VGS / has been shown in Fig. 5 for VDS D 0.1 V and 1 V where
an increase in gm with the drain bias is observed. The gm VGS
curve exhibits a downward trend after VGS  0.6 V for low VDS

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Sarvesh Dubey et al.

Fig. 4. Drain current (ID / against drain-to-source voltage (VDS / for

two different peak doping positions i.e. Rp D 0 nm and 5 nm. Asymmetry is introduced through keeping the peak doping position at other
than the center i.e. at Rp D 5 nm.

Fig. 5. Variation of transconductance (gm / with gate-to-source voltage

(VGS / for different drain voltages (VDS /.

D 0.1 V due to the typical low-field mobility degradation7

which clearly disappears at higher drain voltage VDS D 1 V.
Figure 6 reflects the doping dependence of transconductance
as a function of VGS . Again, the slight degradation in gm at VDS
D 0.1 V is observed for VGS D 0.60.7 V. Such decrease in gm
beyond VGS D 0.6 V may be attributed to the degradation of the
channel mobility as a function of increasing transverse electric
field across the gate oxide at higher gate bias (see Eq. (3)).
On the other hand, a higher value of transconductance at the
lower channel doping (Np D 1  1017 cm 3 / can be observed
in Fig. 6. This may be due to the enhanced carrier mobility at
lower channel doping which in turn provides more drain current leading to more transconductance. Figure 7 displays the
variation of transconductance against gate bias (VGS / with projected range (Rp / as the parameter. It is found that asymmetric
DG MOSFET (Rp at front surface) acquires higher transconductance compared to the symmetric structure (Rp at center)
while keeping other parameters constant. It may be observed,
however, that at larger VGS  1 V), the transconductance of
symmetric as well as asymmetric devices gets merged. Figure
8 compares the efficiency of the symmetric and asymmetric

Fig. 6. Variation of transconductance (gm / with gate-to-source voltage

(VGS / for peak doping concentrations, Np D 1  1017 cm 3 and Np
D 1  1018 cm 3 .

Fig. 7. Variation of transconductance (gm / with gate-to-source voltage

(VGS / for peak doping positions. Asymmetry is introduced through
keeping the peak doping position at other than the center i.e. at Rp D
5 nm.

DG MOSFET in terms of gm /ID ratio against device channel

length at VGS D 1 V. Clearly, the symmetric structure (Rp D
center) possesses a higher gm /ID ratio compared to the asymmetric device structure (Rp D front surface) as is apparent from
the results mentioned earlier in Figs. 4 and 7. Higher gm =ID
ratio thus confirms the symmetric DG MOSFET as more efficient than the corresponding asymmetric device in strong inversion. The variation of drain conductance against drain bias
with various device parameters has been shown in subsequent
figures. Figure 9 contains the drain conductance (gd / versus
drain bias (VDS / graph for two different gate-to-source voltages (VGS D 0.8 V and 1.2 V). Clearly, as shown in Fig. 9,
the higher the overdrive voltage .VGS Vth /, the greater is the
output conductance, gd . However, at larger drain bias (VDS /,
the drain conductance suddenly becomes zero. Figures 10 and
11 deal with the impact of channel doping parameters, Np and
Rp , on drain conductance as a function of drain bias (VDS /. It
is observed that lower doping (say, Np D 1  1017 cm 3 / renders higher drain conductance while asymmetric DG structure

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J. Semicond. 2013, 34(5)

Sarvesh Dubey et al.

Fig. 8. Variation of gm =ID ratio with device channel lengths (L/ for
peak doping positions. Asymmetry is introduced through keeping the
peak doping position at other than the center i.e. at Rp D 5 nm.

Fig. 10. Variation of drain conductance (gd / with drain-to-source voltage (VDS / for peak doping concentrations, Np D 1  1017 cm 3 and
Np D 1  1018 cm 3 .

Fig. 9. Variation of drain conductance (gd / with drain-to-source voltage (VDS / for different gate-to-source voltages (VGS /.

(Rp at front surface) produces higher drain conductance but

at lower drain-to-source voltage, VDS . Thus the Gaussian doping profile is found to be a viable tool to provide better control
over threshold voltage and hence drain current. Note that a reasonably good agreement between model results and simulation
results obtained by ATLASTM establishes the validity and accuracy of the proposed model.

4. Conclusion
An above-threshold drain current model of doped shortchannel DG MOSFET with a vertical Gaussian-like doping
profile has been derived for the linear and saturation regimes of
device operation. Variation in drain current as well as transconductance and drain conductance of symmetric and asymmetric
DG MOSFETs is studied in terms of various device parameters.
In terms of gm /ID ratio, the symmetric DG MOSFET is found
to be more efficient compared to the asymmetric structure. An
excellent matching has been found between the model and numerical simulation results.

Fig. 11. Variation of drain conductance (gd / with drain-to-source

voltage (VDS / for peak doping positions. Asymmetry is introduced
through keeping the peak doping position at other than the center i.e.
at Rp D 5 nm.

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