PES INSTITUTE OF TECHNOLOGY

BANGALORE SOUTH CAMPUS

1Km before Electronics City, Hosur Road, Bangalore-560100.

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

LAB MANUAL

SUBJECT: ELECTRONIC CIRCUITS AND LOGIC DESIGN LAB

SUBJECT CODE: 10CSL38
FACULTY: Ms. T. C. Jermin Jeaunita
Shunt Positive clippers:
a) To remove +ve peak above Vr level:
Circuit diagram:

Waveform

Transfer Characteristics

b) To remove +ve peak above some level

Circuit diagram:

Waveform

Transfer Characteristics

Design:

1. To remove +ve peak above some level say (+3v)

Solution:

Vo= VR + V
Vo= +3V then
VR = Vo V
VR = 3V 0.7V (cut in voltage of diode)
VR = 2.3V

Experiment No: 01

Date: ________________
CLIPPERS & CLAMPERS

AIM:
a. Design and construct a suitable circuit and demonstrate the working of positive clippers,
double-ended clippers and positive clampers using diodes.
b. Demonstrate the working of the above circuits using a simulation package.
Apparatus:
Particulars

Sl. No.

Specification

Quantity

BY 127

02

1.

Diode

2.

Resistors

1 K, 100 K

01, 01

3.

Capacitor

1f

01

4.

Functional Generator

5.

Multi-meter, CRO & Probes

01 Set

6.

Base Board and Wires

01 Set

01

CLIPPERS:
Theory:
Clipper is a circuit which removes a part of the input signal with out distorting the remaining
part of the waveform. It may be positive or negative part of an input signal. Clipping circuits is also
known as limiters, amplitude selectors, or slicers. This kind of processing is useful for signal shaping,
circuit protection and communication.

Based on working, clippers circuits are classified as

1. Positive clipper: one which removes positive part of signal.
2. Negative clipper: one which removes negative part of signal.

Based on diode arrangement clipper circuit are classified as

1. Series Clipper
2. Shunt Clipper

c) To remove +ve peak above some level (say +3 v) & -ve peak above some level (say -3v):
Circuit diagram:

Waveform:

Transfer characteristics

Procedure:
1. Before making connections components are checked for good working conditions.
2. Make the connections as shown in the circuit diagram.
3. Using a signal generator, apply a sine wave input Vi whose amplitude is greater than the clipping
level is applied to the circuit.
4. Output waveform V0 is observed on the CRO. Record the amplitude and time period from the
waveforms.
5. For transfer characteristics, the input voltage is given to the channel 2, output voltage is given to
the channel 1 and XY plotter is pressed.
6. Clipped voltage is measured and verified with the designed values.

Results:
SL
No

Clipper type

Output (Theoretical)

Shunt positive
(without biasing)

Shunt positive
(with biasing)

3V

Shunt positive
(with biasing)

6V

Double ended
(without biasing)

0.7 V

+0.7V, -0.7V

Output (Practical)
Hardware

Output (Practical)
Software

Remarks

Double ended
(with biasing)

+3V, -3V

Double ended
(with biasing)

+5V, -2.9V

a) Positive peak clamped at reference voltage (Vr) level:

Circuit diagram:

Waveform:

b) Negative peak clamped to Vr level:

Circuit diagram:

Design:
RL C>> T
Assume T = 1 ms, let RL C = 100 T, then RL C = 100 ms,
Let R1 = 100 K

C = 1 f

Wave form

CLAMPERS:
Theory:
Clamper adds a DC voltage to the AC level of input signal. Sometimes it is necessary to add
the DC level to the AC output signal. The circuits which are used to add DC level as per the
requirements to the AC output signal are called clamper circuits. The capacitor, diode and resistance
are the three basic elements of a clamper circuit. The clamper circuits are also called DC restorer or
DC inserter circuits.
Depending upon the positive DC or negative DC shift introduced in the output waveform the
clampers are classified as
a. Positive clampers
b. Negative clampers
A negative clamper is a circuit which adds a negative level to the AC output. The output
waveform consists of a capacitor C, ideal diode D and the load resistance RL. During the +ve cycle of
the i/p voltage Vi, the capacitor gets charged through forward biased diode D up to the maximum
value Vm of the i/p signal Vi. In the ve half cycle, the diode D will be remains reverse biased and
the capacitor will be discharging through the resistance RL.
In positive clamper, by charging the orientation of the diode in the negative, the +ve clamper
circuit can be achieved.
During negative half cycle of the i/p voltage Vi, the diode D gets forward biased and almost
instantaneously the capacitor C gets charged. In the positive half cycle the diode D is reverse biased,
the capacitor starts discharging through RL.
Both +ve & -ve clampers are widely used for instance in television receivers to change the
reference level of video signals, clampers are also used in radar and communication circuits.
WORKSHEET:
Procedure:
1. Components are checked for their good working conditions.
2. Connections are made as shown in the circuit diagram.
3. A square wave input Vi is applied through ASG.
4. Keeping the AC/DC knob of the CRO in DC position, Output wave form V0 is observed on the
CRO.
5. Clamped voltage is measured and verified with the designed values

Results:
SL
No

Clamper type

Output (Theoretical)

Positive
(without biasing)

0.7 V

Negative
(without biasing)

0.7 V

Circuit diagram: RC - Coupled Amplifier

Frequency response:

Output (Practical)
Hardware

Output (Practical)
Software

Remarks

Input impedance:

Output impedance:

Experiment No: 02

Date: ________________
RC COUPLED CE AMPLIFIER

AIM:
a. Design and construct a suitable circuit and determine the frequency response, input
impedance, output impedance, and bandwidth of a CE amplifier.
b. Design and build the CE amplifier circuit using a simulation package and determine the
voltage gain for two different values of supply voltage and for two different values of emitter
resistance.
Apparatus:
Sl. No.

Particulars

Specification

Quantity

1.

Transistor SL 100

01

2.

Resistors

as per design

3.

Capacitors

47 f, 0.1f

4.

DRB

5.

Multimeter + CRO Probes

01 Set

6.

Base Board + Wires

01 Set

01, 02
01

Theory:
An amplifier is a circuit which increases the voltage, current or power of i/p signal where the
frequency is maintained constant from o/p to i/p signal. The common collector or emitter follower
circuit has high i/p impedance. Typically it is 200K to 300K. A single stage emitter follower has
i/p impedance up to 800K. The i/p impedance of circuit can be improved by direct coupling two
stages of emitter follower amplifier. CE amplifier provides current in turn voltage amplification. The
ratio of Collector current to base current is noted as the current amplification factor and is denoted as
i.e.[ = IC/IB], is very large.

RC-Coupled amplifier is employed as voltage amplifier and where non-linear distortion is less
because it has an excellent audio frequency over a wide range of frequencies. Circuit contain voltage
divider resistor [R1 & R2].
R1, R2 and RC are selected in such a way that transistor operates in active region. Re is used
for stabilization of operating point. Coupling capacitor is used to block dc current. The emitter bypass capacitor Ce is connected to avoid negative feedback.

Tabular Column:
Vi =.......................... mV
f in Hz

Vo in Volts

Av = (Vo / Vi)

Av db = 20 log (Vo / Vi)

Simulation Results:
Sl. NO

Vi in Volts

Vo in Volts

Av = (Vo/Vi)

Av in db

Av in db using Bode plotter

Input signal increases base current in turn collector current increases [i.e. Ic = Ib]. Hence
output voltage is large compared to input voltage which is known as amplification

Procedure:
I) To plot the frequency response:
1. The input frequency is kept in the mid-band region (around 10 kHz) and the input voltage is
adjusted to a convenient value in ASG so that the output waveform is distortion less and this
value of input voltage must be kept constant throughout the experiment.
2. Frequency of the input signal is varied from 10Hz to its max. Value 10MHz in steps and at each
step corresponding output voltage Vo is noted down.
3. All the readings are tabulated and a graph of gain in db v/s frequency in Hz is plotted on a semi
log sheet.
4. 3db bandwidth is determined from the frequency response curve.

II) To measure input impedance (Zi):

1. Connections are made as shown in the circuit diagram ( ).
2. The input frequency is kept in the mid-band region with all knobs of DRB in the Zero position,
the output voltage falls to half of the initial output voltage
3. The value of DRB is recorded which is equal to input impedance Zi of the amplifier + signal
generator resistance 50.
Therefore Zi = DRB Value Audio Signal Generator Resistance (50)
[Note: Zi < R1 | | R2]
III) To measure output impedance (Zo):
1. Connections are made as shown in the circuit diagram ( ).
2. In the mid-band frequency region (where the gain is constant) with DRB in its max. Value, the
output voltage is measured.
3. The DRB is varied till the output voltage falls to half the initial value.
4. The value of DRB is recorded which is equal to the output impedance Zo of the amplifier. [Note :
Zo < Rd]

WORKSHEET:

IV) To find the Gain Bandwidth Product (GBW) :

1. Gain Bandwidth Product = Max. gain (without db) X bandwidth (Figure of merit)
= Avm X (f2 f1) Hz

Results:
1. Maximum Gain, Av=..
2. Input Impedance: Zi =
3. Output Impedance: Zo =
4. Bandwidth: BW= .Hz.
5. Figure of Merit, FM (GBW): .

MOSFET Circuit Diagram:

IRF 540

D S

Tabular Column:
Transfer Characteristics
VDS1 = _____________ V
VGS in Volt

ID in mA

VDS1 = _____________ V
VGS in Volt

ID in mA

Experiment No: 03

Date: ________________
STATIC CHARACTERISTICS OF MOSFET

AIM:
a. Design and construct a suitable circuit and determine the drain characteristics and
transconductance characteristics of an enhancement-mode MOSFET.
Apparatus:
Sl. No.

Particulars

Range

Quantity

0-20/200mA

1.

MOSFET ( IRF 540 )

2.

Milliammeter

3.

Multimeter

4.

Sping board & Connecting wires

few

Theory:
A MOSFET is a voltage controlled device and requires a only a small input current. The
switching speed of MOSFET is very high and the switching time s are of the order of nanoseconds It
has very high input impedance and works at very high switching frequency.
MOSFETs are of two types namely Enhancement type and Depletion type. Each type are
subdivided into two types namely p-channel and n-channel. IRF 540 is an n-channel enhancement
MOSFET. An n-channel enhancement MOSFET has N substrate with p-impurities on other side. A
thin layer of metal oxide is deposited over the left side of the channel. A metallic gate is deposited

over the silicon di oxide layer which is an insulator. Hence gate is insulated from the channel and for
this reason MOSFET is sometimes called insulated gate FET.
Tabular Column:
Drain Characteristics
VGS1 = _____________ V
VDS in Volt

VGS1 = _____________ V

ID in mA

VDS in Volt

ID in mA

Ideal Graph:
Transfer Characteristics:

Drain Characteristics
ID in mA

Constant current region

ID in mA
VDS2
VDS

ID

VDS1

VGS1

VDS2 > VDS1

ID

VGS2 > VGS1

Constant resistance region

VGS

VT

VGS2

VGS in V

VDS in V

Procedure:
Transfer Characteristics:
1. Check the components / Equipment for their working condition.
2. Connections are made as shown in the circuit diagram.
3. Set VDS to some convenient voltage (say 0.2 V).
4. Increase VGS gradually and note down the corresponding changes in drain current ID.
5. Repeat the above step for different value of VDS (say 0.3 V).
6. A graph of VGS Vs ID is plotted and from the graph Trans conductance is calculated.
Output Characteristics:
1. Set VGS to some convenient voltage greater than threshold voltage VT.
2. Increase VDS gradually and note down the corresponding changes in drain current ID.
3. Repeat the above step for different value of VGS.
4. A graph of VDS Vs ID is plotted and from the graph drain resistance is calculated.
Results:
Trans conductance
Drain Resistance

gm = ID / VGS = ____________ mho

RD = VDS / ID = ____________

CMOS Inverter Circuit Diagram

The left hand part of the above circuit shows the connection of a CMOS inverter.

XLA1 stands for Logical Analyzer.

The right hand part shows the wave forms of a CMOS

If the PMOS is ON, NMOS is OFF and If NMOS is ON, PMOS is OFF.

If VGS = +ve NMOS is ON. For VGS = 0 or ve NMOS is OFF.

If VGS = -ve PMOS is ON. For VGS = 0 or +ve PMOS is OFF.
b) Design and build CMOS inverter using a simulation package and verify its truth table.
CMOS INVERTER:

A CMOS gate, a building block of a digital IC, is composed of an n-channel (NMOS) and pchannel (PMOS) metal-oxide-semiconductor field effect transistors (MOSFET's). In the circuit
diagram, the PMOS device appears in the upper region (connected to a dc bias VCC, logic 1) and the
NMOS device appears in the lower region (connected to the ground potential, GND, logic 0).
For operation, the input Vin, connected to the Gate terminals of both NMOS and PMOS, turns
ON one device type and turns OFF the other device type. The ON/OFF behavior of a MOSFET
device depends on whether the voltage difference between Gate and Source, Vgs, is greater or less
than the threshold voltage, VT, which is a property intrinsic to the device1 (i.e., device structure and
material property). When a MOSFET device is ON, its channel region (the tall rectangle in the
middle of the transistor symbol, the left-hand-side diagram) is filled with charge carriers (blue for
electrons and red for holes) and thus that device electrically connects (or short circuits) the output,
Vout, to the high voltage VCC or to low voltage GND.
For the CMOS inverter, Vout is connected to the VCC (i.e., logic 1) if the PMOS is ON and
the NMOS is OFF. Vout is connected to the GND (i.e., logic 0) if the PMOS is OFF and the NMOS

is ON. Since the transistor ON/OFF behavior is controlled by the input voltage Vin, the output Vout
is determined by the Inverter gate and the input.

Circuit Diagram (With reference):

With Reference:

Circuit Diagram (Without reference):

Wave forms:

Transfer characteristics:

Without Reference: Wave forms:

Transfer characteristics:

Experiment No: 04

Date: ________________
SCHMITT TRIGGER

AIM:
a. Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values and
demonstrate its working.
b. Design and implement a Schmitt trigger using Op-Amp using a simulation package for two
sets of UTP and LTP values and demonstrate its working.
Apparatus:
Sl. No.

Particulars

Range

Quantity

1.

OP AMP

741

2.

Resistors

As per design

3.

signal generator

4.

CRO with probes

1 set

5.

DC power supply

6.

Spring board and wires

1 set

Procedure:
1. Check the components / Equipment for their working condition.
2. Connections are made as shown in the circuit diagram.
3. A sinusoidal input whose amplitude is greater than the magnitude of the UTP & LTP is applied, a
square wave output is obtained and observed on the CRO.
4. UTP & LTP points are noted.
5. To obtain transfer characteristics, input is applied to channel A and output to channel B.
6. UTP & LTP are measured on the transfer characteristics also and thus verified.

Note: The amplitude of the input voltage should be greater than the magnitude of UTP & LTP level.
Formulas to be used:
V R
R2
UTP= R 1 +V
R 1 +R 2 sat R1 +R 2
LTP=

VR R 1
R2
-V
sat R 1 +R 2
R 1 +R 2

Design : With Reference

Let given UTP = 6V, LTP= -2V. Assume Vsat = 12 V

UTP + LTP = 4 = 2

R
VR R 1
R +R
VR = 2 1 2 = 2 1+ 2
R1 +R 2
R1
R1

[eqn 1]

V R2
R2 1
UTP - LTP = 8 = 2 sat

= R1 = 2R 2
R1 +R 2
R1 2

[eqn 2]

Assume R2 = 1K then R1 = 2 K.
Substitute R1 and R2 in eqn1 and calculate VR VR = 3V

Similarly design for UTP = +4, +8, 2 and 2; LTP = -4, +2, -4 and 4.

Design : With out Reference

Let given UTP =4V, LTP=-4V Assume Vsat = 12 V
UTP + LTP = 0 = 2

VR R 1
R1 +R 2

[eqn 3]

Eqn 3 = 0

V R2
R2 1
UTP - LTP = 8 = 2 sat

= R1 = 2R 2
R1 +R 2
R1 2

[eqn 4]

Assume R2 = 1K then R1 = 2 K

Similarly design for UTP = +4, +8, 2 and 2; LTP = -4, +2, -4 and 4.

Results:
1. With Reference:
Sl. No

UTP(TH)

LTP(TH)

Hardware
UTP(Prac)

Software

LTP(Prac) UTP(Prac) LTP(Prac)

2. Without Reference:
Sl. No

UTP(TH)

LTP(TH)

Hardware
UTP(Prac)

Software

LTP(Prac) UTP(Prac) LTP(Prac)

Circuit Diagram:

Wave forms:

Design:
Given f0 = 1 Khz
Relation between R1 and R2 is

R2 = 1.16 R1
R1= 10 k.

Let

Then R2 = 11.6 k.

To calculate R:
Formula to be used:

f0 =

1
2RC

Required f0 = 1 Khz. Assume C = 0.1f then R= 5 k

Experiment No: 05

Date: ________________
OP AMP RELAXATION OSCILLATOR

AIM:
a. Design and construct a rectangular waveform generator (OpAmp relaxation oscillator) for
given frequency and demonstrate its working.
b. Design and implement a rectangular waveform generator (OpAmp relaxation oscillator) using
a simulation package and demonstrate the change in frequency when all resistor values are
doubled.

Apparatus:
Sl No

Particulars

Range

Qty

A 741

01

IC

Resisters

As per Design

Capacitors

As per Design

Diode

BY 127

01

POT or DRB

20k

01

THEORY:
A relaxation oscillator is a circuit that repeatedly alternates between two states at with a
period that depends on the charging of a capacitor. The capacitor voltage may change exponentially
when charged or discharged through a resistor from a constant voltage, or linearly when charged or
discharged through a constant current source. With exponential charging, the timing is expressed in
terms of time constants RC.

PROCEDURE:
1. Check the components / Equipment for their working condition.
2. Make connections as shown in circuit diagram.
3. Check the output at pin 6 of op Amp.
4. Measure the frequency of the output and compare with the given value.

Result:
Sl No

f0 (Theoretical)

f0 (pract) H/W

f0 (pract) simulation

Remarks

Circuit Diagram:
Astable Multivibrator

Wave Form:

Design:
Let Time period T required be 1msec and duty cycle D = 60% = 0.6
Capacitor charging time = tc = 0.69RA C ---------- (1)
Capacitor discharging time = td = 0.69 RB C ---------- (2)
t
c
But T = t + t and any % dutycycle =
c d
t +t
c d
t
Then D = c
T
t
D = 0.6 = c
1msec
t = 0.6msec and t = 0.4msec
c
d

From (2): 0.4 = 0.69 R 2 C

Choose C = 0.01f
 R2 = 5.9k
Choose RB=5.6 k (+330 )
From (1): 0.6= 0.69 R1 C
 RA = 8.6k

Experiment No: 06

Date: ________________
ASTABLE MULTIVIBRATOR

AIM:
Design and implement an astable multivibrator circuit using 555 timer for a given frequency
and duty cycle.

Apparatus:
Sl No

Particulars

Range

Qty

555 timer

--

Power Supply

--

Resistors

As per design

Capacitors

As per design

CRO and patch cords

--

1 set

Procedure:
a) Check the components / Equipment for their working condition.
b) Rig up the circuit as shown in the diagram
c) Observe the out put wave form, note down tc & td.
d) And calculate the duty cycle.
e) Compare the theoretical value with practical value.

Result:

Sl No

F(Theoretical)

D(Theoretical)

F(Practical)

D(Practical)

Function Table:
INPUTS

OUTPUT
Comments

A2

A1

A0

EN

D0

D0

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

If En pin is at logical high value then

irrespective of input, output will be 1.
If En pin is at logical zero value then
if input is 0 0 0 then output will be D0
If En pin is at logical zero value then
if input is 0 0 1 then output will be D1
If En pin is at logical zero value then
if input is 0 1 0 then output will be D2
If En pin is at logical zero value then
if input is 0 1 1 then output will be D3
If En pin is at logical zero value then
if input is 0 1 0 then output will be D4
If En pin is at logical zero value then
if input is 0 1 0 then output will be D5
If En pin is at logical zero value then
if input is 0 1 0 then output will be D6
If En pin is at logical zero value then
if input is 1 1 1 then output will be D7

Experiment No: 07
MULTIPLEXER
AIM:

a. Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the
simplified logic expression using 8:1 multiplexer IC.
Components Required:
SI. NO

Particulars

Specification

Quantity

IC 74151

1.

Multiplexer IC

2.

Trainer Kit

----

3.

Patch cords

----

20

Theory:

Multiplexer means many into one. A multiplexer is a circuit with many inputs but only one
output. By applying control signals, we can steer any input to the output. Thus it is also called a data
selector and control inputs are termed as select inputs. The circuit has n input signals, m control
signals and 1 output signal. M control signals can select at the most 2m input signals thus n<= 2m.
Multiplexer is sometimes called universal logic circuit because a 2n to 1 multiplexer can be used as a
design solution for any n variable truth table.
Lets consider A, B and C variables to be fed as select inputs. The fouth variable D then has to
be present as data input using Entered Variable Map method. All combinations of 3 select inputs and
the data input is written in the truth table. Corresponding Y value(the output) is written in the fifth
column. For the 8 combinations of control inputs, the corresponding 8 inputs for the mux is written in
the 6 column. Using these 8 inputs, the 8 : 1 Mux circuit can be designed and implemented.

Consider a 4 Variable expression:

f(A,B,C,D) = (2,4,5,7,10,11,14) + d (8,9,12,13,15)
Let D be map entered variable
Decimal
Value

Inputs

000

000

001

ABC

MEV Output
F
D

001

010

010

011

Entry in
MEV Map
0 (D0)

D (D1)

Comments
If function F equals 0 for both values of MEV,
enter 0 in appropriate cell on MEV map
If function F complements to the values of MEV
then enter complement of MEV.

1 (D2)

If function equals 1 for both values of MEV,

enter 1.

D(D3)

If function equals to MEV value the enter MEV.

011

100

100

10

101

11

101

12

110

13

110

14

111

15

111

X (D4)

If both function values are X then enter 0 or 1

1 (D5)

If function equals 1 for both values of MEV,

enter 1

X (D6)

If both function values are X then enter 0 or 1

1 (D7)

If function equals 1 for both values of MEV,

enter 1

Procedure:

1. Verify all components and patch cords for there good working condition.
2. Make the connection as shown in the circuit diagram.
3. Give supply to the trainer kit.
4. Provide input data to circuit via switches and verify the truth table.
Pin Diagram:

Circuit Diagram:

+Vcc

16

15

14

4
Y
Y

IC 74151

13

12

11

10

Experiment No: 08
MS JK FLIP FLOP
AIM:

a. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
Components Required:
SI. No.

Particulars

Specification

Quantity

1.

3 input Nand IC

7410

01

2.

Input Nand IC

7400

02

3.

Trainer kit

---

01

4.

Patch cords

---

20

Theory:

JK flip-flop provides the solution for SR flip-flop problem. Compared to SR flip-flop, JK flipflop has two new connections from the Q and Q outputs back to the original input gates. JK flip-flop
behaves like the SR flip-flop except for input condition 1 and 1. Its output toggles for every clock
pulse input unlike SR flip-flop. Although JK flip-flop circuit is an improvement on the clocked SR
flip-flop it still suffers from timing problems called "race". This problem can be solved by Masterslave flip-flop.
The Master-slave JK flip-flop is basically two JK bitable flip-flops connected together in a
series configuration with the outputs form Q and Q from the slave flip-flop being fed back to the
inputs of the Master with the outputs of the Master flip-flop being connected to the two inputs of the
slave flip-flop. The circuit accepts input data when the clock signal is HIGH, and passes the data to
the output on the falling-edge of the clock signal. In other words, the Master-Slave JK flip-flop is a
Synchronous device as it only passes data with the timing of the clock signal.

Procedure:

1. Verify all the components and patch cords for there good working condition.
2. Make connection as shown in the circuit diagram.
3. Give supply to the trainer kit
4. Provide input data to circuit via switches and verify the truth table.

PIN DETAILS OF ICs:

Circuit diagram:

JK FLIP-FLOP TRUTH TABLE:

Clk

Pos edge

Pos edge

Pos edge

Pos edge

Toggle

Neg-edge

No Change

No Change

Experiment No: 09
SYNCHRONOUS COUNTER
AIM:

a. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.
Components Required:
Sl.No

Particulars

Range/Specification

Qty

JK flip-flop IC

7476

2 input AND IC

7408

Digital IC trainer kit

---

Patch cords

---

20

Theory:

In digital logic and computing, a counter is a device which stores (and sometimes displays)
the number of times a particular event or process has occurred, often in relationship to a clock signal.
A synchronous counter is one whose output bits change sate simultaneously. Such a counter
circuit can be built from JK flip-flop by connecting all the clock inputs together, so that each and
every flip-flop receives the exact same clock pulse at the exact same time. This results in all the in all
the individual output bits changing state at exactly the same time in response to the common clock
signal with no ripple effect i.e. with no propagation delay.
By examining the four-bit binary count sequence, it noticed that just before a bit toggles, all
preceding bits are "high". That is a synchronous up-counter can be implemented by toggling the bit
when all of the less significant bits are at a logic high state. For example, bit 1 toggles when bit 0 is
logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit
0 are all high; and so on.
IC 7476 contains 2 JK flip-flops with preset and clear signals.

Procedure:

1. Verify all the components and patch cords for there good working condition.
2. Make connection as shown in the circuit diagram.
3. Give supply to the trainer kit
4. Provide input data to circuit via switches and verify the truth table.

Circuit diagram of Mod 8 counter:

DESIGN FOR MOD 8 UP COUNTER:

Present State
QC
QB
QA
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Design:

Next state
QC+1 QB+1 QA+1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0

KC
X
X
X
X
0
0
0
1

JC
0
0
0
1
X
X
X
X

Flip flop inputs

KB
JB
X
0
X
1
0
X
1
X
X
0
X
1
0
X
1
X

KA
X
1
X
1
X
1
X
1

JA
1
X
1
X
1
X
1
X

Mod-5 Circuit Diagram:

Experiment No: 10
RING COUNTER
AIM:

a. Design and implement a ring counter using 4-bit shift register and demonstrate its working.
Components Required:
Sl.No

Particulars

Specification

Qty

7495, 7404

1,1

IC

Digital IC trainer kit

Patch cords

20

Theory:

A ring counter is a counter where the output of one flip-flop connects directly into the input of
another to produce a particular output pattern. The ability to load the flip-flops to particular state
permits a repeatable output pattern. Typically a pattern consisting of a single 1 bit is circulated, so the
state repeats every N clock cycles if N flip-flops are used. It can be used as a cycle counter of N
states.
IC 7495 is a 4-bit shift register with parallel inputs/output, serial output with right/left
shifting. Pin 6 decides the mode, if it is at low then it will act as a serial shifter and if it is at high then
it will load the data parallel. Shifting left requires external connection of QB to A, QC to B, and QD
to C. serial date is entered at input D.

Procedure:

1. Verify all the components and patch cords for there good working condition.
2. Make connection as shown in the circuit diagram.
3. Give supply to the trainer kit
4. Provide input data to circuit via switches and verify the truth table.

Pin diagram:

OPERATION OF 7495:

Mode-0 for serial shifting of data

Mode-1 for parallel loading of data
Clk 1 is used for right shifting of data
Clk 2 is used for left shifting of data and for parallel loading of
data
A, B, C, D Parallel data inputs
QA, QB, QC, QD - Outputs

STATE TABLE
Clk

QA

QB

QC

QD

Ring counter

Workout: Johnson Counter (switched tail counter).

Repeats

Truth table for Johnson Counter

Clk

QA

QB

QC

QD

10

Repeats

Experiment No: 11
DECADE COUNTER
AIM:

Design and implement an asynchronous counter using decade counter IC to count up from 0
to n (n<=9) and demonstrate its working.
Components Required:
SI. NO

Particulars

Specification

Quantity

7490

1.

Decade counter IC

2.

Trainer Kit

----

3.

Patch cords

----

20

Theory:

A counter is a register that goes through a predetermined sequence of states upon the
application of input pulses. In asynchronous counter a clock signal is provided for one flip-flop and
its output is provided as clock source for next flip-flop. The output of asynchronous counter is not
synchronized with clock signal.
A decade counter follows a sequence of 10 states and returns to zero after the count of
nine. Such a counter must have atleast 4 flip flops to represent each decimal digit since a decimal
digit is represented by a binary code with atleast 4 bits.

The following are the conditions for each flip flop state transition.
1. QA is complemented on the negative edge of every count pulse
2. QB is complemented, if QD is equal to 0 and QA goes from 1 to 0. QB is cleared if QD is
equal to 1 and QA goes from 1 to 0.
3. QC is complemented when QB goes from 1 to zero.
4. QD is complemented whenm QC, QB is equal to 1,1 and QA goes from 1 to 0. QD is cleared
if either QC or QB is zero and QA goes from 1 to 0.
Procedure:
1. Verify all the components and patch cords for there good working condition.
2. Make connections as shown in the circuit diagram.
3. Give supply to the trainer kit and verify the truth table.
State Diagram:
0000

0001

0010

1001

1000

0111

PIN DIAGRAM:

0011

0110

0100

0101

7490 as a Decade counter:

Truth table:
Clk

QD

QC

QB

QA

0
REPEATS

Experiment No: 12
R-2R LADDER NETWORK
AIM:

Design and construct a 4-bit R-2R ladder D/A converter using OpAmp. Determine its
accuracy and resolution.
Components Required:
SI.
NO
1.

Specification Quantity

Particulars

Resistors

2.

Op-Amp IC

3.

Trainer kit
Spring board/ bread board & connecting
wires
CRO & probes or Multimeter

4.
5.

1 K , 2 k

4,6

A 741

---

----

1 set

----

Theory:

A digital to analog converter accepts an n-bit input word in binary and produces an analog
signal proportion to it. There are mainly two techniques used for analog to digital conversion.
1. Binary weigted resistor D/A converter
2. R/2R ladder D/A converter.
In these techniques the shunt resistors are used to generate n binary weighted currents. These
currents are added according to switch positions controlled by the digital input and then converted
into voltage to give analog voltage equivalent to digital input. R/2R ladder uses only two resistor
values. This avoids resistance spread drawback.
Procedure:

1. Verify all the components and patch cords for there good working condition.
2. Make connection as shown in the circuit diagram. And give supply to the trainer kit. Provide
input data to circuit via switches and verify the truth table.

FORMULA :
R Vref
f
D + 2D + 4D + 8D
V =
0 R 16
0
1
2
3

Where the D0, D1, D2, D3 take the value 0 or 1. Rf is feed back resistor. Vref if reference voltage.

Pin Diagram:

NC

NC

Inverting

+Vcc

Non-Inverting

Output

-Vcc

NC

IC 741

Tabulation

D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Binary Inputs
D2
D1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

Circuit Diagram:

Theoritical Values(V)

D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Practical Values(V)

Calculation:

Binary input switch = 5V

V ref = 5V
Step size for 4 bits = Vref / 24 * Rf
= 5 / 24 * 2 *R / 3
= 0.20833V
When input is 0000, output voltage is 0V
When input is 0001, output voltage is 0.20833V
When input is 0010, output voltage is 0.41666V and so on
When input is 1111, output voltage is 15 * 0.20833 = 3.12495 V

Resolution in % = (Step size / Full scale voltage) * 100

Accuracy = (Practical full scale voltage / Theoretical full scale voltage ) * 100

INTRODUCTION TO VERILOG
VERILOG is a complex, sophisticated Hardware Description Language (HDL) which has a
number of constructs similar to the C programming language. The designer can provide the initial
description of the circuit in several different ways; one efficient way is to write this description in
the form of VERILOG source code. This compiler translates this code into a logic circuit.
OBJECTIVE:
1. To allow the structural representation of logic circuits by representing simple circuit
elements such as logic gates or even transistors and a larger circuit can be defined by
writing code that connects such elements tighter.
2. To describe a circuit through behavioral representation by using logic expressions and
programming constructs that defines the behavior of the circuit but not its actual structure in
terms of gates.
GENERAL STRUCTURE OF VERILOG:

module module_name(x1, x2, x3, y);

input x1, x2, x3;
output y;
assign y = (x1 & x2 & x3);
endmodule

A circuit or sub-circuit described with VERILOG is called a module. The module has a name,
module_name, which can be any valid identifier, followed by a list of ports, in which it refers to an
input or output connection in a circuit. The ports can be of type input, output, inout and be either
scalar or vector. A module can contain any number of variables (reg or integer) declarations and a

variety of other types of statements which are included in general form. The assign is the keyword
which instantiates the gate to describe the circuit structure with the continuous assignment which in
turn describes the circuit function. Here, y can be any expression involving the operators. Multiple
assignments can be specified in one assignment statement, using commas to separate the
assignment.

EXPERIMENT 7(b) MULTIPLEXER (8:1)

AIM: To write the VERILOG code for 8:1 Multiplexer. Simulate and verify its working.
COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer.
BLOCK DIAGRAM OF 8:1 MULTIPLEXER:

TRUTH TABLE:
INPUTS
S(2) S(1) S(0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

OUTPUT
Y
I(0)
I(1)
I(2)
I(3)
I(4)
I(5)
I(6)
I(7)

VERILOG CODE:
module Mux(y, i, s);
output y;
input [7:0]i;
input [2:0]s;
reg y;
always @(s or i)
if (s==0)
y=i[0];
else if (s==1)
y = i[1];
else if (s==2)
y = i[2];
else if (s==3)
y = i[3];
else if (s==4)
y = i[4];
else if (s==5)
y = i[5];
else if (s==6)
y = i[6];
else if (s==7)
y = i[7];
endmodule

D FLIP FLOP
AIM: To write the VERILOG code for D FF with positive edge triggering. Simulate
and verify its working.
COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer.
BLOCK DIAGRAM OF D FLIP-FLOP:
D
CLK

D FF

Q
QB

TRUTH TABLE:
INPUT
D
0
1

OUTPUTS
Q
QB
0
1
1
0

VERILOG CODE:

module DFF(D, CLK, Q, QB);

input D,CLK;
output Q, QB;
reg Q;
always @(posedge CLK)
Q = D;
assign QB = (~ Q);
endmodule

MOD 8 UP COUNTER
AIM: To write the VERILOG code for MOD - 8 Up counter. Simulate and verify its
working.
COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer.
BLOCK DIAGRAM OF MOD-8 UP COUNTER:
RST
EN

MOD-8 UP
COUNTER

Q
C
TRUTH
TABLE:

RST
1
0
0
0
0
0
0
0

CLK
X
1
1
1
1
1
1
1

EN
0
1
1
1
1
1
1
1

Q
0000
0001
0010
0011
0100
0101
0110
0111

VERILOG CODE:

module MOD8(RST, CLK,EN, Q);

input RST, CLK, EN;
output [3:0] Q;
reg [3:0] Q;
always @(posedge CLK)
begin if(RST)
Q = 4b0000;
else
if(EN)
Q = Q+1;
if(Q == 4b1000) Q = 4b0000;
end
endmodule
RESULT: The VERILOG code for MOD-8 Up counter is written, coded, simulated and
verified its working by the truth table.

SWITCHED TAIL OR JOHNSONS COUNTER

AIM: To write the VERILOG code for Switched-tail counter. Simulate and verify its
working.
COMPONENTS REQUIRED: Xilinx (Verilog) Simulation software and computer.
BLOCK DIAGRAM OF SWITCHED-TAIL COUNTER:
RST
EN

SWITCHED-TAIL
COUNTER

Q
CLK
TRUTH
TABLE:

EC & LD LAB - 10CSL38

RST
1
0
0
0
0
0
0
0
0
0

CLK
X
1
1
1
1
1
1
1
1
1

EN
0
1
1
1
1
1
1
1
1
1

2013 - `14

Q
0001
0000
1000
1100
1110
1111
0111
0011
0001
0000

VERILOG CODE:
module JOHN(RST, CLK, EN,
Q); input RST, CLK, EN;
output [3:0] Q;
reg [3:0] Q;
always @(posedge
CLK)
begin
if(RST)
Q = 4b0001;
else if(EN)
Q = {~ Q [0], Q [3], Q [2], Q [1]};
end
endmodule
RESULT: The VERILOG code for Switched-Tail counter is written, coded,
simulated and verified its working by the truth table.

VIVA QUESTIONS
CLIPPERS AND CLAMPERS
1. Define p-n junction.
2. Mention the different types of diodes.
3. Explain the V-I characteristics of diode.
4. Define a Clipping Circuit.
5. Mention the different types of clipping circuits.
6. Compare Series and Shunt Clipper.
7. Mention the applications of clipper circuits.
8. Define Clamping Circuit.
9. What are the different types of clamping circuits?
10. Define positive and negative clamping.
11. Mention the applications of clamping circuits.
12. What could be the voltage across the capacitor?
13. What is the importance of C & RL in the clamping circuit?

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EC & LD LAB - 10CSL38

2013 - `14

RC COUPLED CE AMPLIFIER
1.
2.
3.
4.

Define Quiescent Point.

State different region of operating transistor.
What are different configurations of operating the transistor?
Compare common base, common emitter and common collector configuration of
transistor.
5. Define Amplifier. Mention different types of amplifiers.
6. Define ,, ?
7. Define Early Effect of transistor.
8. Name different type of amplifier based on coupling.
9. What are the factors that affect the stability of a transistor?
10. Define Biasing. Mention its different types.
11. What are the reasons for the reduction in gain at low and high frequency?
12. What is the importance of emitter-by-pass capacitor?
MOSFET
1.
2.
3.
4.
5.

Define MOSFET
What are the different types of MOSFET?
Differentiate between enhancement mode and depletion mode MOSFET.
Bring out the differences between MOSFET, JFET and UJT.
Explain the working of a CMOS Inverter.

SCHMITT TRIGGER
1.
2.
3.
4.
5.

What is Schmitt Trigger?

Explain the working of Schmitt trigger.
Define the term U.T.P and L.T.P?
Define Dead band or Dead zone.
Mention the applications of Schmitt Trigger.

RELAXATION OSCILLATOR:
1.
2.
3.
4.

Why this circuit is named as Relaxation oscillator?

What is an oscillator?
What are the different types of oscillators?
Explain the working of the relaxation oscillator.

ASTABLE MULTIVIBRATOR:
1.
2.
3.
4.
5.
6.

Define a multivibrator?
What are the different types of Multivibrators?
Explain the working of astable multivibrator.
Define duty cycle?
What is the necessity of the diode in the circuit shown of a astable multivibrator?
Explain the operation of a 555 timer IC.

Dept. of CSE, PESIT Bangalore South Campus

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EC & LD LAB - 10CSL38

2013 - `14

MULTIPLEXER:
1.
2.
3.
4.
5.
6.

What is a multiplexer?
What is the advantage of using VEM Technique?
What is the importance of Enable Pin?
Differentiate between a MUX and a Decoder?
What is the importance of select line in a MUX?
How to decide the number of Select lines for any MUX?

FLIP FLOPS:
1. Differentiate between a latch and a Flip-Flop.
2. What are the different types of flip-flops? Explain by showing the truth table?
3. What is Race-around problem? How can you rectify it?
4. Differentiate between Sequential and Combinational circuits.
5. Explain the working of a MS-JK flip-flop.
6. What are the difference between +ve edge triggered and ve edge triggered circuit?
7. What is a counter?
8. Differentiate between synchronous and asynchronous counters.
9. What types of flip-flops can be used to implement the memory elements of a counter?
10. Explain the use of PRESET and CLEAR pins in flip-flop.
SHIFT REGISTERS AND COUNTERS:
1. What are registers?
2. What are shift registers?
3. What are the different types of shift registers?
4. Differentiate between SIOP, PISO, PIPO and SISO.
5. Differentiate between a Ring counter and Johnson counter.
6. Why it is called as decade counter?
7. Explain the pins of 7490 IC.
8. Difference between BCD and Binary counter.
9. What is the maximum count of a BCD counter?
10. Mention the steps in designing a counter?
11. Identify the internal components of IC 7490.
R-2R LADDER:
1.
2.
3.
4.
5.
6.
7.

What is ADC? What is DAC?

Mention the types of DAC.
What is the resolution of DAC?
What is the advantage of using R-2R over weighted resistor method?
Which is the fastest ADC? Why?
Mention the types of ADC.
Give some examples of monolithic ADC and DAC.

Dept. of CSE, PESIT Bangalore South Campus

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EC & LD LAB - 10CSL38

2013 - `14

COMPONENT DETAILS
1. DIODE BY 127:

Diodes must be connected the correct way round, the diagram may be labeled a or +
for anode and k or - for cathode (yes, it really is k, not c, for cathode!). The cathode is
marked by a line painted on the body. Diodes are labeled with their code in small print; you
may need a magnifying glass to read this on small signal diodes.
Testing a diode with a DIGITAL Multimeter

Digital Multimeter has a special setting for testing a diode, usually labeled with the diode
symbol.

Connect the red (+) lead to the anode and the black (-) to the cathode. The diode should
conduct and the meter will display a value (usually the voltage across the diode in mV,
1000mV = 1V).

Reverse the connections. The diode should NOT conduct this way so the meter will
display "off the scale" (usually blank except for a 1 on the left).

2. TRANSISTOR:
Testing a transistor with a Multimeter
Set a digital Multimeter to diode test and as described above for testing a diode.
Test each pair of leads both ways (six tests in total):

The base-emitter (BE) junction should behave like a diode and conduct one way only.

The base-collector (BC) junction should behave like a diode and conduct one way only.

The collector-emitter (CE) should not conduct either way.

Testing an NPN transistor

Dept. of CSE, PESIT Bangalore South Campus

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EC & LD LAB - 10CSL38

2013 - `14

Types of transistor:
There are two types of standard transistors, NPN and PNP, with different circuit
symbols. The letters refer to the layers of semiconductor material used to make the transistor.
Most transistors used today are NPN because this is the easiest type to make from silicon.
SL 100 is an NPN transistor.

3. MOSFET:

IR F540

D S

Metal Oxide Semiconductor Field Effect Transistor

Testing a MOSFET
This testing procedure is for use with a digital Multimeter in
the diode test-range with a minimum of 3.3 volt over d.u.t.
(diode-under-test). If your multi-meter is less than that it will
not do the test. Check your meter manual for the specs.
Connect the 'Source' of the MosFet to the meter's negative (-)
lead.
1) Hold the MosFet by the case or the tab but don't touch the metal parts of the test probes
with any of the other MosFet's terminals until needed. Do NOT allow a MOSFET to
come in contact with your clothes, plastic or plastic products, etc. because of the high
static voltages it can generate.
2) First, touch the meter positive lead onto the MosFet's 'Gate'.
3) Now move the positive probe to the 'Drain'. You should get a 'low' reading. The MosFet's
internal capacitance on the gate has now been charged up by the meter and the device is
'turned-on'.
4) With the meter positive still connected to the drain, touch a finger between source and
gate (and drain if you like, it does not matter at this stage). The gate will be discharged
through your finger and the meter reading should go high, indicating a non-conductive
device.

Dept. of CSE, PESIT Bangalore South Campus

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EC & LD LAB - 10CSL38

2013 - `14

4. OP AMP:(OPERATIONAL AMPLIFIER) IC 741

Where:
V+: non-inverting input
V: inverting input
Vout: output
VS+: positive power supply (sometimes also VDD, VCC, or VCC + )
VS: negative power supply (sometimes also VSS, VEE, or VCC )

5. 555 TIMER:

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