Vol. 35, No.

Journal of Semiconductors

February 2014

An effective timing characterization method for an accuracy-proved VLSI standard

cell library 
Jiang Jianhua() , Liang Man(), Wang Lei(), and Zhou Yumei()
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

Abstract: This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard
cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis.
In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition,
the error calculations of some simple circuit path delays are compared between using the characterization file and
an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.
Key words: characteristic parameters; error calculation; look-up table; Lib file
DOI: 10.1088/1674-4926/35/2/025005
EEACC: 2570A; 2570D

1. Introduction
Nowadays the non-linear delay model (NLDM) or the
composite current source timing model (CCS) based look-up
table (LUT) are widely used for static timing analysis (STA).
In those LUTs, the characterization data such as cell delay and
transition time are indexed by a fixed number of input transition time trin and load capacitance Cl values1 . A Synopsys liberty (.lib) format file2; 3 , also known as a timing library file
(Lib file), contains several kinds of LUTs for computing cell
delay. Usually the Lib file is provided by the foundry, however when a designer want to have his own cell library or to
change some parameters in the process, he needs to generate
the lib file himself. For doing this work, the designer should
decide the characteristic parameters (Cl ; trin / of the LUT and
then get the timing information by Hspice simulation or other
EDA tools. After completing the whole librarys characterization, the designer needs to analyze the accuracy of the timing
file for the future work by himself, as no EDA tools can analyze
it automatically.
The accuracy of timing analysis depends on the accuracy
of the delay model used in the cell characterization3 . Highaccuracy timing models allow the designer to reduce guardband margins, thus improve the quality of results and reduce
design iterations4 . The LUT only includes a fixed number of
parameters, for example, the size of 5  5 or 7  7 (Cl ; trin /
pairs, while the delays for the other (Cl ; trin / pairs are obtained
using linear interpolation. As a result, when making a standard cell library of ones own, choosing appropriate characteristic parameters of (Cl ; trin / is the key work for the accuracy
of timing library file. In this paper, some spacing models are
discussed, and the method to validate the accuracy of the characterization is proposed, resulting in the most accurate timing
model. This paper is organized as follows. In Section 2, linear
interpolation and some spacing modes of the index values are
described. In Section 3, the delay calculation of the NLDM is
introduced. In Section 4, a method is proposed to validate the

accuracy of the characterization model, in which the delta delays are calculated between interpolated values and simulation
ones. Section 5 compares two kinds of LUTs by analyzing a
typical circuits delays and proves the validation of the characterization model. The conclusion of this paper is given in
Section 6.

2. Background
2.1. Structure of the non-linear delay model
Figure 1 shows the NLDMs cell delay arc in the timing library file. The cell delay table in this mode is a twodimensional table indexed by input transition time and total
output capacitance5 . The NLDM uses LUTs and linear interpolation to calculate the cell delays. Generally the more indexes in the LUTs, the more precise prediction it can provide.
As a result, this model is able to fulfill the requirements of close
timing correlation with a wide variety of submicron delay modeling schemes3 .
2.2. Delay calculation of the NLDM
Figure 2 is a simple schematic composed by four logic
gates. The delay calculation process of the AND gate U1 in the
schematic is as following. Firstly, the timing arc of U1 should
be examined in the library file to make sure that the propagation

Fig. 1. An example cell delay arc.

* Project supported by the National Science and Technology Major Project (No. 10ZX02305-013-002/10ZX02305-013-004).
Corresponding author. Email: jiangjianhua@ime.ac.cn
Received 5 July 2013, revised manuscript received 28 August 2013
2014 Chinese Institute of Electronics

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Table 1. Coefficient values for fall cell delay.
Coefficient
Value
a
0.1385117
b
0.0449298
c
4.7437053
d
0:2020811

the x; y values (0.62, 0.09) are inserted into Eq. (1) to solve the
fall cell delay z, which is 0.5820 ns.
In some situations the index points in the table cannot
cover the actual values, for example the trin and Cl pairs (3.5,
0.6) are bigger than the maximum points individually. The linear extrapolation is performed by extending the surface formed
by the nearest four data points to cover it. After using the neighboring points (0.39, 2), (0.39, 3), (0.51, 2), (0.51, 3) to get a set
of coefficient values a, b, c and d , data point (3.5, 0.6) needs
to be inserted into Eq. (1) to obtain its propagation delay with
the method described above.

Fig. 2. NLDM calculation schematic.

3. Characterization method
From the NLDMs linear interpolation described above,
it can be found that the distance from the actual values to its
neighboring coordinate points determines the calculation accuracy. Since the size of the LUTs cannot increase unrestrictedly,
the selection of the characteristic parameters becomes important and affects delay calculation directly.

Fig. 3. Coordinate for linear interpolation.

and cell delay tables for this timing arc are specified. After that,
the U1s trin and Cl need to be found. The input transition trin of
U1 is determined by evaluation of the output transition at the
previous gate U0. Because the timing sense in U0 is negative
unate, the rise transition table is adopted for U0 to determine
U1s input transition time. If multiple timing arcs are presented
at gate U0, the maximum of the rise transition values is chosen
as the input transition at U1. On the contrary, the total output capacitance Cl s calculation is easier. It equals the sum of
the capacitance contributed by the pins connected to net1 and
the connecting wire itself. After those calculations, U1s input
transition is determined to be 0.62 ns for example, and the total
output capacitance is 0.09 fC. These two values can be indexed
in the AND gates cell delay table for linear interpolation.
The linear interpolation for the U1 cells delay is depicted
in Fig. 3. Four neighboring values are extracted from the table
by examination of the table breakpoints. The input transition
time 0.62 ns falls between the index values of 0.4 and 0.9. And
the output capacitance 0.09 fC falls between the indexes of 0.06
and 0.15. The index values of the four neighboring values in
the table and their corresponding z values have been marked in
Fig. 3. Besides, the surface surrounded by the four neighboring
values can be described by solving a; b; c, and d coefficients
of Eq. (1).
Next, the coefficient values can be inserted into the equation to determine the cells propagation delay. The four coordinate points (0.4, 0.06, 0.4406209), (0.9, 0.06, 0.4526584),
(0.4, 0.15, 0.8559145), (0.9, 0.15, 0.8632233) are substituted
into Eq. (1). And then the coefficients a; b; c, and d are derived
with common mathematical methods. Table 1 shows the coefficient values for the fall cell delay. The coefficient values and

3.1. Range of the characteristic parameters

As discussed above, if any port/net on a timing path exceeds a value beyond the LUTs range, the STA tool extrapolates the desired value from existing LUT tables. However, the
linear interpolation method does not guarantee the accuracy of
the extrapolated values. In order to improve the accuracy, the
range of the characteristic parameters should be that most of
the points in practice located in the interior of the LUT. The
method of getting the LUTs parameter ranges is as follows.
(1) The output transition time when the largest inverter in
the library drive the smallest one is regarded as the minimum
transition time tmin 6 . (2) The maximum input transition denoted as tmax is obtained from the situation when the smallest
inverter in the library drives the maximum output capacitance.
(3) The minimum output load Cmin is derived from the input
capacitance of the smallest inverter. (4) The maximum output
capacitance is the larger one between 15 times of the minimum
capacitance and four times of the largest input capacitance.
3.2. Lists of characteristic parameters
It is proposed in Ref. [7] that delay varies linearly with
characteristic parameters Cl and trin when these parameters are
within a certain range. However, the characteristic values may
be invariant with indexes in practical applications. The analysis
of an inverter is shown in Figs. 4 and 5 with different characteristic parameters. The simulation results show that the characteristic values vary linearly with output capacitance, but nonlinearly with input transition time, with many inflexion points.
So if the relationship between the output results and characteristic parameters is not linearly as assumed to be, it looks

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Table 2. Correspondence value of MCy and yield.
Distribution
Linear LUT
Logarithmic LUT
Logarithmic
0.0103
0.0087
Uniform
0.0061
0.0088
Normal
0.0055
0.0201

Fig. 4. Variation of characteristic values with output load capacitance

(Cl /. (a) Cell fall. (b) Cell rise. (c) Rise transition. (d) Fall transition.

Fig. 6. Logarithmic distribution histogram.

Fig. 7. Uniform distribution histogram.

Fig. 5. Variation of characteristic values with input transition time

(Cl /. (a) Cell fall. (b) Cell rise. (c) Rise transition. (d) Fall transition.

likely to lead to excessive errors and make the results inaccurate. So the data stored in the table should be selected such that
the interpolation across them yields highly accurate response
times. There are two lists of characteristic parameters provided
in Ref. [8]. One of them is linear, that means the list of input
slew is formed as [tmin ; tmin C a; tmin C 2a; tmin C 3a; tmin C
4a; tmin C 5a; tmin C 6a], in which the (tmin C 6a/ equals tmax ,
The other one is logarithmic, and the list of indexes is created
as [tmin ; 2tmin ; 4tmin ; 8tmin ; 16tmin ; 32tmin ; 64tmin ], in which the
64tmin is tmax . Based on these indexes, more than 100 points
between the max and min value in the table are simulated and
the results are mapped. When there are inflexions in the results,
as shown in Fig. 5, the values between the max and min values
in the index are modified to cover the inflexion points to improve accuracy. After these modifications, accuracy should be
checked to prove the error bound of the interpolated arc of any
row/column (transition/load) in the table.

4. Proposed method of accuracy analysis

After modifying the index value to cover the inflexion
points, the timing lib files accuracy should be checked. This

section presents a novel method to qualify library accuracy.

Error calculations are analyzed as Eq. (2). xsim for a certain
(Cl ; trin / is based on an Hspice simulation; xcal is acquired by
linear interpolation based on the lib file. Three sampling models determining the points (Cl ; trin / are chosen for accuracy analysis and comparison. These sampling models are as follows.
(1) Logarithmic distribution. 100 points of input transitions and
output capacitances are sampled in logarithmic distribution, as
shown in Fig. 6. (2) Uniform distribution. All the sampling
sites are distributed evenly within the limits of the input transition and output capacitance. (3) Normal distribution. This is the
most common distribution in actual application. Each of them
consists of 10000 points, 100 input transitions, and 100 output
capacitances, respectively, within the range of the characteristic parameters. Standard deviation is employed to indicate the
error of the 10000 points according to Eq. (2). One inverter
cells differences for the three kinds of distribution are listed in
Table 2. From the table it can be concluded that the distribution
of sampling points has a great effect on the LUT comparison
results. When the input transition and output capacitance are
sampled under logarithmic distribution, the logarithmic LUT
possesses minimum deviation. Nevertheless, if the characteristic parameters distribute uniformly or normally, the linear LUT
has the lowest error instead. So, one can choose the most accurate LUT according to practical application of the cell library.
More often, cells distributed logarithmically or uniformly are
more reasonable due to the speed and power for ICs.

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In-put

Out-put

N1
N2
N2
N3
N3
N6
N6
N7

N22
N22
N23
N22
N23
N22
N23
N23

Table 3. Correspondence value of MCy and yield.

Linear LUT (ns)
Simulation (ns)
Delay
Error
0.3553
0.3443
0.0110
0.3407
0.3343
0.0067
0.3347
0.3249
0.0098
0.6232
0.6129
0.0103
0.6376
0.6222
0.0154
0.6895
0.6680
0.0215
0.7062
0.6773
0.0289
0.3000
0.2900
0.0100

Logarithmic LUT (ns)

Delay
Error
0.3500
0.0053
0.3407
0.0000
0.3307
0.0040
0.6289
0.0057
0.6481
0.0105
0.6840
0.0055
0.7032
0.0030
0.2971
0.0029

Fig. 8. Normal distribution histogram.

Fig. 10. Layout of C17.

from ICC and Hspice, and the errors of the ICCs reports are
computed. All the relevant data are summarized in Table 3.
As shown in Table 3, the delays of all the paths show one
quarter to one half less error in logarithmic LUTs than in a linear one. This comparison result dominates the advantage of the
logarithmic structure in the LUT of this library.

6. Conclusion
Fig. 9. Schematic of C17.

D

v
uP
u n
u
.x
t iD1 i
n

x/2
1

xi D xcal

xsim :

(1)

5. Circuit verification
The circuits marked C17 in ISCAS85 are applied to ascertain the correctness of the proposed approach. Figure 9 is
C17s schematic.
The verification method is as follows. (1) Synthesize the
circuit C17 using linear and logarithmic LUT timing libraries,
respectively, complete the layout and report their timing by using an IC Compiler. Figure 10 is its layout. The propagation delays of all the paths from inputs to outputs in both implementations are listed in Table 3. (2) Simulate the circuit C17 by using
Hspice, and emulate the delay of all the paths between the input and the output as listed in Table 3. (3) Compare the results

This paper investigates some important questions of the

standard cell characterization. It focuses on the issues of selection of characteristic parameters associated with the distribution in practical application. A novel approach also has been
presented to qualify the accuracy of the characterization model
combined the interpolation of calculation and simulation by using Hspice. A simple circuit path has been implemented and
validated under this method. In short, these methods are simple and effective to determine the table index value and make
a highly accurate timing characterization file.

References
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[3] Scheffer L. EDA for IC implementation, circuit design, and process technology. Addision-Wesley, Reading
[4] Gao Mingzhi, Ye Zuochang, Wang Yan, et al, On modeling the

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digital gate delay under process variation. Journal of Semiconductors, 2011, 32(7): 075010
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