UNIT V

Serial communication standards:

Most of the microprocessors are designed for parallel communication. In parallel communication
for transferring each bit requires one cable, so for transferring large amount of data for long
distances increases cost of cabling which is impractical solution. In such situations serial
communication can be used which uses one single line for transmission of entire databut one bit
after another only.
Serial communication can be classified in to three types based on how transmission can
be done:
Simplex: In simplex, data transmission can be done in only one direction i.e. from transmitter to
receiver only.
Eg: From computer to the printer
Half Duplex: This type of data transmission allows data transfer in both directions but not
simultaneously.
Eg: Walkie talkie
Full Duplex: This type of data transmission allows data transfer in both directions
simultaneously.
Eg: Telephone line
Transmission formats:The data in the serial communication can be sent in two formats
i.e.Asynchronous and Synchronous.
Asynchronous transmission: In this the bits of a character or word can be sent at a constant
rate. When no charaters are being sent a line stays at logic HIGH called MARK (STOP) and
logic LOW called SPACE (START) .
The beginning of a character is indicated by a START bit which is always LOW. This is
used to synchronize the transmitter and receiver. After the start bit, the data bits are sent with
LSB first , followed by one or more stop bits. The combination of start bit, character and stop
bits is called FRAME.

Figure 1: Transmission format for Asynchronous transmission

Synchronous transmission: The start and stop bits in each frame format represents overhead
bytes that reduce the overall character rate. This overhead bits can be eliminated by
synchronizing receiver and transmitter through common clock signal such a communication is
called Synchronous serial communication.

Figure 2: Synchronous serial transmission format

Synchronous bits are inserted instead of start and stop bits. Here a pair of SYNC bits are
used at the start of data frame.

Comparison between Asynchronous and synchronous transmission formats

UNIVERSAL ASYNCHRONOUS SYNCHRONOUS RECEIVER AND

TRANSMITTER (USART 8251A):
To implement saerial communication in microprocessor system, we need two converters
i.e. Parallel to Serial converter and Serial to parallel converter.
To provide this conversion UART and USART devices are designed. UART can be used
for only asynchronous transmission where as USART can be used for both asynchronous and
synchronous transmissions.
Features:
1. It supports Asynchronous standard protocol with:
5 to 8 bit character format
Odd or even parity generation and detection
Baud rate from DC to 19.2k
False start bit detection
2. It supports Asynchronous standard protocol with:
5 to 8 bit character format
Internal or external character synchronization
Automatic SYNC insertion

3.
4.
5.
6.

Baud rate from DC to 64k baud

It has built in baud generator
It allows full duplex transmission and reception
It provides error detection logic, which detects parity , overrun and framing errors.
It has modem control logic which supports basic data set control signals.

Block diagram:

Figure : Block Diagram of USART

Data buffer: This buffer is used to interface 8251A to the system bus. Data is transmitted or
received up on execution of input and output instruction of the CPU. Command and status
information are also transferred through this data buffer.
Read/Write Control logic:
Reset: A high on this pin forces 8251A in to an idle condition.
CLK (clock): The clock input is used to generate internal device timing.
C/ (Control/Data): This input informs the 8251A that the data on the data bus is either a data or
control word/ status information.
(Chip Select): If it is high no read or write operation can be carried out on 8251A.

Operation between CPU and 8251:

Modem Control:
(Data Set Ready): Its status can be checked by the CPU using a status read operation. It is
used to check data set is ready for communicating with modem.
(Data Terminal Ready): This is used to indicate that the device is ready to accept data when
8251A is communicating with modem.
(Clear To Send): This signal enables to transmit serial data when TXE bit is set to 1.
(Request To Send): This signal indicates the beginning of transmission.
Transmitter signals:
Transmitter buffer: The transmitter buffer accepts parallel data from data bus buffer converts it
to a serial bit stream and outputs a composite serial bit stream on TXD for transmission.
Transmitter Control:
TXRDY (Transmitter Ready): This output signals the CPU that the buffer is empty and USART
is ready to accept a data character. This signal is reset when buffer is loaded with data byte.
TXEMPTY (Transmitter Empty): While transmitting USART has no characters to transmit then
this signal can be high and it automatically goes low when a character is received from CPU.
In synchronous mode, high on this pin indicates that a character is not loaded properly
and SYNC characters are used as filters. TXE can be used to indicate end of transmission.
(Transmitter clock): This transmitter clock controls the rate at which the character is to be
transmitted.
Receiver signals:
Receiver buffer: Receiver buffer receives serial data stream on the RXD line, converts serial data
stream to parallel data stream.
Receive Control: It performs false start bit detection, parity error detection, sync detection and
break detection.
RXRDY (Receiver Ready): This signal is made high when USART has a character in the buffer
register and is ready to transfer it to the CPU.
To set RXRDY in asynchronous mode, the receiver must be enabled to sense start bit and a
complete character must be assembled and then transferred to the data output register.
To set RXRDY in synchronous mode, the receiver must be enabled and a complete character
must be assembled and then transferred to the data output register.

If the data was not successfully read from data output register before assembly of the next data
byte, overrun condition error flag is set i.e. previous byte is overwritten by the next byte of the
incoming data and hence it is lost.
(Receiver clock): This receiver clock controls the rate at which the character is to be
received.
SYNDET/BRKDET: This pin is used in the synchronous mode SYNC characters (SYNDET)
and it can be used either as input or output.
When used as an output, the SYNDET pin will go high which indicates that a SYNC
character is located in the receive mode.
When this is used as an input, positive going signal will cause 8251A to start assembling
a data character on the rising edge of the next RXC.
In asynchronous mode this pin acts as a BRKDET, a high on this pin goes low for RXD
through two consecutive stop bit sequences. If RXD is high, it provides break during last bit of
next character.
8251 Registers: The 8251 contains the following registers
Mode Instruction Register
Command Instruction Register
Status Register
Sync Character One Register
Sync Character Two Register
Transmitter Buffer Register
Receive Buffer Register

Sync Character One Register: The sync character one register holds the first sync
character. This information is used by the receiver for sync comparison and by the transmitter for
sync character transmission.
Sync Character Two Register: The sync character two register holds the first sync
character. This information is used by the receiver for sync comparison and by the transmitter for
sync character transmission.
Transmitter Buffer Register (TBR): This register holds the transmitter data, in which
8251 formats, serializes and transmits on the TXD. Once the existing data bits in the shift
register are completely transmitted, the TBR transfers new data in to the shift register.
Receive Buffer Register (RBR): This register holds the data received from the shift
register. After the shift register receives a new data word, it is ready to transfer the new data
word to the RBR. If the existing data in the RBR has already been read by the microprocessor,
then the transfer takes place. If RBR data has not been read, the overrun flag is set.

Operating modes of 8251A:

Control words of 8251A: The control word defines the functionality of 8251A, so they must be
loaded before any transmission or reception. The control words of 8251A can be split into two
formats: 1. Mode instruction 2. Command instruction
Mode instruction: The instruction can be considered as four 2 bit fields.

Figure: Mode instruction format

D0 D1 determines whether the USART has to operate in synchronous (00) or asynchronous
mode (01, 10, and 11). In asynchronous mode this field determines the baud rate based on clock.
D2 D3 determines the number of data bits in one character. With this field we can set character
length ranging from 5 to 8 bits.
D4 D5 controls the parity generation. The parity bit is added to data bits only if parity is
enabled.
D6 D7 these bits can perform different functions depending on mode of transmission. In
asynchronous mode, it controls number of stop bits to be transmitted with the character. In
synchronous mode, it controls the synchronizing process i.e. to transmit single or two
synchronizing characters.
Command instruction: After selecting the mode, command character should be transmitted to
USART. It is used to enable transmit / receive, error reset and modem control.

Figure: Command word format

Status word of 8251A: It is necessary for CPU to monitor the status of transmitter and receiver
to know any error has occurred.

Figure: Status word format

Asynchronous transmission: When a data character is sent to USART by the CPU, it adds start
bit prior to serial data bits followed by optional parity and stop bits using asynchronous control

Figure: Transmitter output in asynchronous mode

word format. This sequence can be transmitted using TXD output pin on the falling edge of
i.e. by enabling transmission enable bit to 0 in the command instruction and
= 0 then
transmitter is ready to transfer data on TXD line.
Asynchronous reception: The RXD is normally high, when USART receives low level it
assumes that it is a start bit and enables internal counter. At a count equivalent to one half of a
bit time it checks the validity of a start bit, is it still exists low on RXD line then it goes to
assemble the character.

Figure: Receiver input in asynchronous mode

The bit counter identifies the data bits, parity bit and stop bit. If a parity error occurs,
parity error flag is set. If a low level is detected as the stop bit, the framing error flag is set. The
receiver requires only one stop bit to mark end of character.
This 8 bit character is loaded into parallel I / O buffer of 8251A. RXRDY pin is then
raised high to indicate CPU that a character is ready for it.
Synchronous mode: The TXD output is high until CPU sends a character to USART which is a
SYNC character. When
line goes low the first character is serially transmitted out. All
characters are shifted out on the falling edge of
.
Once transmission has started, the data stream at the TXD output must continue at the
rate. If CPU does not provide USART with a data character before transmitter buffer
becomes empty, SYNC characters will be automatically inserted in the TXD data stream.
TXEMPTY is made high to indicate CPU that transmitter buffer is empty. TXEMPTY can be
reset when CPU writes data character in the transmitter buffer.
Synchronous reception: Reception can be enabled by setting receive enable bit (bit 2) in the
command instruction. In this mode, character synchronization can be achieved internally or
externally.

Figure: Insertion of SYNC characters

Internal SYNC to detect SYNC character USART should be programmed in the Enter
Hunt mode by setting bit 7 in command instruction. In Hunt mode USART starts sampling data
on the RXD pin on the rising edge of
. The content receive buffer is compared at every bit
boundary with the first SYNC character until a match occurs. Whenever match occurs SYNDET
pin goes high.
Once USART detects SYNC characters it enters from Hunt mode to character
synchronization mode and starts receiving data characters.
External SYNC synchronization can be achieved by applying a high level on SYNDET
pin that forces USART out of hunt mode.
Interface the ASCII encoded keyboard with the microprocessor 8086, and write an ALP to
transmit a string of ASCII character. The starting memroy location is 5000:0200H. The
baud rate should be 300 bits per second and transmitter frequency is 4.8 KHZ. Use 1
stop bits. Interface the 8251 with the microprocessor from address 00H and use NAND gate
to generate chip select. Perform data transform using polling technique.
Step I: Address decoding table

Step III: Interfacing of 8251 USART with 8086 to TTY printer:

If the stop bit is given it specifies that is a asynchronous mode of data transfer
Mode word for asynchronous mode:
Baud rate = 300bps
Clock requency = 4.8 KHZ = 4800 Hz = 16 * Baud rate

Command word to enable transmitter:

Main Program:
MOV AX, 5000H
MOV DS, AX
MOV SI, 0200H
MOV SS, AX
MOV SP, 0000H
MOV AL, 00H
OUT 02H, AL
OUT 02H, AL
OUT 02H, AL
MOV AL, 8AH
OUT 02H, AL
MOV AL, 01H
OUT 02H, AL

RESET REGISTERS

INITIALIZE MODE WORD

INITIALIZE COMMAND WORD

L1:
CALL TRANS
; SUB PROGRAM WILL TRANSMIT DATA IF
TXRDY =1
INC SI
CMP AL, 7FH
; COMPARE AL FOR CARRIAGE RETURN
JNZ L1
INT 03H
Sub program: This program will check the value of TXRDY pin, if TXRDY = 1then 8 bits
of data of memory is transferred to transmitter.
TRANS:
IN AL, 02H
; READ STATUS REGISTER (D0 = TXRDY)
RCR AL, 01H
; TXRDY ---------> CF
JNC TRANS
; CF = 0
MOV AL, [SI]
; SI = 0200H CONTAINS 41 (A)
OUT 00H, AL
RET
Interface the ASCII encoded keyboard with the microprocessor 8086, and write an ALP to
input and store ASCII codes from memory address 5000:0200H. The data is to be received
at 110 baud rate and receiver frequency should be 64 * (the clock frequency = 64 * baud
rate). Use two stop bits. The carriage return character is 0DH. Perform data transferring
using status check (polling technique).

Step I: Address decoding table

Step II: Generate chip select

Step III: Interfacing of 8251 with microprocessor 8086 to ASCII keyboard

Mode word format for asynchronous mode to transfer 2 stop bits, 7 bits (ASCII) and 64 baud rate
is

Command word to make error reset and enable receiver is

Main Program:
MOV AX, 5000H
MOV DS, AX
MOV SI, 0200H
MOV SS, AX
MOV SP, 0000H
MOV AL, 00H
MOV DX, 4002H
OUT DX, AL
OUT DX, AL

RESET REGISTERS

OUT DX, AL
MOV AL, 0CBH
;
INITIALIZE MODE WORD
OUT DX, AL
MOV AL, 14H
OUT DX, AL
;
INITIALIZE COMMAND WORD
L1:
CALL RX
; SUB PROGRAM WILL RECEIVE DATA IF
RXRDY =1
INC SI
CMP AL, 0DH
; COMPARE AL FOR CARRIAGE RETURN
JNZ L1
INT 03H
Sub program: This program will check the value of RXRDY pin, if RXRDY = 1then 8 bits
of data of memory is transferred to transmitter.
RX:
IN AL, DX
; READ STATUS REGISTER (D1 = RXRDY)
RCR AL, 02H
; RXRDY ---------> CF
JNC RX
MOV DX, 4000H
; CF = 0
IN AL, DX
; SI = 0200H CONTAINS 41 (A)
MOV [SI], AL
RET
Interface one serial input device with the microprocessor 8086. Write an ALP to input and
store 100 characters in synchronous mode from memory address 5000:0200H. Each
character should be received in odd parity, 5 bits length and 1200 baud rate. Synchronous
character is 1FH.

Step I: Address decoding table

Step II: Generation of Chip selection

Step III: Interfacing of 8251 with microprocessor 8086 to input device

1. Mode word format for the synchronous mode

2. Synchronous character = 1FH

3. Command word to make error reset, receiver enable and enable enter hunt mode

Synchronous character is checked by receiver. It means that it is checked internally,

therefore, to check this synchronous character for this receiver is hunting hence to enable
internal check EH = 1.
First check the value of SYNDET pin and if SYNDET = 1 i.e. synchronous
character is detected, then check the value of RXRDY pin, and when the RXRDY = 1,
then read data from receiver buffer register.
Main Program:
MOV AX, 5000H
MOV DS, AX
MOV SI, 0200H
MOV SS, AX
MOV SP, 0000H
MOV AL, 00H
OUT 02H, AL
OUT 02H, AL
OUT 02H, AL
MOV AL, 90H
OUT 02, AL
MOV AL, 1FH
OUT 02H, AL
MOV AL, 94H
OUT 02, AL

RESET REGISTERS

INITIALIZE MODE WORD

SYNCHRONOUS CHARACTER SC1

INITIALIZE COMMAND WORD

L1:
(D6 )

IN AL, 02

; READ STATUS WORD TO CHECK SYNDET

RCL AL, 02
JNC L1
; CHECK SYNCHRONOUS CHARACTER
L2:
CALL RX
; SUB PROGRAM WILL RECEIVE DATA IF
RXRDY =1
INC SI
DEC CL
JNZ L2
INT 03H
Sub program: This program will check the value of RXRDY pin, if RXRDY = 1then 8 bits
of data of memory is transferred to transmitter.
RX:
IN AL, 02
; READ STATUS REGISTER (D1 = RXRDY)
RCR AL, 02H
; RXRDY ---------> CF
JNC RX
; CF = 0
IN AL, 00H
; READ BITS FROM DATA PORT
MOV [SI], AL
RET

RS-232 INTERFACE
The RS-232 interface is the Electronic Industries Association (EIA) standard
for the interchange of serial binary data between two devices. It was initially
developed by the EIA to standardize the connection of computers with telephone
line modems. The standard allows as many as 20 signals to be defined, but gives
complete freedom to the user. Three wires are sufficient: send data, receive data,
and signal ground. The remaining lines can be hardwired on or off permanently.
The signal transmission is bipolar, requiring two voltages, from 5 to 25 volts, of
opposite polarity.
The standard RS-232-C connector has 25 pins, 21 pins which are used in the
complete standard. Many of the modem signals are not needed when a computer
terminal is connected directly to a computer and Figure 1 illustrate show some of
the "spare" pins should be linked if not needed. Figure 1 also illustrates the pin
numbering used in the original DB-25 connector and that now commonly used with
a DB-9 connector normally used in modern computers.

Direct to computer RS-232 interface

A 25 wire cable could be used to connect the Data Terminal Equipment (DTE) to the
Data Communication Equipment (DCE). The DTE is a device that is acting as a data
source, data sink, or both, e.g. a terminal, peripheral or computer. The DCE is a
device that provides the functions required to establish, maintain, and terminate a
data-transmission connecting, as well as the signal conversion, and coding required
for communication between data terminal equipment and data circuit; e.g. a
modem.

Pin Description:

The RS-232-C specifies the signaling rate between the DTE and DCE, and a digital
signal is used on all interchange circuits. The RS-232 standard specifies that logic
"1" is to be sent as a voltage in the range -15 to -5 V and that logic "0" is to sent
as a voltage in the range +5 to +15 V. The standard specifies that voltages of at
least 3 V in amplitude will always be recognized correctly at the receiver according
to their polarity, so that appreciable attenuation along the line can be tolerated.
The RS-232-C standard specifies that the maximum length of cable between the
transmitter and receiver should not exceed 100 feet.
When communicating with various microprocessors one needs to convert the
RS232 levels down to lower levels, typically 3.3 or 5.0volts.
Serial RS-232 communication works with voltages -15V to +15V for high and
low. On the other hand, TTL logic operates between 0V and +5V. Modern low power
consumption operates in the range of 0V and +3.3V or even lower. To receive serial
data from an RS232 interface the voltage has to be reduced. Hence some voltage
converters are necessary which can be referred to as Line Drivers. MAX 232 can act
as line drivers.Max232 voltage levels can be +5V or 3.3V. MAX232 converts RS232
voltage levels to compatible TTL voltage levels.